SN54ALS74A_08_技术文档

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ꢉ ꢊꢄꢅꢈꢋ ꢌ ꢀꢍꢎ ꢍꢏ ꢐꢑꢐꢉ ꢒꢐ ꢑꢎ ꢓꢍꢒ ꢒ ꢐꢓꢐ ꢉꢈꢉ ꢑꢎ ꢔꢋꢐ ꢈꢕ ꢅꢍ ꢋ ꢑ ꢕꢅꢌ ꢋ ꢀ

ꢖ ꢍꢎ ꢗꢈ ꢘꢅꢐ ꢄꢓꢈꢄꢁꢉꢈ ꢋ ꢓꢐ ꢀ ꢐꢎ

SDAS143C − APRIL 1982 − REVISED AUGUST 1995

SN54ALS74A, SN54AS74A . . . J PACKAGE

SN74ALS74A, SN74AS74A . . . D OR N PACKAGE

(TOP VIEW)

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

1CLR

1D

1CLK

1PRE

1Q

V

CC

2CLR

1

2

3

4

5

6

7

14

13

12

11

10

9

TYPICAL MAXIMUM

CLOCK FREQUENCY

TYPICAL POWER

2D

DISSIPATION

PER FLIP-FLOP

(mW)

TYPE

2CLK

2PRE

2Q

(C = 50 pF)

L

(MHz)

50

1Q

GND

′ALS74A

′AS74A

6

2Q

8

134

26

description

SN54ALS74A, SN54AS74A . . . FK PACKAGE

(TOP VIEW)

These devices contain two independent

positive-edge-triggered D-type flip-flops. A low

level at the preset (PRE) or clear (CLR) inputs sets

or resets the outputs regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the data (D) input meeting the

setup-time requirements are transferred to the

outputs on the positive-going edge of the clock

(CLK) pulse. Clock triggering occurs at a voltage

level and is not directly related to the rise time of

CLK. Following the hold-time interval, data at the

D input can be changed without affecting the

levels at the outputs.

3

2

1

20 19

18

1CLK

NC

2D

17 NC

4

5

6

7

8

16

15

14

1PRE

NC

2CLK

NC

1Q

2PRE

9 10 11 12 13

NC − No internal connection

The SN54ALS74A and SN54AS74A are

characterized for operation over the full military

temperature range of −55°C to 125°C. The

SN74ALS74A and SN74AS74A are characterized

for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

L

CLR

CLK

X

D

X

H

L

Q

H

L

Q

L

H

L

H

X

H

†

H

L

X

H

↑

H

L

H

↑

H

L

X

Q

0

†

The output levels in this configuration are not

specified to meet the minimum levels for V if the

OH

lows at PRE and CLR are near V maximum.

IL

Furthermore, this configuration is nonstable; that

is, it does not persist when PRE or CLR returns to

its inactive (high) level.

ꢋ

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ꢉ

ꢄ

ꢎ

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Copyright  1995, Texas Instruments Incorporated

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ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢃ ꢄꢇ ꢈ ꢀ ꢁꢂ ꢃꢄ ꢀ ꢆ ꢃ ꢄꢇ ꢈꢀ ꢁꢆ ꢃ ꢄꢅꢀ ꢆ ꢃ ꢄꢇꢈ ꢀ ꢁꢆ ꢃ ꢄꢀ ꢆ ꢃ ꢄ

ꢉ ꢊ ꢄꢅꢈ ꢋꢌꢀ ꢍ ꢎꢍ ꢏ ꢐꢑꢐ ꢉꢒ ꢐ ꢑꢎꢓꢍ ꢒ ꢒ ꢐ ꢓꢐ ꢉꢈꢉ ꢑꢎ ꢔꢋꢐ ꢈꢕ ꢅꢍ ꢋ ꢑꢕ ꢅꢌ ꢋ ꢀ

ꢖꢍ ꢎ ꢗ ꢈꢘ ꢅ ꢐꢄ ꢓꢈꢄꢁ ꢉꢈ ꢋ ꢓꢐ ꢀꢐ ꢎ

SDAS143C − APRIL 1982 − REVISED AUGUST 1995

†

logic symbol

4

5

6

9

8

S

1PRE

1CLK

1D

1Q

2Q

3

2

1

C1

1D

R

1CLR

10

11

12

13

2PRE

2CLK

2D

2CLR

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

logic diagram (positive logic)

PRE

CLR

Q

CLK

D

‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

CC

Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

I

Operating free-air temperature range, T : SN54ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

A

SN74ALS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢃ ꢄꢇ ꢈ ꢀꢁꢂ ꢃ ꢄꢀꢆ ꢃ ꢄ ꢇꢈꢀ ꢁꢆ ꢃ ꢄꢅ ꢀꢆ ꢃ ꢄ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢀ ꢆꢃꢄ

ꢉꢊꢄ ꢅꢈꢋ ꢌ ꢀꢍꢎ ꢍꢏ ꢐꢑꢐꢉ ꢒꢐ ꢑꢎ ꢓꢍꢒ ꢒ ꢐꢓꢐ ꢉꢈꢉ ꢑꢎ ꢔꢋꢐ ꢈꢕ ꢅꢍ ꢋ ꢑ ꢕꢅꢌ ꢋ ꢀ

ꢖ ꢍꢎ ꢗꢈ ꢘꢅꢐ ꢄꢓꢈꢄꢁꢉꢈ ꢋ ꢓꢐ ꢀ ꢐꢎ

SDAS143C − APRIL 1982 − REVISED AUGUST 1995

recommended operating conditions

SN54ALS74A

MIN NOM MAX

SN74ALS74A

MIN NOM MAX

UNIT

V

Supply voltage

4.5

2

5

5.5

4.5

2

5

5.5

V

CC

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Clock frequency

IH

0.7

−0.4

4

0.8

−0.4

8

V

IL

I

f

mA

MHz

OH

OL

clock

0

25

0

15

34

PRE or CLR low

CLK high

CLK low

15

17.5

16

14.5

15

t

w

Pulse duration

ns

Data

t

Setup time before CLK↑

su

PRE or CLR inactive

Data

10

Hold time after CLK↑

2

0

ns

h

T

A

Operating free-air temperature

−55

125

0

70

°C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54ALS74A

SN74ALS74A

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

= 4.5 V,

I = −18 mA

−1.5

V

IK

CC

I

= 4.5 V to 5.5 V,

I

= −2 mA

= 4 mA

= 8 mA

V

CC

−2

V

CC

−2

OH

CC

OH

OL

0.25

0.4

0.25

0.35

0.4

0.5

V

OL

V

CC

V

CC

V

CC

V

CC

= 4.5 V

= 4.5 V,

V

CLK or D

0.1

0.2

0.1

I

V = 7 V

I

mA

µA

mA

I

PRE or CLR

CLK or D

0.2

20

V = 2.7 V

I

IH

IL

PRE or CLR

CLK or D

40

−0.2

−0.4

−112

4

−0.2

−0.4

−112

4

V = 0.4 V

I

PRE or CLR

‡

I

V

= 5.5 V,

V = 2.25 V

O

−20

−30

mA

O

CC

See Note 1

2.4

CC

†

‡

All typical values are at V

CC

= 5 V, T = 25°C.

A

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I

.

OS

NOTE 1:

I

is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded.

CC

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢃ ꢄꢇ ꢈ ꢀ ꢁꢂ ꢃꢄ ꢀ ꢆ ꢃ ꢄꢇ ꢈꢀ ꢁꢆ ꢃ ꢄꢅꢀ ꢆ ꢃ ꢄꢇꢈ ꢀ ꢁꢆ ꢃ ꢄꢀ ꢆ ꢃ ꢄ

ꢉ ꢊ ꢄꢅꢈ ꢋꢌꢀ ꢍ ꢎꢍ ꢏ ꢐꢑꢐ ꢉꢒ ꢐ ꢑꢎꢓꢍ ꢒ ꢒ ꢐ ꢓꢐ ꢉꢈꢉ ꢑꢎ ꢔꢋꢐ ꢈꢕ ꢅꢍ ꢋ ꢑꢕ ꢅꢌ ꢋ ꢀ

ꢖꢍ ꢎ ꢗ ꢈꢘ ꢅ ꢐꢄ ꢓꢈꢄꢁ ꢉꢈ ꢋ ꢓꢐ ꢀꢐ ꢎ

SDAS143C − APRIL 1982 − REVISED AUGUST 1995

switching characteristics (see Figure 1)

V

C

R

= 4.5 V to 5.5 V,

= 50 pF,

CC

L

= 500 Ω,

FROM

TO

(OUTPUT)

†

PARAMETER

(INPUT)

UNIT

T

A

= MIN to MAX

SN54ALS74A SN74ALS74A

MIN

25

3

MAX

MIN

34

3

MAX

f

t

MHz

ns

max

PLH

PHL

PLH

PHL

18

17

23

20

13

15

16

18

PRE or CLR

CLK

Q or Q

5

ns

5

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

CC

Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

I

Operating free-air temperature range, T : SN54AS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

A

SN74AS74A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54AS74A

MIN NOM

SN74AS74A

MIN NOM

UNIT

MAX

V

Supply voltage

4.5

2

5

5.5

4.5

2

5

5.5

V

CC

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Clock frequency

IH

0.8

−2

20

90

0.8

−2

V

IL

I

f

mA

MHz

OH

OL

clock

20

*

0

4

0

4

105

PRE or CLR low

CLK high

4

t *

w

Pulse duration

ns

CLK low

5.5

4.5

2

5.5

4.5

2

Data

t

su

*

Setup time before CLK↑

PRE or CLR inactive

Data

t *

h

Hold time after CLK↑

0

ns

T

A

Operating free-air temperature

−55

125

0

70

°C

* On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢃ ꢄꢇ ꢈ ꢀꢁꢂ ꢃ ꢄꢀꢆ ꢃ ꢄ ꢇꢈꢀ ꢁꢆ ꢃ ꢄꢅ ꢀꢆ ꢃ ꢄ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢀ ꢆꢃꢄ

ꢉꢊꢄ ꢅꢈꢋ ꢌ ꢀꢍꢎ ꢍꢏ ꢐꢑꢐꢉ ꢒꢐ ꢑꢎ ꢓꢍꢒ ꢒ ꢐꢓꢐ ꢉꢈꢉ ꢑꢎ ꢔꢋꢐ ꢈꢕ ꢅꢍ ꢋ ꢑ ꢕꢅꢌ ꢋ ꢀ

ꢖ ꢍꢎ ꢗꢈ ꢘꢅꢐ ꢄꢓꢈꢄꢁꢉꢈ ꢋ ꢓꢐ ꢀ ꢐꢎ

SDAS143C − APRIL 1982 − REVISED AUGUST 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54AS74A

SN74AS74A

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

CC

V

CC

V

CC

V

CC

= 4.5 V,

I = −18 mA

−1.2

V

IK

I

= 4.5 V to 5.5 V,

= 4.5 V,

I

= −2 mA

= 20 mA

V

CC

−2

V

CC

−2

OH

OL

OH

OL

I

0.25

0.5

0.1

0.25

0.5

0.1

V

I

= 5.5 V,

V = 7 V

I

mA

CLK or D

20

I

V

= 5.5 V,

V = 2.7 V

µA

IH

IL

CC

I

PRE or CLR

CLK or D

40

−0.5

−1.8

−112

16

−0.5

−1.8

−112

16

I

V

V = 0.4 V

I

mA

PRE or CLR

‡

I

V

= 5.5 V,

V = 2.25 V

O

−30

mA

O

CC

See Note 1

10.5

CC

†

‡

All typical values are at V

CC

= 5 V, T = 25°C.

A

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I

.

OS

NOTE 1:

I

is measured with D, CLK, and PRE grounded, then with D, CLK, and CLR grounded.

CC

switching characteristics (see Figure 1)

V

C

R

= 4.5 V to 5.5 V,

= 50 pF,

CC

L

= 500 Ω,

FROM

TO

(OUTPUT)

§

PARAMETER

(INPUT)

UNIT

T

A

= MIN to MAX

SN54AS74A

SN74AS74A

MIN

90

MAX

MIN

105

2

MAX

f

t

*

MHz

ns

max

2

9

11.5

10

7.5

10.5

8

PLH

PHL

PLH

PHL

PRE or CLR

CLK

Q or Q

2.5

3.5

2.5

3

ns

10.5

3

9

* On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested.

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢃ ꢄꢇ ꢈ ꢀ ꢁꢂ ꢃꢄ ꢀ ꢆ ꢃ ꢄꢇ ꢈꢀ ꢁꢆ ꢃ ꢄꢅꢀ ꢆ ꢃ ꢄꢇꢈ ꢀ ꢁꢆ ꢃ ꢄꢀ ꢆ ꢃ ꢄ

ꢉ ꢊ ꢄꢅꢈ ꢋꢌꢀ ꢍ ꢎꢍ ꢏ ꢐꢑꢐ ꢉꢒ ꢐ ꢑꢎꢓꢍ ꢒ ꢒ ꢐ ꢓꢐ ꢉꢈꢉ ꢑꢎ ꢔꢋꢐ ꢈꢕ ꢅꢍ ꢋ ꢑꢕ ꢅꢌ ꢋ ꢀ

ꢖꢍ ꢎ ꢗ ꢈꢘ ꢅ ꢐꢄ ꢓꢈꢄꢁ ꢉꢈ ꢋ ꢓꢐ ꢀꢐ ꢎ

SDAS143C − APRIL 1982 − REVISED AUGUST 1995

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7 V

R

= R1 = R2

V

CC

L

S1

R1

R

L

Test

Point

From Output

Under Test

From Output

Under Test

Test

Point

Test

Point

From Output

Under Test

C

L

R

L

R2

L

C

L

(see Note A)

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

3.5 V

Timing

Input

High-Level

1.3 V

Pulse

0.3 V

t

w

h

t

su

3.5 V

0.3 V

Data

Input

Low-Level

1.3 V

Pulse

0.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

3.5 V

Output

Control

(low-level

enabling)

1.3 V

0.3 V

3.5 V

t

PZL

Input

1.3 V

t

PLZ

0.3 V

PHL

[3.5 V

t

Waveform 1

S1 Closed

(see Note B)

t

PLH

1.3 V

V

OH

In-Phase

Output

1.3 V

V

OL

V

OL

0.3 V

t

PHZ

t

PLH

t

PZH

t

PHL

V

OH

V

Waveform 2

S1 Open

(see Note B)

OH

OL

Out-of-Phase

Output

(see Note C)

1.3 V

0.3 V

V

[0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. When measuring propagation delay items of 3-state outputs, switch S1 is open.

D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.

r

f

E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

LCCC

CDIP

CFP

Drawing

5962-9862701Q2A

5962-9862701QCA

84011012A

ACTIVE

FK

J

20

14

20

14

20

14

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB N / A for Pkg Type

POST-PLATE N / A for Pkg Type

FK

J

8401101CA

A42 SNPB

A42

N / A for Pkg Type

8401101DA

W

FK

J

JM38510/37101B2A

JM38510/37101BCA

SN54ALS74AJ

SN54AS74AJ

LCCC

CDIP

SOIC

POST-PLATE N / A for Pkg Type

A42 SNPB

N / A for Pkg Type

J

SN74ALS74AD

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ALS74ADE4

SN74ALS74ADG4

SN74ALS74ADR

ACTIVE

SOIC

D

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ALS74ADRE4

SN74ALS74ADRG4

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74ALS74AJ

SN74ALS74AN

OBSOLETE

ACTIVE

CDIP

PDIP

J

14

TBD

Call TI

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74ALS74AN3

SN74ALS74ANE4

OBSOLETE

ACTIVE

PDIP

N

14

TBD

Call TI

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74ALS74ANSR

SN74ALS74ANSRE4

SN74ALS74ANSRG4

SN74AS74AD

ACTIVE

SO

NS

D

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

PDIP

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74AS74ADE4

SN74AS74ADG4

SN74AS74ADR

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74AS74ADRE4

SN74AS74ADRG4

SN74AS74AN

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

Orderable Device

SN74AS74ANE4

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

PDIP

N

14

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74AS74ANSR

SN74AS74ANSRE4

SN74AS74ANSRG4

SO

NS

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SNJ54ALS74AFK

SNJ54ALS74AJ

SNJ54ALS74AW

SNJ54AS74AFK

SNJ54AS74AJ

ACTIVE

LCCC

CDIP

CFP

FK

J

20

14

20

14

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

FK

J

LCCC

CDIP

POST-PLATE N / A for Pkg Type

A42 SNPB N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

SN74ALS74ADR

SN74ALS74ANSR

SN74AS74ADR

SN74AS74ANSR

SOIC

SO

D

NS

D

14

2500

2000

2500

2000

330.0

16.4

6.5

8.2

6.5

8.2

9.0

10.5

9.0

2.1

2.5

2.1

2.5

8.0

12.0

8.0

16.0

Q1

SOIC

SO

NS

10.5

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74ALS74ADR

SN74ALS74ANSR

SN74AS74ADR

SN74AS74ANSR

SOIC

SO

D

NS

D

14

2500

2000

2500

2000

346.0

33.0

SOIC

SO

NS

Pack Materials-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN54ALS74A_08
厂家：	TEXAS INSTRUMENTS
描述：	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 双上升沿触发的D型触发器具有清零和预设触发器
文件：	总17页 (文件大小：683K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN54ALS74A_08 [TI]

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