SN54ALVTH16827DL [TI]
ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, SSOP-56;
| 型号： | SN54ALVTH16827DL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, SSOP-56 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
SN54ALVTH16827 . . . WD PACKAGE
SN74ALVTH16827 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
1OE1
1Y1
1Y2
GND
1Y3
1Y4
1OE2
1A1
1A2
GND
1A3
1A4
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
)
CC
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
V
V
High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
CC
CC
1Y5
1Y6
1A5
1A6
)
CC
Power Off Disables Outputs, Permitting
Live Insertion
1Y7 10
47 1A7
GND
1Y8
GND
1A8
11
12
46
45
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
1Y9 13
1Y10 14
2Y1 15
2Y2 16
2Y3 17
GND 18
2Y4 19
2Y5 20
2Y6 21
44 1A9
43 1A10
42 2A1
41 2A2
40 2A3
39 GND
38 2A4
37 2A5
36 2A6
Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
+ 0.5 V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
V
22
35
V
CC
CC
2Y7 23
34 2A7
33 2A8
32 GND
31 2A9
30 2A10
29 2OE2
2Y8 24
GND 25
2Y9 26
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
2Y10 27
2OE1 28
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V V
the capability to provide a TTL interface to a 5-V system environment.
operation, but with
CC
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer
section, the two output-enable (1OE1 and 1OE2, or 2OE1 and 2OE2) inputs must be low for the corresponding
Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the
high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
description (continued)
When V
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16827 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16827 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit section)
INPUTS
OUTPUT
Y
OE1
L
OE2
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
logic diagram (positive logic)
1
28
1OE1
2OE1
56
29
1OE2
2OE2
55
2
42
15
1Y1
1A1
2Y1
2A1
To Nine Other Channels
To Nine Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Output current in the low state, I : SN54ALVTH16827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ALVTH16827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, I : SN54ALVTH16827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
O
SN74ALVTH16827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
recommended operating conditions, V
= 2.5 V ± 0.2 V (see Note 3)
CC
SN54ALVTH16827
MIN TYP MAX
SN74ALVTH16827
UNIT
MIN
2.3
TYP
MAX
V
V
V
V
Supply voltage
2.3
1.7
2.7
2.7
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
1.7
0.7
5.5
–6
6
0.7
5.5
–8
8
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
18
10
24
10
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
recommended operating conditions, V
= 3.3 V ± 0.3 V (see Note 3)
CC
SN54ALVTH16827
SN74ALVTH16827
UNIT
MIN
3
TYP
MAX
MIN
3
TYP
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
2
2
0.8
5.5
–24
24
0.8
5.5
–32
32
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
48
64
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
10
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
electrical characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted)
CC
SN54ALVTH16827
SN74ALVTH16827
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 2.3 V to 2.7 V,
I
I
I
I
I
I
I
I
= –100 µA
= –6 mA
= –8 mA
= 100 µA
= 6 mA
V
–0.2
CC
1.8
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
V
V
OH
V
= 2.3 V
CC
CC
1.8
V
= 2.3 V to 2.7 V,
0.2
0.4
0.2
0.47
0.4
V
OL
= 8 mA
V
CC
= 2.3 V
= 18 mA
= 24 mA
0.5
0.5
±1
V
V
= 2.7 V,
V = V
I
or GND
±1
10
10
1
CC
CC
Control inputs
Data inputs
= 0 or 2.7 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 2.7 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 2.3 V,
= 2.3 V,
= 2.7 V,
= 2.7 V,
= 2.3 V,
V = 0.7 V
I
115
–10
115
–10
BHL
§
V = 1.7 V
I
BHH
¶
V = 0 to V
300
–300
300
–300
BHLO
I
CC
CC
#
V = 0 to V
I
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
µA
µA
I
I
I
OZ(PU/PD)
OZH
V = GND or V , OE = don’t care
I
V
= 2.3 V,
O
V
CC
= 2.7 V
5
5
V = 0.7 V or 1.7 V
I
V
= 0.5 V,
O
V
= 2.7 V
= 2.7 V,
–5
–5
OZL
CC
CC
V = 0.7 V or 1.7 V
I
Outputs high
Outputs low
0.04
2.3
0.04
3
0.1
5
0.04
2.3
0.04
3
0.1
5
V
I
I
mA
= 0,
CC
O
V = V
or GND
I
CC
Outputs disabled
0.1
0.1
C
C
V
V
= 2.5 V,
= 2.5 V,
V = 2.5 V or 0
I
pF
pF
i
CC
V
O
= 2.5 V or 0
6
6
o
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 2.5 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
electrical characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted)
V
CC
SN54ALVTH16827
SN74ALVTH16827
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3 V to 3.6 V,
I
I
I
I
I
I
I
I
I
= –100 µA
= –24 mA
= –32 mA
= 100 µA
= 16 mA
= 24 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
2
V
CC
–0.2
2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
V
= 3 V
CC
CC
V
= 3 V to 3.6 V,
0.2
0.5
0.2
0.4
V
OL
V
CC
= 3 V
0.5
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
10
1
CC
CC
Control inputs
Data inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 3.6 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 3 V,
= 3 V,
= 3.6 V,
= 3.6 V,
= 3 V,
V = 0.8 V
I
75
75
BHL
§
V = 2 V
I
–75
500
–75
500
BHH
¶
V = 0 to V
BHLO
I
CC
CC
#
V = 0 to V
I
–500
–500
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
µA
µA
I
I
I
OZ(PU/PD)
OZH
V = GND or V , OE = don’t care
I
V
= 3 V,
O
V
CC
= 3.6 V
5
5
V = 0.8 V or 2 V
I
V
= 0.5 V,
O
V
= 3.6 V
= 3.6 V,
–5
–5
OZL
CC
CC
V = 0.8 V or 2 V
I
Outputs high
Outputs low
0.07
3.2
0.1
6
0.07
3.2
0.1
6
V
I
I
mA
= 0,
CC
O
V = V
or GND
CC
I
Outputs disabled
0.07
0.1
0.07
0.1
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
0.4
0.4
mA
∆I
CC
or GND
CC
C
C
V
V
= 3.3 V,
= 3.3 V,
V = 3.3 V or 0
3
6
3
6
pF
pF
i
CC
I
V
O
= 3.3 V or 0
o
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 3.3 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
An external driver must source at least I
¶
#
||
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
O
CC
High-impedance state during power up or power down
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
switchingcharacteristicsoverrecommendedoperatingfree-airtemperaturerange, C =30pF, V
L
CC
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
SN54ALVTH16827
SN74ALVTH16827
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
1.7
1.9
1.8
2.5
1.7
MAX
3.2
3.7
4.3
4
MIN
1.5
1.7
1.9
1.8
2.5
1.7
MAX
3.2
3.7
4.3
4
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
OE
OE
5.6
4.6
5.6
4.6
switching characteristicsoverrecommendedoperatingfree-airtemperaturerange, C =50pF, V
L
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
SN54ALVTH16827
SN74ALVTH16827
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.8
1.6
1.6
1.5
3.3
2.6
MAX
3
MIN
1.8
1.6
1.6
1.5
3.3
2.6
MAX
3
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
2.8
3.9
3.4
5.8
4.6
2.8
3.9
3.4
5.8
4.6
OE
OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16827, SN74ALVTH16827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES076E – JULY 1996 – REVISED DECEMBER 1998
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
S1
Open
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
6 V
PLH PHL
/t
C
= 50 pF
t
L
PLZ PZL
500 Ω
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
1.5 V
1.5 V
1.5 V
Input
V
V
+ 0.3 V
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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FEATURES | DESCRIPTION | DATASHEETS |
PRICING/AVAILABILITY | SAMPLES |
PRODUCT FOLDER PRODUCT INFO:
|
APPLICATION NOTES RELATED DOCUMENTS
|
PRODUCT SUPPORT: TRAINING
SN74ALVTH16827, 2.5-V/3.3-V 20-Bit Buffers/Drivers With 3-State Outputs
DEVICE STATUS: ACTIVE
PARAMETER NAME SN74ALVTH16827
Voltage Nodes (V) 3.3, 2.5
Vcc range (V)
Input Level
2.3 to 3.6
TTL/CMOS
LVTTL
Output Level
Output Drive (mA) -8/24
tpd(max) (ns)
Static Current
3.7
5
FEATURES
Back to Top
TM
l State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus
Design for 2.5-V and
3.3-V Operation and Low Static Power Dissipation
l Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-
V V
)
CC
l Typical V
(Output Ground Bounce) < 0.8 V at V = 3.3 V, T = 25°C
OLP
CC
A
l High Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V V
)
CC
l Power Off Disables Outputs, Permitting Live Insertion
High-Impedance State During Power Up and Power Down Prevents Driver Conflict
l
l Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent
the Bus From Floating
l Auto3-State Eliminates Bus Current Loading When Output Exceeds V
+ 0.5 V
CC
l Latch-Up Performance Exceeds 250 mA Per JESD 17
l ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using
Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
l Flow-Through Architecture Facilitates Printed Circuit Board Layout
l Distributed V
and GND Pin Configuration Minimizes High-Speed Switching Noise
CC
l Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline
2 of 3
(DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat
(WD) Package
Widebus is a trademark of Texas Instruments Incorporated.
DESCRIPTION
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The 'ALVTH16827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices are composed of two 10-bit sections with separate output-enable signals. For
either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\)
inputs must be low for the corresponding Y outputs to be active. If either output-enable input
is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When V
is between 0 and 1.2 V, the device is in the high-impedance state during power up
CC
or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied
to V through a pullup resistor; the minimum value of the resistor is determined by the
CC
current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
The SN54ALVTH16827 is characterized for operation over the full military temperature range
of -55°C to 125°C. The SN74ALVTH16827 is characterized for operation from -40°C to 85°C.
TECHNICAL DOCUMENTS
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To view the following documents, Acrobat Reader 3.x is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
DATASHEET
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Full datasheet in Acrobat PDF: sces076e.pdf (163 KB) (Updated: 12/18/1998)
Full datasheet in Zipped PostScript: sces076e.psz (162 KB)
APPLICATION NOTES
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View Application Reports for Digital Logic
l Advanced Low-Voltage Technology (SCEA015 - Updated: 07/27/1999)
Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (SDAA011A
l
-
)
Updated: 09/08/1999
Timing Differences Of 10-pF Versus 50pF Loading (SCEA004 -
)
l
Updated: 11/01/1996
RELATED DOCUMENTS
Back to Top
Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB -
l
l
Updated:
)
05/06/1999
Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB -
)
Updated: 04/17/2000
l MicroStar Junior BGA Design Summary (SCET004, 167 KB -
)
Updated: 07/28/2000
l More Power In Less Space - Technical Article (SCAU001A, 850 KB - Updated: 03/01/1996)
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SAMPLES
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SAMPLES
ORDERABLE DEVICE
PACKAGE
DL
PINS
56
TEMP (ºC)
-40 TO 85
-40 TO 85
-40 TO 85
STATUS
ACTIVE
ACTIVE
ACTIVE
SN74ALVTH16827DL
SN74ALVTH16827DLR
SN74ALVTH16827GR
Request Samples
Request Samples
Request Samples
DL
56
DGG
56
PRICING/AVAILABILITY
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BUDGETARY
PRICE
US$/UNIT
QTY=1000+
TEMP
(ºC)
PACK
QTY
ORDERABLE DEVICE PACKAGE PINS
STATUS
PRICING/AVAILABILITY
-40 TO
85
SN74ALVTH16827DL
SN74ALVTH16827DLR
SN74ALVTH16827GR
SN74ALVTH16827VR
DL
DL
56
56
56
56
ACTIVE
ACTIVE
ACTIVE
ACTIVE
3.09
3.09
3.09
3.42
20
Check stock or order
Check stock or order
Check stock or order
Check stock or order
-40 TO
85
1000
2000
2000
-40 TO
85
DGG
DGV
-40 TO
85
Table Data Updated on: 11/15/2000
© Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy
| Important Notice
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