SN54AS194_14 [TI]
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS;
| 型号： | SN54AS194_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS |
| 文件： | 总8页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
SN54AS194 . . . J PACKAGE
SN74AS194 . . . D OR N PACKAGE
(TOP VIEW)
• Parallel-to-Serial, Serial-to-Parallel
Conversions
• Left or Right Shifts
• Parallel Synchronous Loading
• Direct Overriding Clear
• Temporary Data-Latching Capability
• Package Options Include Plastic
Small-Outline Packages (D), Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
SR SER
V
CC
Q
Q
Q
Q
A
B
C
D
A
B
C
D
CLK
S1
S0
SL SER
GND
description
SN54AS194 . . . FK PACKAGE
(TOP VIEW)
These 4-bit bidirectional universal shift registers
feature parallel outputs, right-shift and left-shift
serial (SR SER, SL SER) inputs, operating-
mode-control (S0, S1) inputs, and a direct
overriding clear (CLR) line. The registers have
four distinct modes of operation:
3
2
1 20 19
18
Q
Q
A
B
4
5
6
7
8
B
C
•
•
•
•
Inhibit clock (temporary data latch/do nothing)
Shift right (in the direction Q toward Q )
17
16
15
14
NC
NC
C
A
D
Q
D
Shift left (in the direction Q toward Q )
D
A
CLK
D
9 10 11 12 13
Parallel (broadside) load
Parallel synchronous loading is accomplished by
applying the four bits of data and taking both S0
and S1 high. The data is loaded into the
associated flip-flops and appears at the outputs
after the positive transition of the clock (CLK)
input. During loading, serial data flow is inhibited.
NC – No internal connection
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when
both mode-control inputs are low.
The SN54AS194 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AS194 is characterized for operation from 0°C to 70°C.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
S1
SERIAL
PARALLEL
CLK
Q
Q
Q
Q
D
CLR
A
B
C
S0
X
X
H
H
H
L
LEFT RIGHT
A
X
X
a
B
X
X
b
C
X
X
c
D
X
X
d
L
X
X
H
L
X
L
↑
↑
↑
↑
↑
X
X
X
X
X
X
H
L
X
X
X
H
L
L
L
L
L
H
H
H
H
H
H
H
Q
Q
Q
C0
c
Q
D0
d
A0
B0
a
H
L
b
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Q
Q
Bn
Q
Bn
Q
Dn
Q
Dn
Q
C0
Q
Q
An
An
Cn
Cn
B0
Cn
Cn
L
Q
Q
Q
Q
H
H
L
X
X
X
Q
H
L
Bn
Bn
A0
L
Q
Q
L
X
Q
D0
H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions); ↑ = transition from
low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; Q , Q , Q , Q = the
A0 B0 C0 D0
levelofQ ,Q ,Q ,orQ ,respectively,beforetheindicatedsteady-stateinputconditionswereestablished;Q ,Q ,Q ,
An Bn Cn
A
B
C
D
B
Q
= the level of Q , Q , Q , respectively, before the most recent ↑ transition of the clock.
Dn
A
C
†
logic symbol
1
9
SRG4
0
CLR
S0
R
0
M
3
10
11
S1
1
CLK
C4
1
/2
2
3
4
5
6
7
15
SR SER
1, 4D
3, 4D
3, 4D
3, 4D
3, 4D
2, 4D
Q
A
A
14
13
B
Q
Q
B
C
C
D
12
Q
D
SL SER
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
logic diagram (positive logic)
Parallel Inputs
A
D
6
3
10
S1
9
S0
2
7
SR SER
SL SER
Two
Identical
Channels
Not
†
Shown
1S
C1
1S
C1
1R
R
1R
R
11
CLK
1
CLR
15
12
Q
Q
D
A
Parallel Outputs
†
I/O ports not shown: Q (14) and Q (13)
B
C
Pin numbers shown are for the D, J, and N packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
CLK
S0
Mode-
Control
Inputs
S1
CLR
R
Serial
Data
L
Inputs
A
B
H
L
Parallel
Data
Inputs
C
D
H
L
Q
Q
Q
A
B
C
Outputs
Q
D
Shift Right
Shift Left
Inhibit
Clear Load
Clear
Figure 1. Typical Clear, Load, Right-Shift, and Clear Sequences
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54AS194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
recommended operating conditions
SN54AS194
MIN NOM
SN74AS194
MIN NOM
UNIT
MAX
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.8
–2
20
75
0.8
–2
20
80
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
*
0
4
0
4.5
4
CLR
t *
w
Pulse duration
CLK high
CLK low
Select
4
ns
ns
6
7
9
9.5
4
t
su
*
Data
3.5
6
Setup time before CLK↑
Clear inactive state
6
t *
Hold time, data after CLK↑
0.5
–55
0.5
0
ns
h
T
A
Operating free-air temperature
125
70
°C
* On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data, but are not production tested.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS194
SN74AS194
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
V
V
IK
CC
CC
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
= –2 mA
= 20 mA
V
CC
–2
V
CC
–2
OH
OL
OH
OL
I
0.35
0.5
0.1
0.2
20
0.35
0.5
0.1
0.2
20
Data, CLK, CLR
Mode, SL, SR
Data, CLK, CLR
Mode, SL, SR
Data, CLK, CLR
Mode, SL, SR
I
I
V
= 5.5 V,
= 5.5 V,
V = 7 V
I
mA
CC
CC
I
V
V = 2.7 V
I
µA
IH
IL
40
40
–0.5
–1
–0.5
–1
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V
V = 0.4 V
I
mA
mA
mA
‡
V
O
= 2.25 V
–30
–112
49
–30
–112
43
O
Outputs high
Outputs low
30
38
30
38
CC
60
53
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
switching characteristics (see Figure 2)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
T
A
= MIN to MAX
SN54AS194
SN74AS194
MIN
75
MAX
MIN
80
3
MAX
f
t
t
t
*
MHz
ns
max
2.5
2.5
3.5
8
8
7
7
PLH
PHL
PHL
CLK
CLR
Any Q
Any Q
3
13
4
12
ns
* On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data, but are not production tested.
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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