SN54BCT373_16 [TI]
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS;型号: | SN54BCT373_16 |
厂家: | TEXAS INSTRUMENTS |
描述: | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS 输出元件 |
文件: | 总11页 (文件大小:292K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003
Operating Voltage Range of 4.5 V to 5.5 V
State-of-the-Art BiCMOS Design
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Significantly Reduces I
ESD Protection Exceeds JESD 22
CCZ
– 2000-V Human-Body Model (A114-A)
Full Parallel Access for Loading
SN54BCT373 . . . J OR W PACKAGE
SN74BCT373 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
SN54BCT373 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
3
2
1
20 19
18
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’BCT373 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched
at the logic levels that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
SN74BCT373N
SN74BCT373N
Tube
SN74BCT373DW
SN74BCT373DWR
SN74BCT373NSR
SN74BCT373DBR
SNJ54BCT373J
SNJ54BCT373W
SNJ54BCT373FK
SOIC – DW
BCT373
0°C to 70°C
Tape and reel
Tape and reel
Tape and reel
Tube
SOP – NS
SSOP – DB
CDIP – J
BCT373
BT373
SNJ54BCT373J
SNJ54BCT373W
SNJ54BCT373FK
–55°C to 125°C
CFP – W
Tube
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
LE
11
C1
1D
2
1Q
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
CC
Input clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
IK
Current into any output in the low state: SN54BCT373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54BCT373
MIN NOM MAX
SN74BCT373
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
–12
48
0.8
–18
–15
64
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
–55
125
0
70
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54BCT373
SN74BCT373
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
= 4.5 V
I = –18 mA
–1.2
–1.2
V
IK
CC
I
I
I
I
I
I
= –3 mA
= –12 mA
= –15 mA
= 48 mA
= 64 mA
2.4
2
3.3
3.2
2.4
2
3.3
3.1
OH
OH
OH
OL
OL
V
OH
V
CC
0.38
0.55
V
OL
V
CC
= 4.5 V
V
0.42
0.55
0.4
20
I
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
= 5.5 V
= 5.5 V
= 5 V,
V = 5.5 V
I
0.4
20
mA
µA
I
V = 2.7 V
I
IH
IL
V = 0.5 V
I
–0.6
–225
50
–0.6
–225
50
mA
mA
µA
‡
V
O
V
O
V
O
= 0
–100
–100
OS
= 2.7 V
= 0.5 V
OZH
OZL
CCL
CCH
CCZ
–50
60
–50
60
µA
37
2
37
2
mA
mA
mA
pF
5
5
5
8
5
8
C
C
V = 2.5 V or 0.5 V
I
6
6
i
= 5 V,
V
O
= 2.5 V or 0.5 V
11
11
pF
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
SN54BCT373 SN74BCT373
UNIT
MIN
7.5
2
MAX
MIN
7.5
2
MAX
MIN
7.5
2
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
5.5
5.5
5.5
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003
switching characteristics (see Figure 1)
V
C
= 5 V,
= 50 pF,
V
= 4.5 V to 5.5 V,
C = 50 pF,
L
CC
L
CC
R1 = 500 Ω,
R2 = 500 Ω,
T
A
R1 = 500 Ω,
R2 = 500 Ω,
†
T = MIN to MAX
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
= 25°C
’BCT373
TYP
5.9
SN54BCT373 SN74BCT373
MIN
2
MAX
7.7
MIN
1.5
1
MAX
10.1
10.3
10.1
9.2
MIN
2
MAX
9.3
9.5
9.3
8.8
11.8
12
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
ns
2
6.7
8.5
1.5
2
2
6.2
8.2
2
LE
2
5.9
7.8
2
2
1
7.8
9.6
1
12.3
12.5
7.4
1
OE
OE
1
8.2
10.2
6.6
1
1
1
4.9
1
1
7
1
5
6.7
1
8.1
1
7.4
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
7 V (t
, t
, O.C.)
PZL PLZ
Open
(all others)
S1
From Output
Under Test
Test
Point
C
L
R1
R1
(see Note A)
From Output
Under Test
Test
Point
C
L
R2
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
R
= R1 = R2
L
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3 V
0 V
1.5 V
1.5 V
3 V
Timing Input
(see Note B)
1.5 V
t
w
0 V
3 V
0 V
3 V
0 V
t
h
Low-Level
Pulse
t
1.5 V
su
1.5 V
Data Input
(see Note B)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level enable)
3 V
1.5 V
1.5 V
Input
(see Note B)
1.5 V
1.5 V
0 V
PHL
t
t
PZL
t
t
PLZ
t
PLH
3.5 V
In-Phase
Output
(see Note D)
V
OH
1.5 V
Waveform 1
(see Notes C and D)
1.5 V
1.5 V
1.5 V
t
V
OL
V
OL
0.3 V
t
PHZ
PLH
t
PHL
PZH
V
OH
V
OH
Out-of-Phase
Output
(see Note D)
Waveform 2
(see Notes C and D)
1.5 V
1.5 V
0.3 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9074601M2A
5962-9074601MRA
5962-9074601MSA
SN74BCT373DBLE
SN74BCT373DBR
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
1
1
1
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
ACTIVE
W
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
2000
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74BCT373DW
SN74BCT373DWR
SN74BCT373N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
SO
DW
DW
N
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74BCT373NSR
NS
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SNJ54BCT373FK
SNJ54BCT373J
SNJ54BCT373W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明