SN54F175FK-00 [TI]
F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20;
| 型号： | SN54F175FK-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54F175,74F175
54F175 74F175 Quad D Flip-Flop
Literature Number: SNOS163A
November 1994
54F/74F175 Quad D Flip-Flop
General Description
Features
Y
Edge-triggered D-type inputs
The ’F175 is a high-speed quad D flip-flop. The device is
useful for general flip-flop requirements where clock and
clear inputs are common. The information on the D inputs is
stored during the LOW-to-HIGH clock transition. Both true
and complemented outputs of each flip-flop are provided. A
Master Reset input resets all flip-flops, independent of the
Clock or D inputs, LOW.
Y
Buffered positive edge-triggered clock
Y
Asynchronous common reset
Y
True and complement output
Y
Guaranteed 4000V minimum ESD protection
Package
Commercial
74F175PC
Military
Package Description
Number
N16E
J16A
16-Lead (0.300 Wide) Moldual-In-L
×
54F175DM (Note 2)
16-Lead Ceramic Dual-In-Line
74F175SC (Note 1)
74F175SJ (Note 1)
M16A
M16D
W16A
E20A
16-Lead (0.150 Wideed Small tlinJEDEC
×
16-Lead (0.300 WSmall Outline, EIAJ
×
54F175FM (Note 2)
54F175LM (Note 2)
16-LeCerpack
20-Lead Cmic Leess Chip arrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
SCX and SJX.
×
Note 2: Military grade device with environmental and burn-in processing. Use su
, FMQB LMQB.
Logic Symbols
on Diagrams
Pin Assignm
DIP, SC and
Pin Assignment
for LCC
IEEE/IEC
TL/F/9490–1
TL/F/9490–2
–5
TL/F/9490–3
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9490
RRD-B30M75/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names
Description
U.L.
Input I /I
IH IL
Output I /I
HIGH/LOW
OH OL
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
b
20 mA/ 0.6 mA
D –D
0
Data Inputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
3
CP
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
True Outputs
MR
b
b
Q –Q
0
1 mA/20 mA
1 mA/20 mA
3
Q –Q
0
Complement Outputs
3
Functional Description
Truth Table
The ’F175 consists of four edge-triggered D flip-flops with
individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW-to-HIGH clock
(CP) transition, causing individual Q and Q outputs to follow.
A LOW input on the Master Reset (MR) will force all Q out-
puts LOW and Q outputs HIGH independent of Clock or
Data inputs. The ’F175 is useful for general logic applica-
tions where a common Master Reset and Clock are accept-
able.
Inputs
CP
Outputs
MR
D
Q
Q
n
n
n
L
H
H
X
X
L
H
L
L
H
L
H
L
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
e
L
LOW-to-HIGH Clock Transition
Logic Diagram
TL/F/9490–4
Please note that this diagraded only fof logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
§
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
§
a
§
a
55 C to 125 C
Ambient Temperature under Bias
§
Supply Voltage
Military
Commercial
b
b
a
a a
4.5V to 5.5V
a a
4.5V to 5.5V
Junction Temperature under Bias
Plastic
55 C to 175 C
§
§
a
55 C to 150 C
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
TRI-STATE Output
É
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
54F/74F
Symbol
Parameter
U
C
Conditions
Min
Typ
Max
V
V
V
V
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
e b
18 mA
Input Clamp Diode Voltage
.2
Min
Min
I
CD
OH
IN
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.5
2.5
2.7
I
I
I
1 mA
1 mA
1 mA
CC
OH
OH
OH
74F 10% V
74F 5% V
V
CC
CC
e
e
V
Output LOW
Voltage
54F 10% V
74F 10% V
I
I
20 mA
20 mA
OL
CC
OL
V
Min
Max
Max
Max
0.0
0.5
CC
OL
e
I
I
I
Input HIGH
Current
54F
74F
20.0
5.0
V
V
V
2.7V
IH
IN
mA
mA
mA
V
e
Input HIGH Curre
Breakdown Test
54
7
100
7.0
7.0V
BVI
IN
e
V
CC
Output HIG
5
74F
250
50
CEX
OUT
Leak
e
All Other Pins Grounded
V
ID
In
T
I
ID
1.9 mA
4F
F
4.75
e
IOD
I
O
Cir
V
150 mV
OD
3.75
mA
0.0
All Other Pins Grounded
b
e
0.5V
I
I
I
Input L
0.6
mA
mA
Max
Max
V
IL
IN
b
b
e
0V
OUT
Output Short-Circuit Current
Power Supply Current
60
150
V
OS
CC
e
e
CP
L
MR
22.5
34.0
mA
Max
e
HIGH
D
n
3
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
50 pF
T
, V
CC
e
Mil
T
, V
A CC
Com
A
e a
Symbol
Parameter
V
Units
CC
e
C
C
L
L
e
C
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
f
Maximum Clock Frequency
Propagation Delay
100
140
80
100
MHz
ns
max
t
t
4.0
4.0
5.0
6.5
6.5
8.5
3.5
4.0
8.5
4.0
4.0
7.5
9.5
PLH
CP to Q or Q
n
10.5
PHL
n
t
Propagation Delay
MR to Q
PHL
4.5
4.0
9.0
6.5
11.5
8.0
4.5
4.0
15.0
10.0
4.5
4.0
13.0
9.0
ns
ns
n
t
Propagation Delay
MR to Q
PLH
n
AC Operating Requirements
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
e
Symbol
Parameter
T
, V
CC
Mil
Max
T
A C
Co
Max
Un
A
e a
V
CC
Min
Max
Min
Min
t (H)
s
Setup Time, HIGH or LOW
3.0
3.0
3.0
3.0
t (L)
s
D to CP
n
ns
ns
t (H)
h
Hold Time, HIGH or LOW
D to CP
n
1.0
1.0
1.0
2.0
1.0
1.0
t (L)
h
t
t
(H)
(L)
CP Pulse Width
HIGH or LOW
4.0
5.0
4.0
5.
4.0
5.0
w
w
t
t
(L)
MR Pulse Width, LOW
5.0
5.0
5.0
5.0
ns
ns
w
Recovery Time, MR to CP
rec
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 175
S
C
X
Temperature Range Family
e
e
54F Military
Special Variations
e
74F Commercial
QB
Military grade device with
environmental and burn-in
processing
Device Type
e
X
Devices shipped in 13 reel
×
Package Code
Temperature Range
e
e
e
e
e
e
P
D
F
L
S
SJ
Plastic DIP
Ceramic DIP
Flatpak
Leadless Chip Carrier (LCC)
Small Outline SOIC JEDEC
Small Outline SOIC EIAJ
e
e
a
C
M
Commercial (0 C to 70 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
Physical Dimensions inches (millimeters)
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
16-Lead (0.150 Wide) Molded Small Outline Package, JEDEC (S)
×
NS Package Number M16A
6
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300 Wide) Molded Small tline PacAJ (SJ
×
NS Package Number 6D
6-Lead (0.300 Wide) Molded Dual-In-Line Package (P)
×
NS Package Number N16E
7
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic FlatpaF)
NS Package Number W16
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