SN54F86FK [TI]
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES; 四路2输入异或门
| 型号： | SN54F86FK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES |
| 文件： | 总5页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
SN54F86 . . . J PACKAGE
SN74F86 . . . D OR N PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
description
These devices contain four independent 2-input
exclusive-OR gates. They perform the Boolean
function Y = A B or Y = AB + AB in positive logic.
2Y
GND
8
A common application is as a true/complement
element. If one of the inputs is low, the other input
is reproduced in true form at the output. If one of
the inputs is high, the signal on the other input is
reproduced inverted at the output.
SN54F86 . . . FK PACKAGE
(TOP VIEW)
The SN54F86 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F86 is characterized for
operation from 0°C to 70°C.
3
2
1
20 19
18
1Y
NC
2A
4
5
6
7
8
4A
NC
4Y
NC
3B
17
16
15
14
FUNCTION TABLE
(each gate)
NC
2B
9 10 11 12 13
INPUTS
OUTPUT
Y
A
B
L
L
L
L
H
H
L
H
L
NC – No internal connection
H
H
H
†
logic symbol
1
= 1
1A
2
3
1Y
1B
4
2A
5
6
2Y
2B
9
3A
8
10
3Y
3B
4A
4B
12
13
11
4Y
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an ’F86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of outputs
(i.e., only 1 of the 2) are
active.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
CC
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions
SN54F86
SN74F86
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
–1
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
20
20
T
A
–55
125
0
70
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F86
SN74F86
PARAMETER
TEST CONDITIONS
UNIT
V
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
I
–1.2
–1.2
IK
I
I
I
= –1 mA
= –1 mA
= 20 mA
2.5
3.4
0.3
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
0.5
0.1
V
I
I
I
I
I
I
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
20
IH
IL
V = 0.5 V
I
– 0.6
–150
23
– 0.6
–150
23
mA
mA
mA
mA
‡
V
O
= 0
–60
–60
OS
See Note 3
V = 4.5 V
15
18
15
18
CCH
CCL
28
28
I
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
is measured with outputs open, and the A or B input (not both) at 4.5 V. Remaining inputs are grounded.
NOTE 3:
I
CCH
switching characteristics (see Figure 1)
V
C
R
= 5 V,
= 50 pF,
= 500 Ω,
= 25°C
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
= 500Ω,
FROM
(INPUT)
TO
(OUTPUT)
§
PARAMETER
UNIT
T
A
T
A
= MIN to MAX
′F86
TYP
4
SN54F86
SN74F86
MIN
3
MAX
5.5
5.5
7
MIN
3
MAX
MIN
3
MAX
t
t
t
t
7
8
6.5
6.5
8
PLH
PHL
PLH
PHL
A or B
(other input low)
Y
Y
ns
ns
3
4.2
5.3
4.7
2.6
3.5
3
3
3.5
3
10
8
3.5
3
A or B
(other input high)
6.5
7.5
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F86, SN74F86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDFS019B – JANUARY 1989 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
7 V (t
, t
, O.C.)
PZL PLZ
Open
(all others)
From Output
Under Test
Test
Point
S1
C
L
R1
(see Note A)
R1
From Output
Under Test
Test
Point
C
L
R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
(see Note A)
R
= R1 = R2
L
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note C)
3 V
0 V
1.5 V
1.5 V
t
w
3 V
3 V
0 V
Timing Input
(see Note C)
1.5 V
Low-Level
Pulse
1.5 V
1.5 V
0 V
3 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
PULSE DURATION
Data Input
(see Note C)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
Output
Control
1.5 V
1.5 V
(low-level enable)
0 V
3 V
Input
(see Note C)
t
PZL
1.5 V
1.5 V
t
PLZ
0 V
PHL
3.5 V
t
t
Waveform 1
(see Notes B and E)
PLH
1.5 V
In-Phase
Output
(see Note E)
V
OH
V
OL
1.5 V
1.5 V
1.5 V
t
V
0.3 V
t
OL
PHZ
t
PZH
PLH
t
V
PHL
OH
0.3 V
0 V
V
OH
Waveform 2
(see Notes B and E)
Out-of-Phase
Output
1.5 V
1.5 V
(see Note E)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is open.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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