SN54GTL16622AHV [TI]
18-BIT LVTTL-TO-GTL/GTL BUS TRANSCEIVERS; 18位LVTTL - TO- GTL / GTL总线收发器
| 型号： | SN54GTL16622AHV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT LVTTL-TO-GTL/GTL BUS TRANSCEIVERS |
| 文件： | 总10页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
SN74GTL16622A . . . DGG PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
D-Type Flip-Flops With Qualified Storage
Enable
OEAB
1A1
GND
1A2
1A3
GND
CLKAB
1CEAB
1CEBA
1B1
GND
1B2
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
3
4
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
5
6
I
Supports Partial-Power-Down Mode
V
1B3
7
CC
off
Operation
1A4
GND
1A5
1A6
GND
1A7
1A8
GND
1A9
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
V
8
CC
1B4
1B5
1B6
GND
1B7
1B8
GND
1B9
2B1
GND
2B2
2B3
GND
2B4
2B5
2B6
9
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Distributed V
Minimizes High-Speed Noise
and GND-Pin Configuration
CC
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Ceramic
Quad Flat (HV) Packages
V
description
REF
V
2B7
2B8
GND
2B9
2CEBA
2CEAB
CLKBA
CC
The
’GTL16622A
devices
are
18-bit
GND
2A7
2A8
GND
2A9
registered bus transceivers that provide
LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
signal-level translation. They are partitioned as
two separate 9-bit transceivers with individual
clock-enable controls and contain D-type
flip-flops for temporary storage of data flowing in
either direction. The devices provide an interface
between cards operating at LVTTL logic levels
and a backplane operating at GTL/GTL+ signal
levels. Higher speed operation is a direct result of
the reduced output swing (<1 V), reduced input
threshold levels, and output edge control
(OEC ).
OEBA
The user has the flexibility of using this device at either GTL (V = 1.2 V and V
= 0.8 V) or the preferred
TT
REF
higher noise margin GTL+ (V = 1.5 V and V
= 1 V) signal levels. GTL+ is the Texas Instruments derivative
TT
REF
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
is the reference input voltage for the B port.
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
description (continued)
Data flow in each direction is controlled by the output-enable (OEABandOEBA) and clock(CLKABandCLKBA)
inputs. Theclock-enable(CEABandCEBA)inputsaredesignedtocontroleach9-bittransceiverindependently,
which makes the device more versatile.
For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for
B to A is similar to that of A to B, but uses OEBA, CLKBA, and CEBA.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54GTL16622A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16622A is characterized for operation from –40°C to 85°C.
SN54GTL16622A . . . HV PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
GND
1A5
1A6
GND
1A7
1A8
GND
1A9
NC
1B4
1B5
1B6
GND
1B7
1B8
GND
1B9
NC
10
11
12
13
14
15
16
17
18
59
58
57
56
55
54
53
52
2A1 19
51 2B1
GND
2A2
GND
2B2
20
21
50
49
2A3 22
GND 23
2A4 24
2A5 25
GND 26
48 2B3
47 GND
46 2B4
45 2B5
44 2B6
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
†
FUNCTION TABLE
INPUTS
OUTPUT
B
MODE
Isolation
CEAB
OEAB
CLKAB
A
X
X
X
L
X
H
X
L
H
L
L
L
L
X
Z
‡
B
0
‡
B
0
X
Latched storage of A data
H or L
↑
↑
L
Clocked storage of A data
L
H
H
†
‡
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, CLKBA,
and CEBA.
Output level before the indicated steady-state input conditions are established
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
logic diagram (positive logic)
40
V
REF
1
OEAB
63
64
33
62
1CEAB
CLKAB
CLKBA
1CEBA
OEBA
32
2
CE
1D
61
1B1
1A1
CLK
CE
1D
CLK
To Eight Other Channels
34
2CEAB
35
17
2CEBA
2A1
CE
1D
48
2B1
CLK
CE
1D
CLK
To Eight Other Channels
Pin numbers shown are for the DGG package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
B port and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
REF
Voltage range applied to any output in the high or power-off state, V
O
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Current into any A-port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
IK
I
Output clamp current, I
OK
O
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Notes 4 through 6)
SN54GTL16622A
SN74GTL16622A
UNIT
V
MIN
3.15
1.14
1.35
0.74
0.87
NOM
3.3
1.2
1.5
0.8
1
MAX
3.45
1.26
1.65
0.87
1.1
MIN
3.15
1.14
1.35
0.74
0.87
NOM
3.3
1.2
1.5
0.8
1
MAX
3.45
1.26
1.65
0.87
1.1
V
V
Supply voltage
CC
GTL
Termination
voltage
V
TT
GTL+
GTL
V
V
V
V
Supply voltage
Input voltage
V
V
V
V
REF
GTL+
B port
V
TT
5.5
V
TT
I
Except B port
B port
5.5
V
+50 mV
V
+50 mV
High-level
input voltage
REF
REF
IH
IL
Except B port
B port
2
2
V
REF
–50 mV
V
REF
–50 mV
0.8
Low-level
input voltage
Except B port
0.8
I
I
Input clamp current
–18
–18
mA
mA
IK
High-level
output current
A port
–24
–24
OH
OL
A port
B port
24
50
24
50
85
Low-level
output current
I
mA
T
Operating free-air temperature
–55
125
–40
°C
A
NOTES: 4. All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Normal connection sequence is GND first and V = 3.3 V, I/O, control inputs, V and V (any order) last.
REF
CC
TT
6.
V
and R can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute I
ratings.
OL
TT
TT
Similarly, V
can be adjusted to optimize noise margins, but normally is 2/3 V
.
REF
TT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range for GTL/GTL+
(unless otherwise noted)
SN54GTL16622A
SN74GTL16622A
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
= 3.15 V, I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3.15 V to 3.45 V, I
= –100 µA
V
CC
–0.2
V
CC
–0.2
CC
OH
A port
A port
I
I
= –12 mA
= –24 mA
= 100 µA
2.4
2
2.4
2
V
V
OH
OH
OH
V
CC
V
CC
V
CC
V
CC
= 3.15 V
= 3.15 V to 3.45 V, I
0.2
0.4
0.5
0.2
0.2
0.4
0.55
±5
0.2
0.4
0.5
0.2
0.2
0.4
0.55
±5
OL
I
I
= 12 mA
= 24 mA
OL
= 3.15 V
OL
V
OL
= 3.15 V to 3.45 V, I
= 100 µA
OL
I
I
I
= 10 mA
= 40 mA
= 50 mA
OL
OL
OL
B port
B port
V
CC
= 3.15 V
V
CC
V
CC
V
CC
V
CC
= 3.45 V
= 3.45 V
= 0,
V = V or GND
I TT
I
I
I
V = V
I
or GND
±5
±5
µA
µA
µA
I
CC
A-port and
control inputs
V = 5.5 V or GND
I
±20
100
±20
100
V or V = 0 to 5.5 V
off
I
O
V = 0.8 V
75
75
I
= 3.15 V
A port
V = 2 V
I
–75
–75
I(hold)
‡
V
CC
V
CC
V
CC
= 3.45 V ,
= 3.45 V,
= 3.45 V,
V = 0.8 V to 2 V
±500
±10
10
±500
±10
10
I
§
I
I
A port
B port
V
O
V
O
= V
CC
= 1.5 V
or GND
µA
µA
OZ
OZH
Outputs high
Outputs low
60
60
V
I
= 3.45 V,
= 0,
CC
O
I
A or B port
60
60
mA
CC
V = V
I
or GND
CC
Outputs disabled
60
60
V
= 3.45 V,
CC
A-port or control inputs at V
¶
or GND,
500
500
µA
∆I
CC
CC
One input at V
– 0.6 V
CC
C
C
Control inputs V = 3.15 V or 0
I
2.5
6
3
8.5
9.5
2.5
6
3
8
pF
pF
i
A port
V
O
= 3.15 V or 0
io
B port
7
6.5
8.5
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
For I/O ports, the parameter I
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
includes the input leakage current.
OZ
or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature for GTL (unless otherwise noted)
SN54GTL16622A SN74GTL16622A
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
200
200
MHz
ns
clock
Pulse duration, CLK high or low
2.5
2.5
3.5
0.3
0.3
2.5
2.1
3.3
0.3
0
w
Data before CLK↑
CE before CLK↑
Data after CLK↑
CE after CLK↑
t
Setup time
Hold time
ns
ns
su
h
t
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature for GTL (see Figure 1)
SN54GTL16622A
SN74GTL16622A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
†
†
MIN TYP
MAX
MIN TYP
MAX
f
t
t
t
t
200
2.4
2.1
1.6
2.1
200
2.5
2.2
1.7
2.2
max
PLH
PHL
dis
5.7
5.7
5
5.5
5.5
4.8
5.2
CLKAB
OEAB
B
B
ns
5.5
en
Slew rate
Both transitions (B port)
0.5
0.5
V/ns
ns
t
t
t
t
t
t
Transition time, B outputs (0.6 V to 1 V)
Transition time, B outputs (1 V to 0.6 V)
0.5
0.3
1.9
1.8
1.6
2
2.3
1.7
5.5
5.3
5.3
5.8
0.6
0.4
2.1
2.1
1.7
2.3
2.2
1.5
5.3
5
r
ns
f
PLH
PHL
en
dis
CLKBA
OEBA
A
A
ns
ns
5
5.5
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature for GTL+ (unless otherwise noted)
SN54GTL16622A SN74GTL16622A
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
200
200
MHz
ns
clock
Pulse duration, CLK high or low
2.5
2.5
3.4
0.3
0.1
2.5
2.4
3.2
0.2
0
w
Data before CLK↑
CE before CLK↑
Data after CLK↑
CE after CLK↑
t
Setup time
Hold time
ns
ns
su
h
t
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature for GTL+ (see Figure 1)
SN54GTL16622A
†
SN74GTL16622A
†
MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN TYP
MAX
MIN TYP
200
f
t
t
t
t
200
2.5
2.2
2.3
1.7
max
PLH
PHL
PLH
PHL
5.8
6.1
5.5
5.3
2.6
4
4
5.6
5.7
5.2
5
CLKAB
OEAB
B
B
2.3
2.4
1.8
3.8
3.4
0.5
1.6
1.1
3.8
3.6
3.6
4
ns
Slew rate
Both transitions (B port)
0.5
V/ns
ns
t
t
t
t
t
t
Transition time, B outputs (0.6 V to 1.3 V)
Transition time, B outputs (1.3 V to 0.6 V)
0.9
0.4
1.9
1.8
1.8
2
2.8
3.7
5.5
5.3
5.3
5.8
1
0.5
2
2.7
3.2
5.3
5
r
ns
f
PLH
PHL
en
dis
CLKBA
OEBA
A
A
ns
ns
1.9
1.9
2.1
5
5.5
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
6 V
Open
GND
TT
S1
500 Ω
From Output
Under Test
TEST
S1
Open
6 V
25 Ω
t
t
t
/t
PLH PHL
/t
From Output
Under Test
Test
Point
PLZ PZL
/t
C
= 50 pF
L
500 Ω
GND
PHZ PZH
C
= 30 pF
(see Note A)
L
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
Timing
Input
3 V
0 V
1.5 V
0 V
1.5 V
1.5 V
Input
t
t
h
su
3 V
0 V
Data Input
A Port
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
V
3 V
0 V
TT
Data Input
B Port
Input
(see Note B)
V
REF
V
REF
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PHL
PLH
V
V
OH
Output
V
V
REF
REF
3 V
0 V
Output
Control
(see Note B)
OL
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKAB to B port)
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
1.5 V
V
+ 0.3 V
OL
V
(see Note C)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
OL
V
OH
– 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
V
(see Note C)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKBA to A port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(OEBA to A port)
NOTES: A.
C
includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
9
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相关型号：
SN54GTL16923HVR
GTL/TVC SERIES, DUAL 9-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQFP68, CERAMIC, QFP-68
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