SN54HC112_14 [TI]
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET;
| 型号： | SN54HC112_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
| 文件： | 总14页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄ ꢅꢆꢆꢇ
ꢊꢋꢌ ꢍ ꢎ ꢏꢐ ꢁꢑ ꢒꢌꢓ ꢔꢕ ꢑꢏꢑꢊꢒ ꢑꢏ ꢓꢖꢔ ꢒ ꢒ ꢑꢖꢑ ꢊ ꢗ ꢍꢔ ꢘ ꢏꢗ ꢍꢙ ꢘꢀ
ꢚ ꢔꢓ ꢄ ꢅꢍ ꢑꢌꢖ ꢌꢁꢊ ꢘ ꢖꢑ ꢀ ꢑꢓ
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
SN54HC112 . . . J OR W PACKAGE
SN74HC112 . . . D OR N PACKAGE
(TOP VIEW)
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 40-µA Max I
CC
1CLK
1K
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
Typical t = 13 ns
pd
4-mA Output Drive at 5 V
1CLR
2CLR
2CLK
1J
Low Input Current of 1 µA Max
1PRE
1Q
12 2K
description/ordering information
11
10
9
1Q
2J
2Q
2PRE
2Q
The ’HC112 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup time requirements are transferred to the
outputs on the negative-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
CLK pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops perform as toggle flip-flops by tying J and
K high.
GND
SN54HC112 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
2CLR
2CLK
NC
1J
1PRE
NC
4
5
6
7
8
17
16
15 2K
14
9 10 11 12 13
1Q
2J
1Q
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC112N
SN74HC112N
SN74HC112D
−40°C to 85°C
SN74HC112DR
SN74HC112DT
SNJ54HC112J
SNJ54HC112W
SNJ54HC112FK
HC112
CDIP − J
CFP − W
LCCC − FK
SNJ54HC112J
−55°C to 125°C
SNJ54HC112W
SNJ54HC112FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢆ ꢇ
ꢊ ꢋꢌꢍ ꢎ ꢏꢐ ꢁ ꢑꢒꢌꢓꢔ ꢕ ꢑ ꢏꢑꢊ ꢒꢑ ꢏꢓ ꢖꢔ ꢒꢒ ꢑ ꢖ ꢑꢊ ꢗ ꢍꢔ ꢘꢏꢗ ꢍ ꢙ ꢘꢀ
ꢚꢔ ꢓ ꢄ ꢅ ꢍ ꢑꢌ ꢖ ꢌꢁ ꢊ ꢘ ꢖꢑ ꢀꢑ ꢓ
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
†
L
L
X
H
H
H
H
↓
Q
Q
0
0
H
H
↓
H
L
L
H
L
H
H
↓
H
H
X
L
H
H
H
↓
H
X
Toggle
H
H
H
Q
Q
0
0
†
This configuration is nonstable; that is, it does not persist
when either PRE or CLR returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE
C
J
C
Q
TG
TG
C
K
C
C
TG
C
C
CLK
CLR
C
C
TG
C
Q
2
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢆ ꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢆꢇ
ꢊꢋꢌ ꢍ ꢎ ꢏꢐ ꢁꢑꢒ ꢌꢓ ꢔꢕ ꢑꢏꢑꢊꢒ ꢑ ꢏꢓꢖꢔ ꢒ ꢒ ꢑꢖꢑ ꢊ ꢗ ꢍꢔ ꢘ ꢏꢗ ꢍꢙ ꢘꢀ
ꢚ ꢔꢓ ꢄ ꢅꢍ ꢑꢌꢖ ꢌꢁꢊ ꢘ ꢖꢑ ꢀ ꢑꢓ
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC112
MIN NOM
SN74HC112
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
‡
= 4.5 V
= 6 V
t
Input transition (rise and fall) time
Operating free-air temperature
ns
t
T
A
−55
−40
°C
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
IL
IH
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢆ ꢇ
ꢊ ꢋꢌꢍ ꢎ ꢏꢐ ꢁ ꢑꢒꢌꢓꢔ ꢕ ꢑ ꢏꢑꢊ ꢒꢑ ꢏꢓ ꢖꢔ ꢒꢒ ꢑ ꢖ ꢑꢊ ꢗ ꢍꢔ ꢘꢏꢗ ꢍ ꢙ ꢘꢀ
ꢚꢔ ꢓ ꢄ ꢅ ꢍ ꢑꢌ ꢖ ꢌꢁ ꢊ ꢘ ꢖꢑ ꢀꢑ ꢓ
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC112
SN74HC112
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
4
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
40
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
80
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
10
i
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC112
SN74HC112
A
V
UNIT
CC
MIN
MAX
5
MIN
MAX
3.4
17
MIN
MAX
4
2 V
4.5 V
6 V
25
20
f
Clock frequency
Pulse duration
MHz
clock
29
20
24
2 V
100
20
17
100
20
17
100
20
17
100
20
17
0
150
30
25
150
30
25
150
30
25
150
30
25
0
125
25
21
125
25
21
125
25
21
125
25
21
0
4.5 V
6 V
PRE or CLR low
CLK high or low
Data (J, K)
t
w
ns
2 V
4.5 V
6 V
2 V
4.5 V
6 V
t
t
Setup time before CLK↓
ns
ns
su
2 V
4.5 V
6 V
PRE or CLR inactive
2 V
Hold time, data after CLK↓
4.5 V
6 V
0
0
0
h
0
0
0
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢆ ꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢆꢇ
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ꢚ ꢔꢓ ꢄ ꢅꢍ ꢑꢌꢖ ꢌꢁꢊ ꢘ ꢖꢑ ꢀ ꢑꢓ
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
10
SN54HC112
SN74HC112
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
5
MAX
MIN
3.4
17
MAX
MIN
4
MAX
2 V
4.5 V
6 V
25
29
50
20
24
f
t
t
MHz
max
pd
t
60
20
2 V
54
165
33
245
49
205
41
4.5 V
6 V
16
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
13
28
42
35
ns
ns
2 V
56
125
25
185
37
155
31
4.5 V
6 V
16
13
21
31
26
2 V
29
75
110
22
95
4.5 V
6 V
9
15
19
8
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
35
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢆ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢆꢆ ꢇ
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ꢚꢔ ꢓ ꢄ ꢅ ꢍ ꢑꢌ ꢖ ꢌꢁ ꢊ ꢘ ꢖꢑ ꢀꢑ ꢓ
SCLS099F − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
50%
50%
50%
Pulse
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
84088012A
8408801EA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
16
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
8408801FA
W
J
JM38510/65305BEA
SN54HC112J
SN74HC112D
CDIP
CDIP
SOIC
J
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC112DE4
SN74HC112DR
SN74HC112DRE4
SN74HC112DT
SN74HC112DTE4
SN74HC112N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
N
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC112N3
SN74HC112NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SNJ54HC112FK
SNJ54HC112J
SNJ54HC112W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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相关型号：
SN54HC114
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
TI
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