SN54HC161FH [TI]
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| 型号： | SN54HC161FH |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 计数器 |
| 文件： | 总14页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
SN54HC161 . . . J OR W PACKAGE
SN74HC161 . . . D OR N PACKAGE
(TOP VIEW)
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
CLR
CLK
A
V
CC
RCO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Synchronously Programmable
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT
ENP
GND
LOAD
description
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The ’HC161 are
4-bit binary counters. Synchronous operation is
provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when so instructed by
the count-enable (ENP, ENT) inputs and internal
gating. This mode of operation eliminates the
output counting spikes that are normally
associated with synchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock waveform.
SN54HC161 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
A
B
Q
Q
4
5
6
7
8
A
B
17
16
15
14
NC
C
NC
Q
Q
C
D
D
9 10 11 12 13
These counters are fully programmable; that is,
they can be preset to any number between 0 and
9 or 15. As presetting is synchronous, setting up
a low level at the load input disables the counter
and causes the outputs to agree with the setup
data after the next clock pulse, regardless of the
levels of the enable inputs.
NC – No internal connection
The clear function for the ’HC161 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop
outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54HC161 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC161 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
†
logic symbol
CTRDIV16
1
9
CT=0
CLR
M1
M2
G3
LOAD
15
3CT=15
RCO
10
ENT
7
2
ENP
CLK
G4
C5/2,3,4+
3
4
5
6
14
13
12
11
[1]
[2]
[4]
[8]
Q
A
A
B
C
D
1,5D
Q
B
Q
C
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
logic diagram (positive logic)
9
LOAD
10
ENT
15
RCO
†
LD
7
ENP
†
CK
2
CLK
CK
LD
1
CLR
R
M1
G2
1, 2T/1C3
14
13
Q
Q
A
B
G4
3D
4R
3
A
M1
G2
1, 2T/1C3
G4
3D
4R
4
B
M1
G2
1, 2T/1C3
12
Q
C
G4
3D
4R
5
C
M1
G2
1, 2T/1C3
11
Q
D
G4
3D
4R
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, J, N, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
logic symbol, each D/T flip-flop
LD (Load)
M1
G2
TE (Toggle Enable)
CK (Clock)
1, 2T/1C3
Q (Output)
G4
3D
4R
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
TG
TG
LD
TG
Q
TG
†
LD
†
CK
D
R
†
CK
TG
TG
†
†
CK
CK
†
The origins of LD and CK are shown in the logic diagram of the overall device.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC161
MIN NOM
SN74HC161
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
‡
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
A
–55
–40
°C
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
IL IH
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
= 2 V does not damage the device; however, functionally,
t
CC
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC161
SN74HC161
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 4 mA
4.5 V
6 V
0.26
0.26
±100
8
0.4
0.33
0.33
±1000
80
OL
= 5.2 mA
0.15
0.4
OL
I
I
V = V
I
or 0
6 V
±0.1
±1000
160
10
nA
µA
pF
I
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
C
2 V to 6 V
3
10
10
i
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC161
SN74HC161
A
V
UNIT
CC
MIN
0
MAX
6
MIN
0
MAX
4.2
21
MIN
0
MAX
5
2 V
4.5 V
6 V
f
Clock frequency
Pulse duration
0
31
0
0
25
MHz
clock
0
36
0
25
0
29
2 V
80
16
14
80
16
14
150
30
26
135
27
23
170
34
29
125
25
21
0
120
24
20
120
24
20
225
45
38
205
41
35
255
51
43
190
38
32
0
100
20
17
100
20
17
190
38
32
170
34
29
215
43
37
155
31
26
0
CLK high or low
CLR low
4.5 V
6 V
t
w
ns
2 V
4.5 V
6 V
2 V
A, B, C, or D
LOAD low
4.5 V
6 V
2 V
4.5 V
6 V
t
su
Setup time before CLK↑
ns
2 V
ENP, ENT
4.5 V
6 V
2 V
CLR inactive
4.5 V
6 V
2 V
t
h
Hold time, all synchronous inputs after CLK↑
4.5 V
6 V
0
0
0
ns
0
0
0
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
14
SN54HC161
SN74HC161
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
f
max
31
36
40
25
29
MHz
44
25
2 V
83
215
43
325
65
270
54
RCO
Any Q
RCO
Any Q
RCO
Any
4.5 V
6 V
24
20
37
55
46
CLK
ENT
CLR
2 V
80
205
41
310
62
255
51
t
pd
4.5 V
6 V
25
ns
21
35
53
43
2 V
62
195
39
295
59
245
49
4.5 V
6 V
17
14
33
50
42
2 V
105
21
210
42
315
63
265
53
4.5 V
6 V
18
36
54
45
t
t
ns
ns
PHL
2 V
110
22
220
44
330
66
275
55
4.5 V
6 V
19
37
56
47
2 V
38
75
110
22
95
4.5 V
6 V
8
15
19
t
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
60
pF
pd
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
Low-Level
Pulse
(see Note A)
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit
counter. The ’HC161 count in binary. Virtually any count mode (modulo-N, N -to-N , N -to-maximum) can be
1
2
1
used with this fast look-ahead circuit.
The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and
4.5-V V ). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every
CC
succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in
addition to the bipolar equivalents (LS, ALS, AS).
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
LSB
CTR
CLR
Clear (L)
CT=0
LOAD
ENT
M1
G3
RCO
RCO
RCO
RCO
3CT=MAX
Count (H)/
Disable (L)
ENP
CLK
G4
C5/2,3,4+
Load (L)
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
Count (H)/
Disable (L)
Clock
CTR
CLR
LOAD
ENT
CT=0
M1
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
CTR
CLR
LOAD
ENT
CT=0
M1
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
[1]
[2]
[3]
[4]
A
B
C
D
1,5D
Q
Q
Q
Q
A
B
C
D
CTR
CLR
CT=0
M1
LOAD
ENT
3CT=MAX
G3
ENP
CLK
G4
C5/2,3,4+
A
B
C
D
1,5D [1]
Q
Q
Q
Q
A
B
C
D
[2]
[3]
[4]
To More Significant Stages
Figure 2
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
The glitch on RCO is caused because the propagation delay of the rising edge of Q of the second stage is
A
shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q , Q , Q , and Q
A
B
C
D
(ENT × Q × Q × Q × Q ). The resulting glitch is about 7–12 ns in duration. Figure 3 shows the condition in
A
B
C
D
which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to
other stages. Q , Q , and Q of the first and second stage are at logic one, and Q of both stages are at logic
B
C
D
A
zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q and RCO of the
A
first stage go high. On the rising edge of the third clock pulse, Q and RCO of the first stage return to a low level,
A
and Q of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears
A
because of the race condition inside the chip.
1
2
3
4
5
CLK
ENT1
Q
, Q , Q
B1 C1 D1
Q
A1
RCO1, ENT2
Q
, Q , Q
B2 C2 D2
Q
A2
RCO2
Glitch (7–12 ns)
Figure 3
The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock
edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the
inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t ). In other words,
g
f
= 1/(t CLK-to-RCO + t ). For example, at 25°C at 4.5-V V , the clock-to-RCO propagation delay is
max
pd g CC
43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the
cascaded counters can use is 18 MHz. The following tables contain the f
applications that use more than two ’HC161 devices cascaded together.
, t , and f
specifications for
clock
w
max
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS297A – JANUARY 1996 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC161
SN74HC161
A
V
UNIT
CC
MIN
0
MAX
3.6
18
MIN
0
MAX
2.5
12
MIN
0
MAX
2.9
14
2 V
4.5 V
6 V
f
t
Clock frequency
0
0
0
MHz
clock
0
21
0
14
0
17
2 V
140
28
24
200
40
36
170
36
30
Pulse duration, CLK high or low
4.5 V
6 V
ns
w
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Note 3)
T = 25°C
A
SN54HC161
SN74HC161
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
3.6
18
MAX
MIN
2.5
12
MAX
MIN
2.9
14
MAX
2 V
4.5 V
6 V
f
MHz
max
21
14
17
NOTE 3: These limits apply only to applications that use more than two ’HC161 devices cascaded together.
If the ’HC161 are used as a single unit, or only two cascaded together, then the maximum clock frequency that
the device can use is not limited because of the glitch. In these situations, the device can be operated at the
maximum specifications.
A glitch can appear on RCO of a single ’HC161 device, depending on the relationship of ENT to CLK. Any
application that uses RCO to drive any input except an ENT of another cascaded ’HC161 must take this
into consideration.
13
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Copyright 1998, Texas Instruments Incorporated
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