SN54HC374-SP [TI]
具有三态输出的八路边沿触发式 D 型触发器;
| 型号： | SN54HC374-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的八路边沿触发式 D 型触发器 触发器 |
| 文件： | 总33页 (文件大小：2289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC374, SN74HC374
ZHCSPE9G –DECEMBER 1982 –REVISED APRIL 2022
SNx4HC374 具有三态输出的八路边沿触发D 类触发器
1 特性
2 说明
• 2V 至6V 的宽工作电压范围
• 高电流三态真实输出最多可驱动15 个LSTTL 负载
• 单个封装中包含八路D 类触发器
• 针对负载的完全并行访问
• 低功耗，ICC 最大80µA
• tpd 典型值= 14 ns
这些 8 位触发器具有专门设计用于驱动高电容或相对
低阻抗负载的三态输出。它们特别适合用于实现缓冲寄
存器、I/O 端口、双向总线驱动器和工作寄存器。
器件信息
器件型号
封装(1)
封装尺寸（标称值）
12.80mm × 7.50mm
7.20mm × 5.30mm
25.40mm × 6.35mm
15.00 mm × 5.30 mm
6.50mm × 4.40mm
26.92mm × 6.92mm
8.89mm × 8.89mm
13.09 mm × 6.92 mm
SN74HC374DW
SN74HC374DB
SN74HC374N
SN74HC374NS
SN74HC374PW
SN54HC374J
SN54HC374FK
SN54HC374W
SOIC (20)
SSOP (20)
PDIP (20)
SO (20)
• ±6mA 输出驱动（电压为5V 时）
• 低输出电流，最大值1 µA
TSSOP (20)
CDIP (20)
LCCC (20)
CFP (20)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS141
SN54HC374, SN74HC374
ZHCSPE9G –DECEMBER 1982 –REVISED APRIL 2022
www.ti.com.cn
Table of Contents
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Device Functional Modes............................................8
8 Power Supply Recommendations..................................9
9 Layout...............................................................................9
9.1 Layout Guidelines....................................................... 9
10 Device and Documentation Support..........................10
10.1 Documentation Support.......................................... 10
10.2 接收文档更新通知................................................... 10
10.3 支持资源..................................................................10
10.4 Trademarks.............................................................10
10.5 Electrostatic Discharge Caution..............................10
10.6 术语表..................................................................... 10
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 说明................................................................................... 1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) ..................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements..................................................5
5.6 Switching Characteristics............................................6
5.7 Switching Characteristics............................................6
5.8 Operating Characteristics........................................... 6
6 Parameter Measurement Information............................7
7 Detailed Description........................................................8
Information.................................................................... 11
3 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision F (December 2021) to Revision G (April 2022)
Page
• Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, DB was 70 is now 122.7,
N was 69 is now 84.6, NS was 60 is now 113.4, PW was 83 is now 131.8........................................................4
Changes from Revision E (August 2003) to Revision F (December 2021)
Page
• 更新了整个文档中的编号、格式、表格、图和交叉参考，以反映现代数据表标准..............................................1
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4 Pin Configuration and Functions
FK package
20-Pin LCCC
Top View
J, W, DB, DW, N, NS, or PW package
20-Pin CDIP, CFP, SSOP, SOIC, PDIP, SO, or TSSOP
Top View
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage range
VCC
IIK
7
±20
±20
±35
±70
150
150
–0.5
Input clamp current(2)
VI < 0 or VI > VCC
VO < 0 or VO > VCC
VO = 0 to VCC
mA
mA
mA
mA
°C
IOK
IO
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature
TJ
Tstg
Storage temperature range
°C
–65
(1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
SN54HC374
SN74HC374
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VIH
High-level input voltage
3.15
4.2
3.15
4.2
V
V
0.5
1.35
1.8
0.5
1.35
1.8
VIL
Low-level input voltage
VI
Input voltage
0
0
VCC
VCC
1000
500
400
125
0
0
VCC
VCC
1000
500
400
85
V
V
VO
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
Input transition rise and fall time
Operating free-air temperature
ns
°C
∆t/∆v
TA
–55
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
SN74HC374
DW (SOIC)
20 PINS
DB (SSOP)
20 PINS
N (PDIP)
20 PINS
NS (SO)
20 PINS
PW (TSSOP)
20 PINS
THERMAL METRIC
UNIT
RθJA
Junction-to-ambient thermal
109.1
76
122.7
81.6
77.5
46.1
84.6
72.5
65.3
55.3
113.4
78.6
78.4
47.1
131.8
72.2
82.8
21.5
°C/W
resistance(1)
RθJC (top)
RθJB
Junction-to-case (top) thermal
resistance
°C/W
°C/W
°C/W
Junction-to-board thermal
resistance
77.6
51.5
Junction-to-top characterization
parameter
ΨJT
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5.3 Thermal Information (continued)
SN74HC374
DW (SOIC)
DB (SSOP)
20 PINS
N (PDIP)
20 PINS
NS (SO)
20 PINS
PW (TSSOP)
20 PINS
THERMAL METRIC
20 PINS
UNIT
Junction-to-board
characterization parameter
ΨJB
77.1
77.1
N/A
65.2
N/A
78.1
N/A
82.4
N/A
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
SN54HC374
SN74HC374
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
1.9
TYP
MAX
MIN MAX
1.9
MIN MAX
1.9
2 V
4.5 V
6 V
1.998
4.499
5.999
4.3
4.4
4.4
4.4
IOH = –20 µA
5.9
5.9
5.9
VOH
VI = VIH or VIL
V
4.5 V
6 V
3.98
5.48
3.7
3.84
5.34
0.1
IOH = –6 mA
5.8
5.2
IOH = –7.8 mA
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
IOL = 20 µA
4.5 V
6 V
0.1
0.1
VOL
VI = VIH or VIL
0.1
0.1
0.1
V
IOL = 6 mA
4.5 V
6 V
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
±1000
±5
IOL = 7.8 mA
0.15
0.4
II
VI = VCC or 0
VO = VCC or 0
VI = VCC or 0,
6 V
±0.1
±1000
±10
160
10
nA
µA
µA
pF
IOZ
ICC
Ci
6 V
±0.01
IO = 0
6 V
80
2 V to 6 V
3
10
10
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
SN54HC374
SN74HC374
MIN
VCC
UNIT
MIN
MAX
6
MIN
MAX
4
MAX
2 V
4.5 V
6 V
5
fclock
Clock frequency
30
20
24 MHz
28
35
24
2 V
80
16
14
100
20
17
10
5
120
24
20
150
30
25
13
5
100
20
17
125
25
21
12
5
tw
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
4.5 V
6 V
ns
ns
ns
2 V
tsu
4.5 V
6 V
2 V
th
4.5 V
6 V
5
5
5
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5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see 图6-1)
TA = 25°C
SN54HC374
SN74HC374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC
UNIT
MIN
6
TYP
12
60
70
63
17
15
60
16
14
36
17
16
28
8
MAX
MIN
4
MAX
MIN
5
MAX
2 V
4.5 V
6 V
fmax
30
35
20
24
24
28
MHz
2 V
180
36
270
54
225
45
tpd
ten
tdis
tt
CLK
OE
Any Q
Any Q
Any Q
Any Q
4.5 V
6 V
ns
ns
ns
ns
31
46
38
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
150
30
225
45
190
38
OE
4.5 V
6 V
26
38
32
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
5.7 Switching Characteristics
over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see 图6-1)
TA = 25°C
SN54HC374
SN74HC374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC
UNIT
MIN TYP MAX
MIN MAX
MIN
5
MAX
2 V
4.5 V
6 V
6
30
35
12
60
70
80
22
19
70
25
22
45
17
13
fmax
24
28
MHz
2 V
230
46
345
69
290
58
tpd
ten
tt
CLK
OE
Any Q
Any Q
Any Q
4.5 V
6 V
ns
ns
ns
39
58
49
2 V
200
40
300
60
250
50
4.5 V
6 V
34
51
43
2 V
210
42
315
63
265
53
4.5 V
6 V
36
53
45
5.8 Operating Characteristics
TA = 25°C
PARAMETER
Power dissipation capacitance per flip-flop
TEST CONDITIONS
TYP
100
UNIT
pF
Cpd
No load
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6 Parameter Measurement Information
V
CC
PARAMETER
R
C
S1
S2
L
L
50 pF
or
t
Open
Closed
Closed
Open
PZH
S1
Test
t
1 kΩ
1 kΩ
en
t
R
Point
PZL
L
150 pF
From Output
Under Test
t
PHZ
Open
Closed
Open
t
50 pF
C
dis
L
(see Note A)
t
Closed
PLZ
S2
50 pF
or
t
or t
−−
Open
Open
pd
t
150 pF
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
w
90%
t
90%
50%
10%
50%
10%
Input
CC
Low-Level
Pulse
0 V
50%
50%
t
f
r
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PULSE DURATIONS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
t
50%
50%
0 V
V
0 V
t
PLH
PHL
t
t
PLZ
PZL
OH
≈V
CC
50%
≈V
Output
Waveform 1
(See Note B)
In-Phase
Output
CC
90%
t
90%
50%
10%
50%
10%
10%
t
V
OL
V
OL
t
r
f
t
t
t
PLH
PZH
PHZ
PHL
90%
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈0 V
OL
t
f
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
t
are the same as t
en
are the same as t .
t
and t
PHL
pd
图6-1. Load Circuit and Voltage Waveforms
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7 Detailed Description
7.1 Overview
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-
impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
An output-enable ( OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram
7.3 Device Functional Modes
表7-1. Function Table
(each flip-flop)
INPUTS
OUTPUT
OE
L
CLK
D
H
L
Q
H
↑
↑
L
L
L
H or L
X
X
X
Q0
Z
H
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-May-2023
PACKAGING INFORMATION
Orderable Device
5962-8407101VRA
5962-8407101VSA
84071012A
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
CDIP
CFP
J
20
20
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
5962-8407101VR
Samples
Samples
Samples
A
SNV54HC374J
ACTIVE
ACTIVE
W
1
1
Non-RoHS
& Green
SNPB
SNPB
-55 to 125
5962-8407101VS
A
SNV54HC374W
LCCC
FK
Non-RoHS
& Green
-55 to 125
84071012A
SNJ54HC
374FK
8407101RA
8407101SA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
J
20
20
20
20
20
1
1
1
1
1
Non-RoHS
& Green
SNPB
SNPB
SNPB
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8407101RA
SNJ54HC374J
Samples
Samples
Samples
Samples
Samples
Non-RoHS
& Green
8407101SA
SNJ54HC374W
JM38510/65602BRA
M38510/65602BRA
SN54HC374J
CDIP
CDIP
CDIP
Non-RoHS
& Green
JM38510/
65602BRA
J
Non-RoHS
& Green
JM38510/
65602BRA
J
Non-RoHS
& Green
SN54HC374J
SN74HC374DBR
SN74HC374DWR
SN74HC374DWRG4
SN74HC374N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
PDIP
PDIP
SO
DB
DW
DW
N
20
20
20
20
20
20
20
20
2000 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
HC374
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
HC374
HC374
20
20
RoHS & Green
RoHS & Green
SN74HC374N
SN74HC374N
HC374
SN74HC374NE4
SN74HC374NSR
SN74HC374PWR
SNJ54HC374FK
N
NS
PW
FK
2000 RoHS & Green
2000 RoHS & Green
TSSOP
LCCC
HC374
1
Non-RoHS
& Green
84071012A
SNJ54HC
374FK
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SNJ54HC374J
SNJ54HC374W
ACTIVE
CDIP
CFP
J
20
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8407101RA
SNJ54HC374J
Samples
Samples
ACTIVE
W
1
Non-RoHS
& Green
SNPB
8407101SA
SNJ54HC374W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
OTHER QUALIFIED VERSIONS OF SN54HC374, SN54HC374-SP, SN74HC374 :
Catalog : SN74HC374, SN54HC374
•
Military : SN54HC374
•
Space : SN54HC374-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC374DBR
SN74HC374DWR
SN74HC374DWR
SN74HC374NSR
SN74HC374NSR
SN74HC374PWR
SN74HC374PWR
SSOP
SOIC
SOIC
SO
DB
DW
DW
NS
20
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
24.4
24.4
24.4
24.4
16.4
16.4
8.2
10.9
10.9
8.4
7.5
13.3
13.3
13.0
13.0
7.0
2.5
2.7
2.7
2.5
2.5
1.4
1.4
12.0
12.0
12.0
12.0
12.0
8.0
16.0
24.0
24.0
24.0
24.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
SO
NS
8.4
TSSOP
TSSOP
PW
PW
6.95
6.95
7.0
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC374DBR
SN74HC374DWR
SN74HC374DWR
SN74HC374NSR
SN74HC374NSR
SN74HC374PWR
SN74HC374PWR
SSOP
SOIC
SOIC
SO
DB
DW
DW
NS
20
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
2000
356.0
367.0
367.0
367.0
367.0
356.0
356.0
356.0
367.0
367.0
367.0
367.0
356.0
356.0
35.0
45.0
45.0
45.0
45.0
35.0
35.0
SO
NS
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-8407101VSA
84071012A
W
FK
W
N
CFP
LCCC
CFP
20
20
20
20
20
20
20
1
1
506.98
506.98
506.98
506
26.16
12.06
26.16
13.97
13.97
12.06
26.16
6220
2030
6220
11230
11230
2030
6220
NA
NA
8407101SA
1
NA
SN74HC374N
SN74HC374NE4
SNJ54HC374FK
SNJ54HC374W
PDIP
PDIP
LCCC
CFP
20
20
1
4.32
4.32
NA
N
506
FK
W
506.98
506.98
1
NA
Pack Materials-Page 3
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
5.85
NOTE 3
10
11
0.38
0.22
20X
5.6
5.0
0.1
C A B
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
FK 20
8.89 x 8.89, 1.27 mm pitch
LCCC - 2.03 mm max height
LEADLESS CERAMIC CHIP CARRIER
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229370\/A\
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
2
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 - 8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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