SN54HC377J [TI]
OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE; 八路D型触发器与时钟使能
| 型号： | SN54HC377J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE |
| 文件： | 总13页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
SN54HC377 . . . J OR W PACKAGE
SN74HC377 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
CLKEN
1Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
Typical t = 12 ns
pd
±4-mA Output Drive at 5 V
1D
Low Input Current of 1 µA Max
Eight Flip-Flops With Single-Rail Outputs
2D
17 7D
16 7Q
15 6Q
2Q
3Q
Clock Enable Latched to Avoid False
Clocking
3D
14
6D
4D
13 5D
12 5Q
11 CLK
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
4Q
GND 10
– Pattern Generators
SN54HC377 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
These devices are positive-edge-triggered octal
D-type flip-flops with an enable input. The ’HC377
devices are similar to the ’HC273 devices, but
feature a latched clock-enable (CLKEN) input
instead of a common clear.
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse, if CLKEN is low. Clock triggering
occurs at a particular voltage level and is not
directly related to the transition time of the
positive-going pulse. When CLK is at either the
high or low level, the D input has no effect at the
output. These devices are designed to prevent
false clocking by transitions at CLKEN.
15 6Q
14
6D
9 10 11 12 13
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
SN74HC377N
SN74HC377N
Tube
SN74HC377DW
SN74HC377DWR
SN74HC377NSR
SNJ54HC377J
SNJ54HC377W
SNJ54HC377FK
–40°C to 85°C
SOIC – DW
HC377
Tape and reel
Tape and reel
Tube
SOP – NS
CDIP – J
HC377
SNJ54HC377J
SNJ54HC377W
SNJ54HC377FK
CFP – W
LCCC – FK
Tube
–55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
ꢉ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢓ ꢌꢎ ꢐꢗ ꢒ ꢎꢆꢰꢂ ꢆꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢇꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢇ
ꢉꢅ ꢊꢋ ꢌ ꢍ ꢎꢊ ꢏꢐꢑ ꢒꢌ ꢓ ꢐ ꢎꢒꢌꢉ ꢐ ꢀ
ꢔꢓ ꢊ ꢄ ꢅ ꢌ ꢉꢅ ꢕ ꢑꢁꢋ ꢖꢌ ꢑ
SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLKEN CLK
D
X
H
L
H
L
X
↑
Q
0
H
L
↑
L
X
L
X
Q
0
logic diagram (positive logic)
1
CLKEN
11
CLK
C1
1D
2
5
6
3
1Q
2Q
3Q
1D
C1
1D
4
2D
C1
1D
7
3D
C1
1D
9
12
15
16
19
8
4Q
5Q
6Q
7Q
8Q
4D
C1
1D
13
5D
C1
1D
14
6D
C1
1D
17
7D
C1
1D
18
8D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
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ꢅ
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ꢇ
ꢇ
ꢀ
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ꢔ ꢓꢊ ꢄ ꢅꢌ ꢉ ꢅꢕ ꢑ ꢁꢋ ꢖꢌ
SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC377
MIN NOM
SN74HC377
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
–55
–40
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢇꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢇ
ꢉꢅ ꢊꢋ ꢌ ꢍ ꢎꢊ ꢏꢐꢑ ꢒꢌ ꢓ ꢐ ꢎꢒꢌꢉ ꢐ ꢀ
ꢔꢓ ꢊ ꢄ ꢅ ꢌ ꢉꢅ ꢕ ꢑꢁꢋ ꢖꢌ ꢑ
SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC377
SN74HC377
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= –20 µA
OH
5.9
V
V
V = V or V
IH
V
OH
OL
I
IL
I
I
= –4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
0.1
V = V or V
V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.26
0.26
±100
8
0.4
0.33
0.33
±1000
80
OL
= 5.2 mA
0.15
0.4
OL
I
I
V = V
I
or 0
6 V
±0.1
±1000
160
10
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
i
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC377
SN74HC377
A
V
UNIT
CC
MIN
MAX
5
MIN
MAX
3
MIN
MAX
4
2 V
4.5 V
6 V
25
16
20
f
t
Clock frequency
MHz
clock
29
19
23
2 V
100
20
17
100
20
17
100
20
17
5
150
30
25
150
30
25
150
30
25
5
125
25
21
125
25
21
125
25
21
5
4.5 V
6 V
Pulse duration, CLK high or low
ns
ns
ns
w
2 V
4.5 V
6 V
D
t
t
Setup time before CLK↑
su
2 V
4.5 V
6 V
CLKEN high or low
2 V
Hold time after CLK↑
CLKEN inactive or active, data
4.5 V
6 V
5
5
5
h
5
5
5
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ ꢅꢊꢋꢌ ꢍꢎꢊ ꢏꢐ ꢑ ꢒ ꢌꢓ ꢐ ꢎꢒ ꢌꢉ ꢐ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢇ
ꢀ
ꢑ
ꢔ
ꢓ
ꢊ
ꢄ
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ꢉ
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SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
11
SN54HC377
SN74HC377
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
5
MAX
MIN
3
MAX
MIN
4
MAX
2 V
4.5 V
6 V
25
29
54
16
19
20
23
f
t
t
MHz
max
pd
t
64
2 V
56
160
32
27
75
15
13
240
48
200
40
34
95
19
16
4.5 V
6 V
15
CLK
Any
Any
ns
ns
12
41
2 V
38
110
22
4.5 V
6 V
8
6
19
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per flip-flop
TEST CONDITIONS
TYP
UNIT
C
No load
30
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢇꢈ ꢀꢁ ꢇ ꢃ ꢄꢅꢆ ꢇ ꢇ
ꢉꢅ ꢊꢋ ꢌ ꢍ ꢎꢊ ꢏꢐꢑ ꢒꢌ ꢓ ꢐ ꢎꢒꢌꢉ ꢐ ꢀ
ꢔꢓ ꢊ ꢄ ꢅ ꢌ ꢉꢅ ꢕ ꢑꢁꢋ ꢖꢌ ꢑ
SCLS307B– JANUARY 1996 – REVISED JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
High-Level
Pulse
50%
50%
50%
From Output
Under Test
Test
Point
0 V
t
w
C
= 50 pF
L
V
CC
(see Note A)
Low-Level
Pulse
50%
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
CC
Input
50%
50%
0 V
V
t
t
PLH
PHL
90%
V
CC
OH
In-Phase
Output
Reference
Input
90%
t
50%
50%
10%
50%
10%
V
OL
0 V
V
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
V
CC
OH
OL
Data
Input
90%
90%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
50%
10%
50%
10%
0 V
V
t
t
t
r
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
SOIC
Drawing
5962-87807012A
5962-8780701RA
SN54HC377J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
20
20
20
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
SN74HC377DW
DW
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SN74HC377DWR
SN74HC377N
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
SO
DW
N
20
20
20
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC377NSR
NS
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SNJ54HC377FK
SNJ54HC377J
ACTIVE
ACTIVE
LCCC
CDIP
FK
J
20
20
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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