SN54HC74W [TI]
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET; 双D型上升沿触发的触发器具有清零和预设型号: | SN54HC74W |
厂家: | TEXAS INSTRUMENTS |
描述: | DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
文件: | 总16页 (文件大小:530K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
SN54HC74 . . . J OR W PACKAGE
SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 40-µA Max I
CC
1CLR
1D
V
CC
2CLR
1
2
3
4
5
6
7
14
13
Typical t = 15 ns
pd
±4-mA Output Drive at 5 V
1CLK
1PRE
1Q
12 2D
Low Input Current of 1 µA Max
11
10
9
2CLK
2PRE
2Q
description/ordering information
1Q
8
The ’HC74 devices contain two independent
D-type positive-edge-triggered flip-flops. A low
levelatthepreset(PRE)orclear(CLR)inputssets
or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.
GND
2Q
SN54HC74 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
2D
1CLK
NC
4
5
6
7
8
NC
17
16
2CLK
1PRE
NC
15 NC
14
2PRE
1Q
9 10 11 12 13
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HC74N
SN74HC74N
SN74HC74D
SN74HC74DR
SN74HC74DT
SN74HC74NSR
SN74HC74DBR
SN74HC74PW
SN74HC74PWR
SN74HC74PWT
SNJ54HC74J
HC74
–40°C to 85°C
SOP – NS
HC74
HC74
SSOP – DB
TSSOP – PW
HC74
CDIP – J
CFP – W
LCCC – FK
SNJ54HC74J
SNJ54HC74W
SNJ54HC74FK
–55°C to 125°C
SNJ54HC74W
SNJ54HC74FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram (positive logic)
PRE
C
CLK
C
Q
TG
C
C
TG
C
C
C
C
D
TG
C
TG
C
Q
CLR
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54HC74
SN74HC74
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
∆t/∆v
Input transition rise/fall time
= 4.5 V
= 6 V
ns
T
A
Operating free-air temperature
–55
–40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC74
SN74HC74
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 4 mA
4.5 V
6 V
0.26
0.26
±100
4
0.4
0.33
0.33
±1000
40
OL
= 5.2 mA
0.15
0.4
OL
I
I
V = V
I
or 0
6 V
±0.1
±1000
80
nA
µA
pF
I
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
C
2 V to 6 V
3
10
10
10
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC74
SN74HC74
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
MIN
MAX
2 V
4.5 V
6 V
4.2
21
25
5
25
29
f
Clock frequency
Pulse duration
31
MHz
clock
0
100
20
17
80
16
14
100
20
17
25
5
36
0
150
30
25
120
24
20
150
30
25
40
8
0
125
25
21
100
20
17
125
25
21
30
6
2 V
PRE or CLR low
CLK high or low
Data
4.5 V
6 V
t
w
ns
2 V
4.5 V
6 V
2 V
4.5 V
6 V
t
t
Setup time before CLK↑
ns
ns
su
2 V
PRE or CLR inactive
4.5 V
6 V
4
7
5
2 V
0
0
0
Hold time, data after CLK↑
4.5 V
6 V
0
0
0
h
0
0
0
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
10
SN54HC74
SN74HC74
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
f
t
t
31
36
50
25
29
MHz
max
pd
t
60
25
2 V
70
230
46
345
69
290
58
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
4.5 V
6 V
20
15
39
59
49
ns
ns
2 V
70
175
35
250
50
220
44
4.5 V
6 V
20
15
30
42
37
2 V
28
75
110
22
95
4.5 V
6 V
8
15
19
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per flip-flop
TEST CONDITIONS
TYP
UNIT
C
No load
35
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
From Output
Under Test
Test
Point
High-Level
Pulse
50%
50%
0 V
C
= 50 pF
L
t
w
(see Note A)
V
CC
Low-Level
Pulse
50%
50%
LOAD CIRCUIT
0 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
V
V
CC
CC
Reference
Input
50%
Input
50%
50%
t
0 V
V
0 V
V
t
t
PLH
t
h
PHL
su
CC
OH
In-Phase
Output
Data
Input
90%
t
90%
90%
90%
50%
10%
50%
10%
50%
10%
50%
10%
V
0 V
OL
t
r
f
f
t
t
r
f
t
t
PLH
PHL
90%
V
V
OH
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
OL
t
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CFP
Drawing
5962-8405601VCA
5962-8405601VDA
84056012A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
J
W
FK
J
14
14
20
14
14
20
14
14
14
14
14
1
1
1
1
1
1
1
1
1
None
None
None
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
LCCC
CDIP
CFP
8405601CA
8405601DA
W
FK
J
JM38510/65302B2A
JM38510/65302BCA
JM38510/65302BDA
SN54HC74J
LCCC
CDIP
CFP
W
J
CDIP
SSOP
SOIC
SN74HC74ADBLE
SN74HC74D
DB
D
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC74DBLE
SN74HC74DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
None
Call TI
Call TI
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC74DR
SN74HC74DT
SN74HC74N
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
D
D
N
14
14
14
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC74N3
OBSOLETE
ACTIVE
PDIP
SO
N
14
14
None
Call TI
Call TI
SN74HC74NSR
NS
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC74PW
ACTIVE
TSSOP
PW
14
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74HC74PWLE
SN74HC74PWR
OBSOLETE TSSOP
PW
PW
14
14
None
Call TI
Call TI
ACTIVE
TSSOP
2000
250
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74HC74PWT
ACTIVE
TSSOP
PW
14
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SNJ54HC74FK
SNJ54HC74J
SNJ54HC74W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2005
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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