SN54HCT74WR [TI]
HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, DFP-14;
| 型号： | SN54HCT74WR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, DFP-14 触发器 |
| 文件： | 总5页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HCT74, SN74HCT74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS169B – DECEMBER 1982 – REVISED MAY 1997
SN54HCT74 . . . J OR W PACKAGE
SN74HCT74 . . . D, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
1CLR
1D
V
CC
2CLR
2D
1
2
3
4
5
6
7
14
13
12
11
1CLK
1PRE
1Q
2CLK
10 2PRE
description
9
8
1Q
2Q
2Q
The ’HCT74 contain two independent D-type
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the
D input may be changed without affecting the
levels at the outputs.
GND
SN54HCT74 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
2D
1CLK
NC
4
5
6
7
8
NC
17
16
2CLK
1PRE
NC
15 NC
14
9 10 11 12 13
2PRE
1Q
The SN54HCT74 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT74 is characterized for
operation from –40°C to 85°C.
NC – No internal connection
FUNCTION TABLE
INPUTS
OUTPUT
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
†
This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT74, SN74HCT74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS169B – DECEMBER 1982 – REVISED MAY 1997
†
logic symbol
4
1PRE
1CLK
1D
S
5
6
3
1Q
1Q
C1
2
1D
R
1
1CLR
2PRE
2CLK
2D
10
11
12
13
9
8
2Q
2Q
2CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, PW, and W packages.
logic diagram (positive logic)
PRE
C
CLK
C
C
Q
TG
C
TG
C
C
C
C
D
TG
TG
C
Q
C
CLR
‡
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT74, SN74HCT74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS169B – DECEMBER 1982 – REVISED MAY 1997
recommended operating conditions
SN54HCT74
MIN NOM
SN74HCT74
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0
0.8
0
0.8
V
CC
0
V
V
0
V
V
V
CC
CC
Output voltage
0
0
V
O
CC
CC
t
Input transition (rise and fall) time
Operating free-air temperature
0
500
125
0
500
85
ns
°C
t
T
–55
–40
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT74
SN74HCT74
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –4 mA
= 20 µA
= 4 mA
4.4 4.499
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
OH
I
IL
IL
3.98
4.3
0.001
0.17
3.7
3.84
0.1
0.26
±100
4
0.1
0.4
0.1
0.33
V = V or V
V
OL
I
IH
I
I
V = V
I
or 0
5.5 V
5.5 V
±0.1
±1000
80
±1000
40
nA
I
CC
CC
V = V
I
or 0,
I
O
= 0
µA
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
CC
.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HCT74
SN74HCT74
A
V
UNIT
CC
MIN
0
MAX
27
MIN
0
MAX
18
MIN
0
MAX
22
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
Clock frequency
Pulse duration
MHz
clock
0
30
0
20
0
24
16
14
18
16
12
11
0
24
21
27
24
18
16
0
20
18
23
21
15
14
0
PRE or CLR low
CLK high or low
Data
ns
w
t
t
Setup time before CLK↑
ns
ns
su
PRE or CLR inactive
0
0
0
0
0
0
Hold time, data after CLK↑
h
0
0
0
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT74, SN74HCT74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS169B – DECEMBER 1982 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
40
SN54HCT74
SN74HCT74
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
27
MAX
MIN
18
MAX
MIN
22
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
t
MHz
max
pd
t
30
46
20
24
21
35
31
28
25
15
14
53
48
42
38
22
20
44
40
35
31
19
17
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
17
ns
ns
20
18
8
7
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per flip-flop
TEST CONDITIONS
TYP
UNIT
C
No load
35
pF
pd
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
From Output
Under Test
Test
Point
High-Level
1.3 V
1.3 V
1.3 V
Pulse
C
= 50 pF
L
t
w
(see Note A)
3 V
0 V
Low-Level
Pulse
1.3 V
LOAD CIRCUIT
3 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
1.3 V
1.3 V
t
t
PLH
PHL
90%
3 V
V
V
OH
In-Phase
Output
Reference
Input
90%
t
1.3 V
1.3 V
10%
1.3 V
10%
0 V
OL
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
3 V
0 V
Out-of-
Phase
Output
V
V
Data
Input
OH
2.7 V
2.7 V
90%
t
1.3 V
0.3 V
1.3 V
0.3 V
1.3 V
10%
1.3 V
10%
OL
t
t
t
r
f
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
max
D. The outputs are measured one at a time with one input transition per measurement.
E. and t are the same as t
t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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