SN54LS06FK [TI]
LS SERIES, HEX 1-INPUT INVERT GATE, CQCC20, CERAMIC, CC-20;
| 型号： | SN54LS06FK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LS SERIES, HEX 1-INPUT INVERT GATE, CQCC20, CERAMIC, CC-20 输出元件 高压 驱动 |
| 文件： | 总6页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
The SN74LS16 is obsolete
and is no longer supplied.
SDLS020B – MAY 1990 – REVISED JANUARY 2002
SN54LS06 . . . J PACKAGE
SN74LS06, SN74LS16 . . . D, N, OR NS PACKAGE
(TOP VIEW)
Convert TTL Voltage Levels to MOS Levels
High Sink-Current Capability
Input Clamping Diodes Simplify System
Design
1A
1Y
2A
2Y
3A
V
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
6A
6Y
5A
5Y
4A
4Y
Open-Collector Driver for Indicator Lamps
and Relays
Inputs Fully Compatible With Most TTL
Circuits
3Y
GND
8
description
These hex inverter buffers/drivers feature
high-voltage open-collector outputs to interface
with high-level circuits (such as MOS), or for
driving high-current loads, and also are character-
ized for use as inverter buffers for driving TTL
inputs. The ’LS06 devices have a rated output
voltage of 30 V, and the SN74LS16 has a rated
output voltage of 15 V. The maximum sink current
for the SN54LS06 is 30 mA, and for the
SN74LS06 and SN74LS16 is 40 mA.
SN54LS06 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
6Y
NC
5A
NC
5Y
2A
NC
2Y
4
5
6
7
8
17
16
15
14
NC
3A
9 10 11 12 13
These devices are compatible with most TTL
families. Inputs are diode-clamped to minimize
transmission effects, which simplifies design.
Typical power dissipation is 175 mW and average
propagation delay time is 8 ns.
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LS06D
SOIC – D
SOP – NS
LS06
Tape and reel
Tape and reel
SN74LS06DR
SN74LS06NSR
SN74LS06DBR
SN74LS06N
0°C to 70°C
74LS06
SSOP – DB Tape and reel
LS06
PDIP – N
Tube
Tube
Tube
SN74LS06N
SN54LS06J
SNJ54LS06J
SN54LS06J
CDIP – J
–55°C to 125°C
SNJ54LS06J
LCCC – FK
Tube
SNJ54LS06FK
SNJ54LS06FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
The SN74LS16 is obsolete
and is no longer supplied.
SDLS020B – MAY 1990 – REVISED JANUARY 2002
logic diagram (positive logic)
2
4
6
1
1Y
2Y
3Y
4Y
5Y
6Y
1A
3
2A
5
3A
9
8
10
12
4A
11
5A
13
6A
Pin numbers shown are for the D, J, N, and NS packages.
schematic (each gate)
V
CC
2.5 kΩ
9 kΩ
1 kΩ
15 kΩ
Output
2.5 kΩ
Input
2 kΩ
2 kΩ
GND
Resistor values shown are nominal.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
The SN74LS16 is obsolete
and is no longer supplied.
SDLS020B – MAY 1990 – REVISED JANUARY 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Output voltage, V (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
O
SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN74LS06
SN74LS16
SN54LS06
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.8
30
0.8
30
15
40
70
V
’LS06
V
V
OH
High-level output voltage
SN74LS16
V
I
Low-level output current
30
mA
°C
OL
T
A
Operating free-air temperature
–55
125
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LS06
SN54LS06
SN74LS16
‡
PARAMETER
UNIT
TEST CONDITIONS
I = –12 mA
§
§
MIN TYP
MAX
–1.5
0.25
MIN TYP
MAX
–1.5
0.25
0.25
0.4
V
IK
V
V
= MIN,
= MIN,
V
V
CC
I
’LS06,
V
OH
= 30 V
I
V
IL
= 0.8 V
OH
CC
SN74LS16,
V
OH
= 15 V
I
I
I
= 16 mA
= 30 mA
= 40 mA
0.25
0.4
0.7
0.25
OL
OL
OL
V
OL
V
CC
= MIN,
V
IH
= 2 V
V
0.7
1
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX,
= MAX,
= MAX,
= MAX
= MAX
V = 7 V
I
1
20
mA
µA
I
V = 2.4 V
I
20
IH
V = 0.4 V
I
–0.2
18
–0.2
18
mA
mA
mA
IL
CCH
CCL
60
60
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, and T = 25°C.
CC
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
The SN74LS16 is obsolete
and is no longer supplied.
SDLS020B – MAY 1990 – REVISED JANUARY 2002
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
CC
A
FROM
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
MIN
MAX
UNIT
(INPUT)
t
t
7
15
20
PLH
A
R
= 110 Ω,
C
= 15 pF
L
ns
Y
L
10
PHL
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
The SN74LS16 is obsolete
and is no longer supplied.
SDLS020B – MAY 1990 – REVISED JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2001, Texas Instruments Incorporated
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