SN54LS490WR [TI]
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDFP16, CERAMIC, FP-16;
| 型号： | SN54LS490WR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDFP16, CERAMIC, FP-16 计数器 |
| 文件： | 总8页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
SN54LS490 . . . J OR W PACKAGE
SN74LS490 . . . D OR N PACKAGE
(TOP VIEW)
Dual Versions of the SN54LS90 and
SN74LS90 Counters
Individual Clock, Direct Clear, and Set-to-9
Inputs for Each Decade Counter
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLK
1CLR
V
CC
2CLK
2CLR
Dual Counters Can Significantly Improve
System Densities as Package Count Can
Be Reduced by 50%
1Q
A
1SET9
2Q
A
1Q
2SET9
Maximum Count Frequency of
25 MHz . . . 35 MHz Typical
B
1Q
C
2Q
B
1Q
2Q
2Q
D
C
D
Buffered Outputs Reduce Possibility of
Collector Commutation
GND
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
SN54LS490 . . . FK PACKAGE
(TOP VIEW)
description
3
2
1 20 19
18
2CLR
1Q
4
5
6
7
8
A
Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to
implement two individual 4-bit decade counters in
a single package. Each decade counter has
individual clock (1CLK, 2CLK), clear (1CLR,
2CLR), and set-to-9 (1SET9, 2SET9) inputs. BCD
count sequences of any length up to
divide-by-100 can be implemented with a single
’LS490 device. Buffering on each output is
provided to significantly reduce susceptibility to
collector commutation. All inputs are diode
clamped to reduce the effects of line ringing. The
counters have parallel outputs from each counter
stage so that submultiples of the input count
frequency are available for system timing signals.
2Q
1SET9
NC
17
16
15
14
A
NC
2SET9
1Q
B
2Q
B
1Q
C
9 10 11 12 13
NC – No internal connection
The SN54LS490 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LS490 is characterized for use in industrial systems operating from 0°C to 70°C.
CLEAR/SET-TO-9 FUNCTION TABLE
(each counter)
INPUTS
OUTPUTS
CLR SET9
Q
Q
Q
Q
D
A
B
C
H
L
L
L
H
L
L
L
L
L
H
L
L
H
Count
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
BCD COUNT SEQUENCE
(each counter)
OUTPUTS
COUNT
Q
Q
Q
Q
A
D
C
B
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
L
H
L
H
H
L
H
L
L
L
H
†
logic symbol
CTRDIV10
3
5
6
7
2
4
1
1Q
1Q
0
3
A
1CLR
1SET9
1CLK
CT=0
CT=9
+
B
CT
1Q
1Q
C
D
13
11
10
9
14
12
15
2Q
2Q
A
2CLR
2SET9
2CLK
B
2Q
2Q
C
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
schematics of inputs and outputs
EQUIVALENT OF
EACH CLK INPUT
EQUIVALENT OF
EACH CLR AND SET9 INPUT
TYPICAL OF
ALL OUTPUTS
V
CC
V
CC
V
CC
43 kΩ NOM
120 Ω NOM
18 kΩ NOM
Input
Input
Output
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
logic diagram (each counter)
4, 12
SET9
3, 13
S
R
Q
A
1, 15
CLK
T
5, 11
Q
B
T
R
6, 10
Q
C
T
R
7, 9
S
R
Q
D
T
2, 14
CLR
Pin numbers shown are for the D, J, N, and W packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Clear and set-to-9 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Clock input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54LS490
MIN NOM
SN74LS490
MIN NOM
UNIT
MAX
5.5
–400
4
MAX
5.25
–400
8
V
Supply voltage
4.5
5
4.75
5
V
µA
mA
MHz
ns
CC
OH
OL
I
I
f
t
t
High-level output current
Low-level output current
Count frequency
0
25
0
25
count
w
Pulse width (any input)
Clear or set-to-9 inactive-state setup time
Operating free-air temperature
20
20
‡
‡
25↓
25↓
ns
su
T
A
–55
125
0
70
°C
‡
The arrow (↓) indicates that the falling edge of the clock pulse is used for reference.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LS490
SN74LS490
†
PARAMETER
UNIT
TEST CONDITIONS
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
High-level input voltage
Low-level input voltage
Input clamp voltage
2
2
V
V
V
IH
0.7
0.8
IL
V
CC
= MIN,
I = –18 mA
I
–1.5
–1.5
IK
V
V
= MIN, V = 2 V,
IH
IL
CC
IL
V
High-level output voltage
2.5
3.4
2.7
3.4
V
OH
OL
= V max
V
V
V
= MIN,
= 2 V,
I
I
= 4 mA
= 8 mA
0.25
0.4
0.25
0.35
0.4
0.5
0.1
0.2
CC
IH
IL
OL
V
Low-level output voltage
V
= V max
OL
IL
Input current
at maximum
input voltage
CLR, SET9
CLK
V
= MAX,
= MAX,
V = 7 V
I
0.1
0.2
CC
CC
I
I
mA
V
V = 5.5 V
I
CLR, SET9
CLK
20
100
20
100
High-level
input current
I
I
V
= MAX,
= MAX,
V = 2.7 V
µA
IH
CC
CC
I
CLR, SET9
CLK
–0.4
–1.6
–100
26
–0.4
–1.6
–100
26
Low-level
input current
V
V = 0.4 V
I
mA
IL
§
I
I
Short-circuit output current
Supply current
V
V
= MAX
= MAX,
–20
–20
mA
mA
OS
CC
CC
See Note 3
15
15
CC
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
CC
A
NOTE 3:
I
is measured with all outputs open, both CLR inputs grounded following momentary connection to 4.5 V, and all other inputs
CC
grounded.
switching characteristics, V
= 5 V, T = 25°C (see Figures 1 and 2)
CC
A
FROM
(INPUT)
TO
PARAMETER
TEST CONDITIONS
(OUTPUT)
MIN
TYP
MAX
UNIT
CLK
Q
C
= 15 pF,
R
= 2 kΩ
25
35
12
13
24
26
32
36
24
24
20
MHz
f
A
A
L
L
L
L
max
20
20
39
39
54
54
39
39
36
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PLH
PHL
CLK
Q
C
= 15 pF,
R
= 2 kΩ
ns
ns
CLK
Q
Q
C
= 15 pF,
R
= 2 kΩ
B,
Q
D
L
L
CLK
CLR
C
C
C
= 15 pF,
= 15 pF,
= 15 pF,
R
R
R
= 2 kΩ
= 2 kΩ
= 2 kΩ
ns
ns
ns
C
L
L
L
L
L
L
Any
Q
Q
Q
A,
D
C
SET9
Q
B,
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
SET9
1.3 V
1.3 V
t
su
3 V
0 V
1.3 V
1.3 V
CLR
CLK
t
t
w(clock)
su
3 V
0 V
1.3 V
1.3 V
1.3 V
1.3 V
t
t
PLH
(Measure at
+ 1)
PHL
(Measure at
t + 2)
n
t
t
PHL
PLH
t
n
V
V
OH
1.3 V
1.3 V
1.3 V
1.3 V
Q
Q
A
D
OL
t
t
PLH
(Measure at
PHL
(Measure at
t
t
t
PHL
PHL
PHL
t
+ 2)
t
+ 4)
n
n
V
OH
OL
1.3 V
1.3 V
1.3 V
1.3 V
V
t
t
PLH
PLH
(Measure at
(Measure at
t
t
t
PHL
PHL
PHL
t
+ 4)
t
+ 8)
n
n
V
V
OH
Q
1.3 V
1.3 V
1.3 V
1.3 V
C
OL
t
t
PHL
PHL
(Measure at
(Measure at
t
t
t
PLH
PHL
PHL
t
+ 8)
t + 10)
n
n
V
OH
OL
1.3 V
1.3 V
1.3 V
1.3 V
Q
B
V
NOTE A: Input pulses are supplied by a generator having the following characteristics: t ≤ 15 ns, t ≤ 6 ns, PRR ≤ 1 MHz, duty cycle = 50%,
r
f
Z
O
≈ 50 Ω.
Figure 1. Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
Test
Point
Test
Point
R
L
S1
V
CC
R
From Output
Under Test
L
(see Note B)
C
L
From Output
Under Test
R
L
(see Note B)
(see Note A)
5 kΩ
C
L
From Output
Under Test
Test
Point
(see Note A)
C
L
(see Note A)
S2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
w
h
t
su
3 V
1.3 V
Data
Input
Low-Level
Pulse
1.3 V
1.3 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
1.5 V
Waveform 1
S2 Open
(see Notes C
and F)
t
PHL
t
PLH
1.3 V
V
In-Phase
Output
(see Note F)
OH
OL
V
V
+ 0.3 V
OL
1.3 V
1.3 V
1.3 V
V
t
PHZ
t
PLH
t
PZH
t
PHL
Waveform 2
S2 Closed
(see Notes C
and F)
V
OH
OL
– 0.3 V
Out-of-Phase
Output
OH
1.3 V
1.3 V
V
(see Note F)
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 15 ns, t ≤ 6 ns.
O
r
f
F. S1 and S2 are closed for t
G. The outputs are measured one at a time with one input transition per measurement.
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PZL
Figure 2. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
相关型号：
©2020 ICPDF网 联系我们和版权申明