SN54LV126AJ [TI]
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS; 具有三态输出翻两番总线缓冲器GATES
| 型号： | SN54LV126AJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
SN54LV126A . . . J OR W PACKAGE
SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Typical V
< 0.8 V at V , T = 25°C
(Output Ground Bounce)
OLP
CC
A
1OE
1A
V
CC
4OE
4A
1
2
3
4
5
6
7
14
13
12
11
Typical V
> 2 V at V , T = 25°C
(Output V
Undershoot)
OHV
CC
OH
1Y
A
2OE
2A
4Y
Latch-Up Performance Exceeds 250 mA Per
JESD 17
10 3OE
2Y
9
8
3A
3Y
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
GND
SN54LV126A . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
3
2
1
20 19
18
4
5
6
7
8
1Y
NC
4A
17
16
15
14
NC
4Y
description
2OE
NC
NC
3OE
These quadruple bus buffer gates are designed
for 2-V to 5.5-V V operation.
2A
9 10 11 12 13
CC
The ’LV126A devices feature independent line
drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.
NC – No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
The SN54LV126A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV126A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
†
logic symbol
1
1
1OE
EN
3
6
1Y
2Y
3Y
4Y
2
1A
4
2OE
5
2A
10
8
3OE
9
3A
13
4OE
11
12
4A
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
1
10
9
1OE
3OE
3A
2
3
6
8
1A
1Y
2Y
3Y
4Y
4
5
13
12
2OE
2A
4OE
4A
11
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
recommended operating conditions (see Note 4)
SN54LV126A
SN74LV126A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
V
V
V
V
V
V
V
= 2 V
1.5
1.5
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
× 0.3
× 0.3
× 0.3
5.5
V
× 0.3
× 0.3
× 0.3
5.5
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
V
V
V
V
Input voltage
0
0
0
0
0
0
V
V
I
High or low state
3-state
V
V
CC
5.5
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–2
–50
–2
–8
–16
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
–8
mA
µA
–16
50
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
8
8
mA
16
16
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV126A
SN74LV126A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= –50 µA
2 V to 5.5 V
2.3 V
V
–0.1
2
V
CC
–0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= –2 mA
= –8 mA
= –16 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
±1
0.1
0.4
0.44
0.55
±1
V
OL
= 8 mA
3 V
= 16 mA
4.5 V
I
I
I
I
V = V
or GND
5.5 V
µA
µA
µA
µA
pF
I
I
CC
V
= V
or GND
5.5 V
±5
±5
OZ
CC
off
O
CC
V = V
or GND,
I
O
= 0
5.5 V
20
20
I
CC
V or V = 0 to 5.5 V
0 V
5
5
I
O
C
V = V
or GND
3.3 V
1.6
1.6
i
I
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
7.1
SN54LV126A SN74LV126A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
13
MIN
1
MAX
15.5
15.5
17
MIN
1
MAX
15.5
15.5
17
t
t
t
t
t
t
t
*
*
A
Y
Y
Y
Y
Y
Y
pd
OE
OE
A
C
C
= 15 pF
= 50 pF
7.4
13
1
1
ns
en
L
L
*
5.7
14.7
16.5
16.5
18.2
2
1
1
dis
pd
en
dis
9.2
1
18.5
18.5
20.5
1
18.5
18.5
20.5
2
OE
OE
9.5
1
1
ns
8.1
15
1
†
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
5
SN54LV126A SN74LV126A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
8
MIN
1
MAX
9.5
9.5
11.5
13
MIN
1
MAX
9.5
9.5
11.5
13
t
t
t
t
t
t
t
*
*
A
Y
Y
Y
Y
Y
Y
pd
OE
OE
A
C
C
= 15 pF
= 50 pF
5.1
8
1
1
ns
en
L
L
*
4.4
9.7
11.5
11.5
13.2
1.5
1
1
dis
pd
en
dis
6.4
1
1
OE
OE
6.6
1
13
1
13
ns
6.1
1
15
1
15
†
1.5
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
3.5
SN54LV126A SN74LV126A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
5.5
5.1
6.8
7.5
7.1
8.8
1
MIN
1
MAX
6.5
6
MIN
1
MAX
6.5
6
t
t
t
t
t
t
t
*
*
A
Y
Y
Y
Y
Y
Y
pd
OE
OE
A
C
C
= 15 pF
= 50 pF
3.6
1
1
ns
en
L
L
*
3.3
1
8
1
8
dis
pd
en
dis
4.6
1
8.5
8
1
8.5
8
OE
OE
4.6
1
1
ns
4.3
1
10
1
10
1
†
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Skew between any two outputs of the same package switching in the same direction
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV126A
UNIT
PARAMETER
MIN
TYP
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
0.32
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
–0.23
3.06
–0.8
OL
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
OH
2.31
0.97
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
V
TYP
14.4
15.9
UNIT
CC
3.3 V
5 V
C
Power dissipation capacitance
Outputs enabled
C
pF
pd
L
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
From Output
Under Test
Test
Point
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
C
C
PLH PHL
/t
L
L
t
V
CC
(see Note A)
(see Note A)
PLZ PZL
/t
GND
PHZ PZH
V
CC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
t
50% V
CC
CC
CC
t
CC
0 V
0 V
t
PZL
t
t
PLH
PHL
PLZ
Output
Waveform 1
V
OH
≈ V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
CC
V
V
OL
+ 0.3 V
– 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
PHZ
t
PHL
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
V
OH
50% V
50% V
50% V
CC
CC
≈ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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