SN54LV21A [TI]
SN54LV21A,SN74LV21A DUAL 4-INPIT POSITIVE-AND GATES; SN54LV21A ， SN74LV21A双4 INPIT正与门
| 型号： | SN54LV21A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN54LV21A,SN74LV21A DUAL 4-INPIT POSITIVE-AND GATES |
| 文件： | 总11页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢁ ꢏꢌꢐ ꢏꢑ ꢀꢎ ꢐ ꢎꢅꢒ ꢍꢈꢁꢋ ꢓ ꢈꢐꢒ ꢀ
SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004
SN54LV21A . . . J OR W PACKAGE
SN74LV21A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
2-V to 5.5-V V
Operation
CC
Max t of 6 ns at 5 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
1A
1B
V
CC
1
2
3
4
5
6
7
14
13
12
11
A
2D
2C
NC
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
NC
1C
= 3.3 V, T = 25°C
A
I
Supports Partial-Power-Down Mode
off
1D
10 2B
Operation
9
8
1Y
2A
2Y
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
GND
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LV21A . . . FK PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
3
2
1
20 19
18
2C
NC
NC
NC
NC
1C
NC
1D
4
5
6
7
8
These dual 4-input positive-AND gates are
17
16
designed for 2-V to 5.5-V V
operation.
CC
15 NC
14
9 10 11 12 13
The ’LV21A devices perform the Boolean function
2B
Y + A • B • C • D or Y + A ) B ) C ) D
positive logic.
in
These devices are fully specified for
partial-power-down applications using I . The I
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
off
off
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 50
SN74LV21AD
SOIC − D
LV21A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV21ADR
SN74LV21ANSR
SN74LV21ADBR
SN74LV21APW
SN74LV21APWR
SN74LV21APWT
SN74LV21ADGVR
SNJ54LV21AJ
SOP − NS
74LV21A
LV21A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV21A
TVSOP − DGV
CDIP − J
LV21A
SNJ54LV21AJ
SNJ54LV21AW
SNJ54LV21AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV21AW
SNJ54LV21AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
ꢌ ꢁ ꢄꢒꢀꢀ ꢑ ꢐꢔ ꢒꢕꢖ ꢎꢀ ꢒ ꢁ ꢑꢐꢒꢋ ꢗꢘ ꢙꢚ ꢛꢜꢝ ꢞꢟꢠ ꢡꢗ ꢝꢜ ꢡꢗꢢ ꢙꢡꢚ ꢏꢕ ꢑ ꢋ ꢌ ꢣꢐ ꢎꢑ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢈ
ꢋ ꢌꢈꢄ ꢃ ꢍꢎ ꢁꢏ ꢌꢐ ꢏ ꢑꢀ ꢎ ꢐꢎ ꢅ ꢒꢍ ꢈꢁꢋ ꢓ ꢈꢐꢒ ꢀ
SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
H
L
B
H
X
L
C
H
X
X
L
D
H
X
X
X
L
H
L
L
L
L
X
X
X
X
X
X
logic diagram (positive logic)
1
9
10
12
13
1A
2A
2B
2C
2D
2
1B
1C
1D
6
8
1Y
2Y
4
5
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range applied in high or low state, V (see Notes 1 and 2) . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Output voltage range applied in power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢁ ꢏꢌꢐ ꢏꢑ ꢀꢎ ꢐ ꢎꢅꢒ ꢍꢈꢁꢋ ꢓ ꢈꢐꢒ ꢀ
SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004
recommended operating conditions (see Note 4)
SN54LV21A
MIN MAX
SN74LV21A
MIN MAX
UNIT
V
V
Supply voltage
2
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
× 0.3
× 0.3
× 0.3
5.5
V
× 0.3
× 0.3
× 0.3
5.5
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
V
V
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV21A
SN74LV21A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.9
1.9
i
I
CC
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢈ
ꢋ ꢌꢈꢄ ꢃ ꢍꢎ ꢁꢏ ꢌꢐ ꢏ ꢑꢀ ꢎ ꢐꢎ ꢅ ꢒꢍ ꢈꢁꢋ ꢓ ꢈꢐꢒ ꢀ
SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
7*
SN54LV21A
SN74LV21A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
12*
MIN
1*
MAX
14*
19
MIN
1
MAX
14
t
pd
A, B, C, or D
A, B, C, or D
Y
Y
C
C
= 15 pF
= 50 pF
ns
ns
L
L
t
pd
9.2
15.7
1
1
19
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV21A
SN74LV21A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
7*
MIN
1*
MAX
8.5*
12
MIN
1
MAX
8.5
t
pd
A, B, C, or D
A, B, C, or D
Y
Y
C
C
= 15 pF
= 50 pF
5.1*
ns
ns
L
L
t
pd
6.6
10.5
1
1
12
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV21A
SN74LV21A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
5*
MIN
1*
MAX
6*
MIN
1
MAX
t
pd
A, B, C, or D
A, B, C, or D
Y
Y
C
C
= 15 pF
= 50 pF
3.8*
6
8
ns
ns
L
L
t
pd
4.9
7
1
8
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV21A
PARAMETER
UNIT
MIN
TYP
0.2
0
MAX
0.8
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.8
OL
3.2
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
17.4
20.2
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢁ ꢏꢌꢐ ꢏꢑ ꢀꢎ ꢐ ꢎꢅꢒ ꢍꢈꢁꢋ ꢓ ꢈꢐꢒ ꢀ
SCES340D − SEPTEMBER 2000 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
t
CC
CC
0 V
0 V
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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