SN54LV4040A [TI]
12-BIT ASYNCHRONOUS BINARY COUNTERS; 12位异步二进制计数器
| 型号： | SN54LV4040A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT ASYNCHRONOUS BINARY COUNTERS |
| 文件： | 总8页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
SN54LV4040A . . . J OR W PACKAGE
SN74LV4040A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
L
Q
Q
Q
Q
Typical V
>2.3 V at V
(Output V
Undershoot)
F
E
K
J
H
I
OHV
CC
OH
Q
Q
= 3.3 V, T = 25°C
A
G
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Q
D
C
Q
CLR
CLK
Q
B
Extremely Low Input Current
GND
Q
A
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
SN54LV4040A . . . FK PACKAGE
(TOP VIEW)
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
3
2
1
20 19
18
Q
Q
Q
Q
Package Options Include Plastic
4
5
6
7
8
J
E
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Ceramic (J) DIPs
17
16
15
14
H
G
NC
NC
Q
I
CLR
Q
D
Q
C
9 10 11 12 13
description
NC – No internal connection
The ’LV4040A devices are 12-bit asynchronous
binary counters with the outputs of all stages
availableexternally. A high level at the clear (CLR)
input asynchronously clears the counter and
resets all outputs low. The count is advanced on
a high-to-low transition at the clock (CLK) input.
Applications include time-delay circuits, counter
controls, and frequency-dividing circuits.
The SN54LV4040A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV4040A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
CLR
L
↑
↓
No change
Advance to next stage
All outputs L
L
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
†
logic symbol
RCTR12
9
7
6
5
Q
0
A
Q
Q
B
C
Q
Q
Q
D
E
F
11
10
3
2
CLR
CLK
CT=0
CT
4
Q
Q
Q
Q
G
H
I
13
12
14
15
1
J
Q
Q
K
L
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
11
CLR
R
R
R
R
R
10
CLK
T
T
T
T
T
9
7
6
5
3
Q
Q
Q
Q
Q
E
A
B
C
D
R
R
R
R
R
R
R
T
T
T
T
T
T
T
2
4
13
12
14
15
1
Q
Q
Q
Q
Q
Q
Q
L
F
G
H
I
J
K
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LV4040A
SN74LV4040A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
V
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–2
–50
–2
–6
–12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
–6
mA
µA
–12
50
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV4040A
SN74LV4040A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
–0.1
2
TYP
MAX
MIN
–0.1
2
TYP
MAX
I
I
I
I
I
I
I
I
= –50 µA
2 V to 5.5 V
2.3 V
3 V
V
CC
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
= –2 mA
= –6 mA
= –12 mA
= 50 µA
= 2 mA
V
V
V
OH
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
3 V
0.1
0.4
0.44
0.55
±1
0.1
0.4
0.44
0.55
±1
V
OL
= 6 mA
= 12 mA
4.5 V
5.5 V
5.5 V
0 V
I
I
I
V = V
or GND
or GND,
µA
µA
µA
I
I
CC
CC
V = V
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
5
5
I
O
3.3 V
5 V
1.9
1.8
1.9
1.8
C
V = V
I
or GND
pF
i
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V ± 0.2 V
CC
T
= 25°C
SN54LV4040A SN74LV4040A
A
UNIT
MIN
7
MAX
MIN
7
MAX
MIN
7
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
6.5
6.5
6.5
6.5
6.5
6.5
CLR inactive before CLK↓
su
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V ± 0.3 V
CC
T
= 25°C
SN54LV4040A SN74LV4040A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
5
5
5
5
5
5
CLR inactive before CLK↓
su
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54LV4040A SN74LV4040A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
5
5
5
5
5
5
CLR inactive before CLK↓
su
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
switching characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
115
95
SN54LV4040A SN74LV4040A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
50
MAX
MIN
40
35
1
MAX
MIN
40
35
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
40
L
L
L
L
t
t
t
t
t
t
*
*
*
8.7
19.4
19.4
19.9
24.1
24.1
24.5
5.9
23
23
24
28
28
28
7
23
23
24
28
28
28
7
PLH
PHL
PHL
PLH
PHL
PHL
C
C
C
= 15 pF
= 15 pF
= 50 pF
ns
ns
ns
CLK
CLR
Q
A
8.7
1
1
9.3
1
1
Any Q
10.5
10.5
11.7
1.7
1
1
CLK
CLR
Q
A
1
1
C
C
= 50 pF
= 50 pF
1
1
ns
ns
Any Q
L
L
∆t
pd
Q
n
Q
n+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
160
130
6.1
SN54LV4040A SN74LV4040A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
75
MAX
MIN
75
50
1
MAX
MIN
75
50
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
55
L
L
L
L
t
t
t
t
t
t
*
*
*
11.9
11.9
12.8
15.4
15.4
16.3
4.4
14
14
14
14
PLH
PHL
PHL
PLH
PHL
PHL
C
C
C
= 15 pF
= 15 pF
= 50 pF
ns
ns
ns
CLK
CLR
Q
A
6.1
1
1
7.1
1
15
1
15
Any Q
7.5
1
17.5
17.5
18.5
5
1
17.5
17.5
18.5
5
CLK
CLR
Q
A
7.5
1
1
C
C
= 50 pF
= 50 pF
9
1
1
ns
ns
Any Q
L
L
∆t
pd
Q
n
1.2
Q
n+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
235
185
4.2
SN54LV4040A SN74LV4040A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
150
95
MAX
MIN
125
80
1
MAX
MIN
125
80
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
L
L
L
L
t
t
t
t
t
t
*
*
*
7.3
7.3
8.5
8.5
8.5
8.5
PLH
PHL
PHL
PLH
PHL
PHL
C
C
C
= 15 pF
= 15 pF
= 50 pF
ns
ns
ns
CLK
CLR
Q
A
4.2
1
1
5.3
8.6
1
10
1
10
Any Q
5.3
9.3
1
10.5
10.5
12
1
10.5
10.5
12
CLK
CLR
Q
A
5.3
9.3
1
1
C
C
= 50 pF
= 50 pF
6.8
10.6
3.1
1
1
ns
ns
Any Q
L
L
∆t
pd
Q
n
0.8
3.5
3.5
Q
n+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV4040A
PARAMETER
UNIT
MIN
TYP
0.5
MAX
V
OL(P)
V
OL(V)
V
IH(D)
V
IL(D)
Quiet output, maximum dynamic V
0.8
V
V
V
V
OL
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.5
–0.8
OL
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
11.9
13.1
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
V
CC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
CC
V
CC
Output
Control
50% V
50% V
50% V
50% V
t
CC
CC
CC
CC
0 V
0 V
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
OL
+ 0.3 V
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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