SN54LV595AFKR [TI]
LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20;
| 型号： | SN54LV595AFKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
SN54LV595A . . . J OR W PACKAGE
SN74LV595A . . . D, DB, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
CC
A
B
Q
Typical V
> 2 V at V
(Output V
Undershoot)
C
D
A
OHV
CC
OH
Q
SER
OE
= 3.3 V, T = 25°C
A
Q
E
8-Bit Serial-In, Parallel-Out Shift
Shift Register Has Direct Clear
Q
12 RCLK
F
11
10
9
Q
SRCLK
SRCLR
G
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Q
H
GND
Q
H′
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
SN54LV595A . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Packages, Chip
Carriers (FK), and DIPs (J)
3
2
1 20 19
18
SER
OE
Q
4
5
6
7
8
D
Q
17
16
E
NC
NC
description
15 RCLK
14
9 10 11 12 13
Q
F
SRCLK
The ’LV595A devices are 8-bit shift registers
designed for 2-V to 5.5-V V operation.
Q
G
CC
These devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage register. The shift
NC – No internal connection
register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When
the output-enable (OE) input is high, all outputs except Q are in the high-impedance state.
H′
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register is always one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV595A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV595A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
†
logic symbol
13
OE
EN3
C2
12
RCLK
SRG8
10
11
R
SRCLR
SRCLK
C1/
15
1
14
Q
Q
2D
3
SER
1D
A
B
2
Q
Q
C
D
3
4
5
6
7
9
Q
Q
E
F
Q
Q
G
H
2D
3
Q
H′
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
Q
Q
1D
C1
R
3D
C3
15
Q
Q
Q
Q
A
B
2D
C2
3D
C3
1
2
3
R
2D
C2
R
3D
C3
Q
Q
Q
Q
Q
Q
C
D
2D
C2
3D
C3
R
2D
C2
R
3D
C3
Q
Q
Q
4
5
6
Q
Q
Q
Q
Q
Q
E
F
2D
C2
R
3D
C3
2D
C2
3D
C3
G
R
2D
C2
R
3D
C3
Q
7
9
Q
Q
Q
H
H′
Pin numbers shown are for the D, DB, J, NS, PW, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range applied in the high or low state, V (see Notes 1 and 2) . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Output voltage range applied in high-impedance or power-off state, V (see Note 1) . . . . . . . –0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
recommended operating conditions (see Note 4)
SN54LV595A
SN74LV595A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
0
5.5
0
0
0
5.5
V
V
I
High or low state
3-state
V
V
CC
5.5
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–2
–50
–2
–8
–16
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
–8
mA
µA
–16
50
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
8
8
mA
16
16
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV595A
SN74LV595A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
I
I
I
I
= –50 µA
2 V to 5.5 V
2.3 V
V
–0.1
2
V
CC
–0.1
2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
= –2 mA
= –6 mA
= –8 mA
= –12 mA
= –16 mA
= 50 µA
= 2 mA
Q
2.48
2.48
3.8
2.48
2.48
3.8
H′
Q –Q
V
OH
3 V
V
A
H
Q
H′
Q –Q
4.5 V
3.8
3.8
A
H
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.44
0.55
0.55
±1
0.1
0.4
0.44
0.44
0.55
0.55
±1
Q
H′
Q –Q
= 6 mA
V
OL
3 V
V
= 8 mA
A
H
Q
H′
Q –Q
= 12 mA
= 16 mA
4.5 V
A
H
I
I
I
I
V = V
or GND
5.5 V
5.5 V
5.5 V
0 V
µA
µA
µA
µA
I
I
CC
V
= V
or GND
±5
±5
OZ
CC
off
O
CC
V = V
or GND
I
O
= 0
20
20
I
CC
V or V = 0 to 5.5 V
5
5
I
O
3.3 V
5 V
3.5
3
3.5
3
C
V = V
I
or GND
pF
i
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V ± 0.2 V
CC
T
= 25°C
SN54LV595A SN74LV595A
A
UNIT
MIN
MAX
7
MIN
MAX
7.5
7.5
6.5
3
MIN
MAX
7.5
7.5
6.5
3
SRCLK high or low
RCLK high or low
SRCLR low
t
w
Pulse duration
7
ns
6
SER before SRCLK↑
SRCLK↑ before RCLK↑
2.5
8
†
9
9
t
t
ns
ns
Setup time
Hold time
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
8.5
4
9.5
4
9.5
4
1.5
1.5
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V ± 0.3 V
CC
T
= 25°C
SN54LV595A SN74LV595A
A
UNIT
MIN
MAX
5.5
5.5
5
MIN
MAX
5.5
5.5
5
MIN
MAX
5.5
5.5
5
SRCLK high or low
RCLK high or low
SRCLR low
t
w
Pulse duration
ns
SER before SRCLK↑
SRCLK↑ before RCLK↑
3.5
8
3.5
8.5
9
3.5
8.5
9
†
t
t
ns
ns
Setup time
Hold time
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
8
3
3
3
1.5
1.5
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54LV595A SN74LV595A
A
UNIT
MIN
MAX
5
MIN
MAX
5
MIN
MAX
5
SRCLK high or low
RCLK high or low
SRCLR low
t
Pulse duration
5
5
5
ns
w
5.2
3
5.2
3
5.2
3
SER before SRCLK↑
SRCLK↑ before RCLK↑
†
5
5
5
t
t
ns
ns
Setup time
Hold time
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
5
5
5
2.5
2
2.5
2
2.5
2
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
80
SN54LV595A SN74LV595A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
65
MAX
MIN
45
40
1
MAX
MIN
45
40
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
60
70
L
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
*
*
*
*
8.4
14.2
14.2
19.6
19.6
14.6
13.9
18.1
13.7
15.2
17.2
17.2
22.5
22.5
18.8
17
15.8
15.8
22.2
22.2
16.3
15
15.8
15.8
22.2
22.2
16.3
15
PLH
PHL
PLH
PHL
PHL
PZH
RCLK
Q –Q
A
H
8.4
1
1
9.4
1
1
SRCLK
SRCLR
OE
Q
Q
H′
H′
9.4
1
1
8.7
1
1
C
= 15 pF
ns
L
*
8.2
1
1
Q –Q
A
H
H
H
*
10.9
8.3
1
20.3
15.6
16.7
19.3
19.3
25.5
25.5
21.1
18.3
23
1
20.3
15.6
16.7
19.3
19.3
25.5
25.5
21.1
18.3
23
PZL
*
1
1
PHZ
OE
Q –Q
A
*
9.2
1
1
PLZ
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
11.2
11.2
13.1
13.1
12.4
10.8
13.4
12.2
14
1
1
RCLK
Q –Q
A
1
1
1
1
SRCLK
SRCLR
OE
Q
Q
H′
H′
1
1
C
= 50 pF
ns
1
1
L
1
1
Q –Q
A
H
21
1
1
18.3
20.9
1
19.5
22.6
1
19.5
22.6
OE
Q –Q
A
H
1
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
SN54LV595A SN74LV595A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80
TYP
120
105
6
MAX
MIN
70
50
1
MAX
MIN
70
50
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
55
L
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
*
*
*
*
11.9
11.9
13
13.5
13.5
15
13.5
13.5
15
PLH
PHL
PLH
PHL
PHL
PZH
RCLK
Q –Q
A
H
6
1
1
6.6
6.6
6.2
6
1
1
SRCLK
SRCLR
OE
Q
Q
H′
H′
13
1
15
1
15
12.8
11.5
11.5
14.7
14.7
15.4
15.4
16.5
16.5
16.3
15
1
13.7
13.5
13.5
15.2
15.2
17
1
13.7
13.5
13.5
15.2
15.2
17
C
= 15 pF
ns
L
*
1
1
Q –Q
A
H
H
H
*
7.8
6.1
6.3
7.9
7.9
9.2
9.2
9
1
1
PZL
*
1
1
PHZ
OE
Q –Q
A
*
1
1
PLZ
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
1
1
RCLK
Q –Q
A
1
17
1
17
1
18.5
18.5
17.2
17
1
18.5
18.5
17.2
17
SRCLK
SRCLR
OE
Q
Q
H′
H′
1
1
C
= 50 pF
ns
1
1
L
7.8
9.6
8.1
9.3
1
1
Q –Q
A
H
15
1
17
1
17
15.7
15.7
1
16.2
16.2
1
16.2
16.2
OE
Q –Q
A
H
1
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170
140
4.3
4.3
4.5
4.5
4.5
4.3
5.4
2.4
2.7
5.6
5.6
6.4
6.4
6.4
5.7
6.8
3.5
3.4
SN54LV595A SN74LV595A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
135
120
MAX
MIN
115
95
1
MAX
MIN
115
95
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
L
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
*
*
*
*
7.4
7.4
8.2
8.2
8
8.5
8.5
9.4
9.4
9.1
10
8.5
8.5
9.4
9.4
9.1
10
PLH
PHL
PLH
PHL
PHL
PZH
RCLK
Q –Q
A
H
1
1
1
1
SRCLK
SRCLR
OE
Q
Q
H′
H′
1
1
1
1
C
= 15 pF
ns
L
*
8.6
8.6
6
1
1
Q –Q
A
H
H
H
*
1
10
1
10
PZL
*
1
7.1
7.2
10.5
10.5
11.4
11.4
11.1
12
1
7.1
7.2
10.5
10.5
11.4
11.4
11.1
12
PHZ
OE
Q –Q
A
*
5.1
9.4
9.4
10.2
10.2
10
1
1
PLZ
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
1
1
RCLK
Q –Q
A
1
1
1
1
SRCLK
SRCLR
OE
Q
Q
H′
H′
1
1
C
= 50 pF
ns
1
1
L
10.6
10.6
10.3
10.3
1
1
Q –Q
A
H
1
12
1
12
1
11
1
11
OE
Q –Q
A
H
1
11
1
11
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV595A
PARAMETER
UNIT
MIN
TYP
0.2
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.2
3.2
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
32.7
33.1
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV595A, SN74LV595A
8-BIT SHIFT REGISTERS
WITH 3-STATE OUTPUT REGISTERS
SCLS414C – APRIL 1998 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
V
CC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
CC
Input
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
CC
CC
CC
t
CC
0 V
0 V
t
t
t
t
PLZ
PLH
PHL
PZL
Output
Waveform 1
V
≈ V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
≈ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PHL
PHZ
PZH
PLH
.
Figure 1. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
SN54LV595AWR
LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16, CERAMIC, FP-16
TI
©2020 ICPDF网 联系我们和版权申明