SN54LVT646JT [TI]
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 3.3 -V ABT八路总线收发器和寄存器具有三态输出型号: | SN54LVT646JT |
厂家: | TEXAS INSTRUMENTS |
描述: | 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
文件: | 总10页 (文件大小:157K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
SN54LVT646 . . . JT OR W PACKAGE
SN74LVT646 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
CLKAB
SAB
DIR
A1
V
CC
1
24
23
22
21
20
19
18
17
16
15
14
13
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CLKBA
SBA
OE
B1
2
)
CC
3
Support Unregulated Battery Operation
Down to 2.7 V
4
A2
5
A3
B2
6
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
A4
B3
7
= 3.3 V, T = 25°C
CC
A
A5
B4
8
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
A6
B5
9
A7
A8
GND
B6
B7
B8
10
11
12
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
SN54LVT646 . . . FK PACKAGE
(TOP VIEW)
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and and Thin Shrink Small-Outline
(PW) Packages, Ceramic Chip Carriers
(FK), Ceramic Flat (W) Packages, and
Ceramic (JT) DIPs
4
3
2
1
28 27 26
25
OE
B1
B2
NC
A1
A2
A3
NC
A4
A5
A6
5
24
23
22
6
7
8
21 B3
9
description
20
19
10
11
B4
B5
These bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V
12 13 14 15 16 17 18
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
NC – No internal connection
The ’LVT646 consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high
transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental
bus-management functions that can be performed with the ′LVT646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT646 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT646 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVT646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/Os
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
†
†
†
↑
X
Unspecified
Input
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
21
OE
L
3
1
23
2
22
SBA
L
21
OE
L
3
DIR
H
1
23
CLKAB CLKBA SAB
L
2
22
SBA
X
DIR CLKAB CLKBA SAB
L
X
X
X
X
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
21
3
1
23
2
22
21
OE
L
3
DIR
L
1
23
2
22
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
X
X
X
↑
X
X
H or L
X
X
H
X
H
X
X
L
H
H or L
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
Pin numbers shown are for the DB, DW, JT, PW, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
†
logic symbol
21
G3
OE
3
DIR
3 EN1 [BA]
3 EN2 [AB]
23
22
1
CLKBA
SBA
C4
G5
CLKAB
SAB
C6
2
G7
20
4D
2
B1
5
5
≥1
4
A1
1
1
6D
7
7
≥1
1
5
19
18
17
16
15
14
13
B2
B3
B4
B5
B6
B7
B8
A2
A3
A4
A5
A6
A7
A8
6
7
8
9
10
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, PW, and W packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
logic diagram (positive logic)
21
OE
3
DIR
23
CLKBA
22
SBA
1
CLKAB
2
SAB
One of Eight
Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, PW, and W packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . –0.5 V to 7 V
O
Current into any output in the low state, I : SN54LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W
A
DW package . . . . . . . . . . . . . . . . . . . 1.7 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
SN54LVT646 SN74LVT646
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
A
–55
125
–40
85
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVT646
SN74LVT646
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
‡
= MIN to MAX ,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= – 8 mA
= – 24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
CC
2.4
V
OH
V
V
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
CC
CC
Control
inputs
‡
= 0 or MAX ,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
100
1
20
µA
I
§
V
CC
= 3.6 V
V = V
I CC
A or B ports
1
V = 0
I
–5
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
= 3 V
A or B ports
I(hold)
CC
V = 2 V
I
–75
–75
I
I
V
V
= 3.6 V,
= 3.6 V,
V
= 3 V
1
–1
1
–1
µA
µA
OZH
CC
O
O
V
= 0.5 V
OZL
CC
Outputs high
Outputs low
0.13
8.8
0.39
14
0.13
8.8
0.19
12
V
= 3.6 V,
or GND
CC
I
= 0,
CC
O
I
mA
CC
V = V
I
Outputs
disabled
0.13
0.39
0.3
0.13
0.19
0.2
V
= 3 V to 3.6 V,
One input at V
or GND
– 0.6 V,
CC
CC
Other inputs at V
¶
∆I
mA
CC
CC
C
C
V = 3 V or 0
4.5
11
4.5
11
pF
pF
i
I
V
O
= 3 V or 0
io
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Unused terminals at V or GND
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVT646
= 3.3 V
SN74LVT646
= 3.3 V
V
V
CC
± 0.3 V
CC
± 0.3 V
V
CC
= 2.7 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
150
150
150
150
MHz
ns
clock
Pulse duration, CLK high or low
3.3
1.5
2.5
3.3
1.5
3.0
3.3
1.3
2
3.3
1.3
2.4
w
Data high
Data low
Setup time, A or B before CLKAB↑ or
CLKBA↑
t
ns
ns
su
h
Hold time, A or B after
CLKAB↑ or CLKBA↑
t
0.9
0.9
0.4
0.4
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 2)
SN54LVT646
= 3.3 V
SN74LVT646
= 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
V
V
CC
± 0.3 V
CC
± 0.3 V
V
CC
= 2.7 V
MAX
V
= 2.7 V
MAX
PARAMETER
UNIT
CC
†
MIN
150
1.2
1.2
0.8
0.6
1
MAX
MIN
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
150
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
5.9
5.9
4.9
4.8
6.4
6.4
6
6.9
6.6
5.6
5.5
7.4
7
1.8
2.1
1.3
1
3.8
3.8
2.8
2.7
3.7
3.8
3
5.7
5.7
4.7
4.6
6.2
6.2
5.8
6
6.7
6.4
5.4
5.3
7.2
6.8
7.2
7.3
6.9
5.9
7.5
7.1
8.1
6.3
CLKBA or
CLKAB
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
1.4
1.4
1
‡
SBA or SAB
1
0.6
0.6
1.4
1.4
0.6
0.8
0.8
1
7.4
7.5
7.1
6.5
7.7
7.3
8.3
7
OE
OE
6.2
6.7
6.4
6.7
6.5
7.4
6.7
1
3.2
4.3
3.8
3.4
3.4
4.1
3.5
2.3
2.2
1
6.5
5.8
6.5
6.3
7.2
5.8
DIR
DIR
1.2
1.7
1.5
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT646, SN74LVT646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS140D – MAY 1992 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
t
/t
Open
6 V
500 Ω
Open
GND
PLH PHL
From Output
Under Test
t
/t
PLZ PZL
t
/t
PHZ PZH
GND
C
= 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
t
1.5 V
1.5 V
Input
t
PZL
t
t
PHL
PLH
PLZ
1.5 V
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
(see Note B)
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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