SN54LVTH162374-SP [TI]
具有三态输出的 3.3V ABT 16 位边沿 D 类触发器;型号: | SN54LVTH162374-SP |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有三态输出的 3.3V ABT 16 位边沿 D 类触发器 驱动 触发器 总线驱动器 总线收发器 |
文件: | 总13页 (文件大小:339K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉ ꢊ ꢋ ꢌ ꢃ ꢍ ꢀꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌꢃ
ꢎꢋ ꢏꢅ ꢐꢑꢆ ꢈ ꢉ ꢏꢑꢒ ꢆ ꢓꢔꢕ ꢓ ꢏꢆꢖ ꢒꢕ ꢕꢓ ꢖꢓꢔ ꢔꢏꢆ ꢗꢘ ꢓ ꢙ ꢄꢒ ꢘ ꢏꢙ ꢄꢚ ꢘꢀ
ꢛ ꢒꢆ ꢇ ꢋ ꢏꢀꢆꢐꢆ ꢓ ꢚ ꢜꢆ ꢘ ꢜꢆꢀ
ꢋ
SCBS262K − JULY 1993 − REVISED SEPTEMBER 2003
SN54LVTH162374 . . . WD PACKAGE
SN74LVTH162374 . . . DGG OR DL PACKAGE
(TOP VIEW)
D
D
Members of the Texas Instruments
Widebus Family
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
1CLK
1D1
1D2
GND
1D3
1D4
2
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3
4
3.3-V V
)
5
CC
6
D
D
D
D
Support Unregulated Battery Operation
Down to 2.7 V
7
V
V
CC
CC
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
9
= 3.3 V, T = 25°C
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
D
D
D
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
Flow-Through Architecture Optimizes PCB
Layout
V
V
CC
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2CLK
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering information
The ’LVTH162374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for
low-voltage (3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system
CC
environment. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVTH162374DL
SN74LVTH162374DLR
SN74LVTH162374DGGR
SN74LVTH162374KR
74LVTH162374ZQLR
SNJ54LVTH162374WD
SSOP − DL
LVTH162374
Tape and reel
Tape and reel
TSSOP − DGG
VFBGA − GQL
LVTH162374
−40°C to 85°C
−55°C to 125°C
Tape and reel
Tube
LL2374
VFBGA − ZQL (Pb-free)
CFP − WD
SNJ54LVTH162374WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢃ ꢍ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ ꢋ ꢌ ꢃ
ꢋꢎ ꢋꢏꢅ ꢐ ꢑ ꢆ ꢈ ꢉꢏ ꢑꢒ ꢆ ꢓ ꢔꢕ ꢓꢏꢆ ꢖꢒ ꢕꢕ ꢓꢖ ꢓꢔ ꢔ ꢏꢆꢗ ꢘꢓ ꢙ ꢄꢒ ꢘꢏꢙ ꢄ ꢚ ꢘꢀ
ꢛꢒ ꢆ ꢇ ꢋ ꢏꢀꢆꢐꢆ ꢓ ꢚꢜꢆ ꢘ ꢜꢆꢀ
SCBS262K − JULY 1993 − REVISED SEPTEMBER 2003
description/ordering information (continued)
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1CLK
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2CLK
A
B
C
D
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
V
CC
V
CC
GND
GND
E
F
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC − No internal connection
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
2
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ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉ ꢊ ꢋ ꢌ ꢃ ꢍ ꢀꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌꢃ
ꢋ ꢎꢋ ꢏꢅ ꢐꢑꢆ ꢈ ꢉ ꢏꢑꢒ ꢆ ꢓꢔꢕ ꢓ ꢏꢆꢖ ꢒꢕ ꢕꢓ ꢖꢓꢔ ꢔꢏꢆ ꢗꢘ ꢓ ꢙ ꢄꢒ ꢘ ꢏꢙ ꢄꢚ ꢘꢀ
ꢛ ꢒꢆ ꢇ ꢋ ꢏꢀꢆꢐꢆ ꢓ ꢚ ꢜꢆ ꢘꢜ ꢆꢀ
SCBS262K − JULY 1993 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1
24
2OE
1OE
25
36
48
2CLK
2D1
1CLK
C1
1D
C1
2
13
2Q1
1Q1
47
1D1
1D
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG, DL, and WD packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVTH162374 SN74LVTH162374
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
−12
12
0.8
5.5
−12
12
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢃ ꢍ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ ꢋ ꢌ ꢃ
ꢋꢎ ꢋꢏꢅ ꢐ ꢑ ꢆ ꢈ ꢉꢏ ꢑꢒ ꢆ ꢓ ꢔꢕ ꢓꢏꢆ ꢖꢒ ꢕꢕ ꢓꢖ ꢓꢔ ꢔ ꢏꢆꢗ ꢘꢓ ꢙ ꢄꢒ ꢘꢏꢙ ꢄ ꢚ ꢘꢀ
ꢛꢒ ꢆ ꢇ ꢋ ꢏꢀꢆꢐꢆ ꢓ ꢚꢜꢆ ꢘ ꢜꢆꢀ
SCBS262K − JULY 1993 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH162374
SN74LVTH162374
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
V
V
= 2.7 V,
= 3 V,
−1.2
−1.2
V
V
V
IK
CC
CC
CC
CC
CC
I
I
I
= −12 mA
= 12 mA
2
2
OH
OL
OH
= 3 V,
0.8
10
1
0.8
10
1
OL
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
Control inputs
Data inputs
V = V
or GND
I
CC
I
I
I
µA
µA
µA
I
V = V
1
1
I
CC
V
= 3.6 V
= 0,
CC
CC
V = 0
I
−5
−5
100
V
V or V = 0 to 4.5 V
off
I
O
V = 0.8 V
I
75
75
V
V
= 3 V
CC
V = 2 V
I
−75
−75
Data inputs
I(hold)
500
−750
‡
= 3.6 V ,
V = 0 to 3.6 V
I
CC
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
−5
−5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
100*
100*
100
100
µA
µA
I
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
= 3.6 V, I = 0,
O
CC
V = V
I
mA
mA
CC
or GND
CC
I
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
∆I
CC
or GND
CC
C
C
V = 3 V or 0
3
9
3
9
pF
pF
i
I
V
O
= 3 V or 0
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
‡
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH162374
= 3.3 V
SN74LVTH162374
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
0.3 V
0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
160
160
160
160
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
3
2.8
1.2
3.3
3.2
0.5
3
1.8
0.8
3
2
w
High or low
High or low
ns
su
h
0.1
ns
4
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ꢋ ꢎꢋ ꢏꢅ ꢐꢑꢆ ꢈ ꢉ ꢏꢑꢒ ꢆ ꢓꢔꢕ ꢓ ꢏꢆꢖ ꢒꢕ ꢕꢓ ꢖꢓꢔ ꢔꢏꢆ ꢗꢘ ꢓ ꢙ ꢄꢒ ꢘ ꢏꢙ ꢄꢚ ꢘꢀ
ꢛ ꢒꢆ ꢇ ꢋ ꢏꢀꢆꢐꢆ ꢓ ꢚ ꢜꢆ ꢘꢜ ꢆꢀ
SCBS262K − JULY 1993 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVTH162374
= 3.3 V
SN74LVTH162374
V
V
= 3.3 V
V
FROM
(INPUT)
TO
(OUTPUT)
CC
CC
V
CC
= 2.7 V
= 2.7 V
MAX
PARAMETER
UNIT
CC
0.3 V
0.3 V
†
MIN
160
1.4
1.4
1
MAX
MIN
MAX
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
160
160
160
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
6.6
5.8
6.6
6
7.4
6
2
2.2
1.8
1.8
2.4
2
3.4
3.3
3.5
3.5
4.2
3.8
5.3
4.9
5.6
4.9
5.4
5
6.2
5.1
6.9
6
CLK
OE
Q
Q
Q
7.4
6.8
7.4
6
ns
1.4
1
6.6
6
5.7
5.1
ns
ns
OE
1.4
0.5
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢃ ꢍ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ ꢋ ꢌ ꢃ
ꢋꢎ ꢋꢏꢅ ꢐ ꢑ ꢆ ꢈ ꢉꢏ ꢑꢒ ꢆ ꢓ ꢔꢕ ꢓꢏꢆ ꢖꢒ ꢕꢕ ꢓꢖ ꢓꢔ ꢔ ꢏꢆꢗ ꢘꢓ ꢙ ꢄꢒ ꢘꢏꢙ ꢄ ꢚ ꢘꢀ
ꢛꢒ ꢆ ꢇ ꢋ ꢏꢀꢆꢐꢆ ꢓ ꢚꢜꢆ ꢘ ꢜꢆꢀ
SCBS262K − JULY 1993 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
S1
Open
GND
500 Ω
TEST
/t
S1
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
GND
(see Note A)
PHZ PZH
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
Output
1.5 V
1.5 V
1.5 V
1.5 V
t
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9854201QXA
5962-9854201VXA
74LVTH162374ZQLR
ACTIVE
ACTIVE
ACTIVE
CFP
WD
48
48
56
1
1
None
None
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-1-260C-UNLIM
CFP
WD
VFBGA
ZQL
1000
Pb-Free
(RoHS)
SNAGCU
SN74LVTH162374DGGR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74LVTH162374DL
SN74LVTH162374DLR
SN74LVTH162374KR
SNJ54LVTH162374WD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
VFBGA
CFP
DL
DL
48
48
56
48
25
1000
1000
1
None
None
None
None
CU NIPDAU Level-1-235C-UNLIM
CU NIPDAU Level-1-235C-UNLIM
GQL
WD
SNPB
Call TI
Level-1-240C-UNLIM
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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