SN54LVTH162541_08 [TI]
3.3-V ABT 16-BIT BUFFERS/DRIVERS;
| 型号： | SN54LVTH162541_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUFFERS/DRIVERS 驱动 |
| 文件： | 总7页 (文件大小：106K) |
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SN54LVTH162541, SN74LVTH162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS690E – MAY 1997 – REVISED APRIL 1999
SN54LVTH162541 . . . WD PACKAGE
SN74LVTH162541 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1OE1
1Y1
1OE2
1A1
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
1Y2
1A2
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
GND
1Y3
GND
1A3
1Y4
1A4
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
V
V
CC
CC
1Y5
1Y6
1A5
1A6
3.3-V V
)
CC
GND 10
1Y7 11
39 GND
38 1A7
Support Unregulated Battery Operation
Down to 2.7 V
1Y8
1A8
12
37
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
2Y1 13
2Y2 14
GND 15
2Y3 16
2Y4 17
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
= 3.3 V, T = 25°C
CC
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
18
31
V
CC
CC
2Y5 19
2Y6 20
GND 21
2Y7 22
2Y8 23
2OE1 24
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE2
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) V
capability to provide a TTL interface to a 5-V system environment.
operation, but with the
CC
These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable
signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit
buffer section are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162541, SN74LVTH162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS690E – MAY 1997 – REVISED APRIL 1999
description (continued)
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
TheSN54LVTH162541ischaracterizedforoperationoverthefullmilitarytemperaturerangeof–55°Cto125°C.
The SN74LVTH162541 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
Y
OE2
L
A
L
OE1
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162541, SN74LVTH162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS690E – MAY 1997 – REVISED APRIL 1999
†
logic symbol
1
&
&
1OE1
1OE2
EN1
EN2
48
24
25
2OE1
2OE2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
1
1
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1Y1
3
1Y2
5
1Y3
6
1Y4
8
1Y5
9
1Y6
11
1Y7
12
1Y8
13
1
2
2Y1
14
2Y2
16
2Y3
17
2Y4
19
2Y5
20
2Y6
22
2Y7
23
2Y8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
25
1
1OE1
2OE1
2OE2
48
1OE2
47
2
36
13
1A1
1Y1
2Y1
2A1
To Seven Other Channels
To Seven Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162541, SN74LVTH162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS690E – MAY 1997 – REVISED APRIL 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH162541 SN74LVTH162541
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–12
12
0.8
5.5
–12
12
V
IL
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
I
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162541, SN74LVTH162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS690E – MAY 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH162541
SN74LVTH162541
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
V
V
= 2.7 V,
= 3 V,
–1.2
–1.2
V
V
V
IK
CC
CC
CC
CC
CC
I
I
I
= –12 mA
= 12 mA
2
2
OH
OL
OH
OL
= 3 V,
0.8
10
±1
1
0.8
10
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
Control inputs
V = V
or GND
±1
I
CC
CC
I
I
I
µA
µA
µA
I
V = V
1
I
V
CC
V
CC
V
CC
= 3.6 V
= 0,
Data inputs
V = 0
I
–5
–5
V or V = 0 to 4.5 V
±100
off
I
O
V = 0.8 V
I
75
75
= 3 V
V = 2 V
I
–75
–75
Data inputs
I(hold)
500
–750
‡
V
CC
= 3.6 V ,
V = 0 to 3.6 V
I
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
–5
–5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
±100*
±100*
±100
±100
µA
µA
I
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
4
9
4
9
pF
pF
i
I
V
O
= 3 V or 0
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVTH162541
= 3.3 V
SN74LVTH162541
FROM
(INPUT)
TO
(OUTPUT)
V
V
= 3.3 V
V
CC
CC
V
CC
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
MIN
± 0.3 V
± 0.3 V
†
MIN
1.1
1.1
1.4
1.4
2.1
2.1
MAX
4.3
4.3
5.3
5.1
6.1
5.7
MIN
MAX
4.9
4.9
6.3
5.8
6.4
5.9
MIN TYP
MAX
4.1
4.1
5
MAX
4.7
4.7
6.1
5.5
6.2
5.5
0.5
t
t
t
t
t
t
t
1.2
1.2
1.5
1.5
2.2
2.2
2.9
2.4
3.2
3.3
4.3
4
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
ns
ns
OE
OE
4.8
5.9
5.4
0.5
ns
ns
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162541, SN74LVTH162541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS690E – MAY 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
pd
/t
t
PLZ PZL
/t
C
= 50 pF
L
t
GND
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
Output
Output
1.5 V
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
– 0.3 V
OH
1.5 V
1.5 V
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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