SN54LVTH18504A_12 [TI]
3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS;
| 型号： | SN54LVTH18504A_12 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS |
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SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
Members of the Texas Instruments
SCOPE Family of Testability Products
Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
Members of the Texas Instruments
Widebus Family
SCOPE Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V V
)
CC
Support Unregulated Battery Operation
Down to 2.7 V
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in 64-Pin Plastic Thin Quad Flat
(PM) Packages Using 0.5-mm
Center-to-Center Spacings and 68-Pin
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacings
B-Port Outputs of ’LVTH182504A Devices
Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required
description
The ’LVTH18504A and ’LVTH182504A scan test devices with 20-bit universal bus transceivers are members
of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports
IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) V
capability to provide a TTL interface to a 5-V system environment.
operation, but with the
CC
In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the
TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the
boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the
SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while
CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and
CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs
are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to
A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.
Inthetestmode, thenormaloperationoftheSCOPEuniversalbustransceiversisinhibited, andthetestcircuitry
is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs
boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
description (continued)
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
TheB-portoutputsof’LVTH182504A, whicharedesignedtosourceorsinkupto12mA, includeequivalent25-Ω
series resistors to reduce overshoot and undershoot.
The SN54LVTH18504A and SN54LVTH182504A are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74LVTH18504A and SN74LVTH182504A are characterized for
operation from –40°C to 85°C.
SN54LVTH18504A, SN54LVTH182504A . . . HV PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A4
A5
A6
GND
A7
A8
A9
A10
NC
B5
B6
B7
GND
B8
B9
B10
V
CC
NC
V
B11
B12
B13
B14
GND
B15
B16
B17
CC
A11
A12
A13
GND
A14
A15
A16
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
SN74LVTH18504A, SN74LVTH182504A . . . PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
A4
A5
A6
GND
A7
A8
B5
B6
B7
GND
B8
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
6
B9
B10
A9
A10
7
8
V
CC
9
V
B11
B12
B13
B14
GND
B15
B16
B17
CC
10
11
12
13
14
15
16
A11
A12
A13
GND
A14
A15
A16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
†
FUNCTION TABLE
(normal mode, each register)
INPUTS
OUTPUT
B
OEAB
LEAB CLKENAB CLKAB
A
‡
L
L
L
L
L
L
H
L
L
L
L
L
↑
X
L
B
0
L
L
L
↑
H
X
L
H
‡
L
H
X
X
X
X
X
X
X
B
0
L
H
H
X
H
X
H
Z
†
‡
A-to-B data flow is shown. B-to-A data flow is similar, but uses
OEBA, LEBA, CLKENBA, and CLKBA.
Output level before the indicated steady-state input conditions were
established
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
functional block diagram
Boundary-Scan Register
22
CLKENAB
27
LEAB
23
CLKAB
V
CC
28
OEAB
54
59
CLKENBA
LEBA
55
CLKBA
OEBA
V
CC
60
C1
1D
C1
1D
62
53
A1
B1
C1
C1
1D
1D
1 of 20 Channels
Bypass Register
Boundary-Control
Register
Identification
Register
V
58
CC
TDO
Instruction
Register
24
TDI
TMS
TCK
V
CC
56
TAP
Controller
26
Pin numbers shown are for the PM package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
Terminal Functions
TERMINAL NAME
A1–A20
DESCRIPTION
Normal-function A-bus I/O ports. See function table for normal-mode logic.
Normal-function B-bus I/O ports. See function table for normal-mode logic.
Normal-function clock inputs. See function table for normal-mode logic.
B1–B20
CLKAB, CLKBA
CLKENAB, CLKENBA
GND
Normal-function clock enables. See function table for normal-mode logic.
Ground
LEAB, LEBA
Normal-function latch enables. See function table for normal-mode logic.
Normal-functionoutput enables. See function table for normal-mode logic. An internal pullup at each terminal forces
the terminal to a high level if left unconnected.
OEAB, OEBA
TCK
Test clock. One of four terminals required by IEEE Std 1149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
Test data input. One of four terminals required by IEEE Std 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left
unconnected.
TDI
Test data output. One of four terminals required by IEEE Std 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
TDO
TMS
Test mode select. One of four terminals required by IEEE Std 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.
V
CC
Supply voltage
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
test architecture
Serial-testinformationisconveyedbymeansofa4-wiretestbusorTAPthatconformstoIEEEStd1149.1-1990.
Test instructions, test data, and test control signals are passed along this serial-test bus. The TAP controller
monitors two signals from the test bus: TCK and TMS. The TAP controller extracts the synchronization (TCK)
and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the
test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Std 1149.1-1990 4-wire test bus and boundary-scan architecture
and the relationships of the test bus, the TAP controller, and the test registers. As shown, the device contains
an 8-bit instruction register and four test data registers: a 48-bit boundary-scan register, a 3-bitboundary-control
register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
TMS = L
TMS = H
TMS = H
TMS = H
TMS = H
Run-Test/Idle
Select-DR-Scan
TMS = L
Select-IR-Scan
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
TMS = L
Capture-IR
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
Exit1-IR
TMS = H
Exit1-DR
TMS = L
TMS = L
Pause-DR
TMS = H
Pause-IR
TMS = H
Exit2-IR
TMS = L
TMS = L
TMS = L
TMS = L
Exit2-DR
TMS = H
TMS = H
Update-DR
Update-IR
TMS = H
TMS = L
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
state diagram description
The TAP controller is a synchronous finite-state machine that provides test control signals throughout the
device. The state diagram shown in Figure 1 is in accordance with IEEE Std 1149.1-1990. The TAP controller
proceeds through its states, based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is defined as a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register at a time can be accessed.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’LVTH18504A and ’LVTH182504A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–46 in the boundary-scan register are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked,
the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should
be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the
PSA test operation.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO. On the first
falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level
present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle, in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such updates occur
on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’LVTH18504A and
’LVTH182504A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On
the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to the
logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
register overview
With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
itsnormallogicfunction, ortestmode, inwhichthenormallogicfunctionisinhibitedoraltered), thetestoperation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’LVTH18504A and ’LVTH182504A. The even-parity feature
specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any
instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The instruction register order of scan is shown
in Figure 2.
Bit 7
Parity
(MSB)
Bit 0
(LSB)
TDI
TDO
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Figure 2. Instruction Register Order of Scan
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
data register description
boundary-scan register
The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and
output data). The BSR is used to store test data that is to be applied externally to the device output pins, and/or
to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device
input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, BSCs 47–46 are reset to logic 1, ensuring that these cells, which control A-port and B-port
outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state).
Reset values of other BSCs should be considered indeterminate.
The BSR order of scan is from TDI through bits 47–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
47
46
45
44
43
42
41
40
––
––
––
––
––
––
––
––
––
––
OEAB
OEBA
CLKAB
CLKBA
CLKENAB
CLKENBA
LEAB
LEBA
––
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A20-I/O
A19-I/O
A18-I/O
A17-I/O
A16-I/O
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A9-I/O
19
18
17
16
15
14
13
12
11
10
9
B20-I/O
B19-I/O
B18-I/O
B17-I/O
B16-I/O
B15-I/O
B14-I/O
B13-I/O
B12-I/O
B11-I/O
B10-I/O
B9-I/O
––
––
––
8
––
A8-I/O
7
B8-I/O
––
A7-I/O
6
B7-I/O
––
A6-I/O
5
B6-I/O
––
A5-I/O
4
B5-I/O
––
A4-I/O
3
B4-I/O
––
A3-I/O
2
B3-I/O
––
––
––
––
21
20
A2-I/O
A1-I/O
1
0
B2-I/O
B1-I/O
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
boundary-control register
The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run
(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set.
Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that
are decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 010, which selects the PSA test operation. The boundary-control register order of scan
is shown in Figure 3.
Bit 2
(MSB)
Bit 0
(LSB)
TDI
TDO
Bit 1
Figure 3. Boundary-Control Register Order of Scan
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.
TDI
TDO
Bit 0
Figure 4. Bypass Register Order of Scan
11
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3.3-V ABT SCAN TEST DEVICES
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SCBS667B – JULY 1996 – REVISED JUNE 1997
device-identification register
The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,
part number, and version of this device.
For the ’LVTH18504A, either of the binary values 00100000000000011101000000101111 (2001D02F, hex) or
00110000000000011101000000101111 (3001D02F, hex) is captured (during Capture-DR state) in the IDR to
identify this device as TI SN54/74LVTH18504A.
For the ’LVTH182504A, either of the binary values 00010000000000100010000000101111 (1002202F, hex)
or 00100000000000100010000000101111 (2002202F, hex) is captured (during Capture-DR state) in the IDR
to identify this device as TI SN54/74LVTH182504A.
The IDR order of scan is from TDI through bits 31–0 to TDO. Table 2 shows the IDR bits and their significance.
Table 2. Device-Identification Register Configuration
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
†
†
†
†
†
†
†
†
†
†
†
†
31
30
29
28
––
––
––
––
––
––
––
––
––
––
––
––
VERSION3
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
PARTNUMBER15
PARTNUMBER14
PARTNUMBER13
PARTNUMBER12
PARTNUMBER11
PARTNUMBER10
PARTNUMBER09
PARTNUMBER08
PARTNUMBER07
PARTNUMBER06
PARTNUMBER05
PARTNUMBER04
PARTNUMBER03
PARTNUMBER02
PARTNUMBER01
PARTNUMBER00
11
10
9
MANUFACTURER10
MANUFACTURER09
MANUFACTURER08
MANUFACTURER07
MANUFACTURER06
MANUFACTURER05
MANUFACTURER04
MANUFACTURER03
MANUFACTURER02
MANUFACTURER01
MANUFACTURER00
VERSION2
VERSION1
VERSION0
8
––
––
––
––
––
––
––
––
––
––
––
––
7
6
5
4
3
2
1
†
0
LOGIC1
––
––
––
––
––
––
––
––
†
Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111
(02F, hex).
12
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3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of
each instruction.
Table 3. Instruction-Register Opcodes
†
BINARY CODE
BIT 7 → BIT 0
MSB → LSB
SELECTED
DATA REGISTER
SCOPE OPCODE
DESCRIPTION
MODE
00000000
10000001
10000010
00000011
10000100
00000101
00000110
10000111
10001000
00001001
00001010
10001011
00001100
10001101
10001110
00001111
All others
EXTEST
IDCODE
Boundary scan
Identification read
Boundary scan
Device identification
Boundary scan
Bypass
Test
Normal
Normal
Normal
Normal
Normal
Modified test
Test
SAMPLE/PRELOAD
Sample boundary
‡
‡
‡
BYPASS
BYPASS
BYPASS
HIGHZ
Bypass scan
Bypass scan
Bypass
Bypass scan
Bypass
Control boundary to high impedance
Control boundary to 1/0
Bypass scan
Bypass
CLAMP
Bypass
‡
BYPASS
Bypass
Normal
Test
RUNT
Boundary-run test
Bypass
READBN
READBT
CELLTST
TOPHIP
SCANCN
SCANCT
BYPASS
Boundary read
Boundary scan
Boundary scan
Boundary scan
Bypass
Normal
Test
Boundary read
Boundary self test
Boundary toggle outputs
Boundary-control-register scan
Boundary-control-register scan
Bypass scan
Normal
Test
Boundary control
Boundary control
Bypass
Normal
Test
Normal
†
‡
Bit 7 is used to maintain even parity in the 8-bit instruction.
The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’LVTH18504A or ’LVTH182504A.
boundary scan
This instruction conforms to the IEEE Std 1149.1-1990 EXTEST instruction. The BSR is selected in the scan
path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has been
scannedintotheI/OBSCsforpinsintheoutputmodeisappliedtothedeviceI/Opins. Datapresentatthedevice
pins, except for output-enables, is passed through the BSCs to the normal on-chip logic. For I/O pins, the
operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47–46 of the
BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode.
Otherwise, the I/O pins operate in the input mode. The device operates in the test mode.
identification read
This instruction conforms to the IEEE Std 1149.1-1990 IDCODE instruction. The IDR is selected in the scan
path. The device operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Std 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected
in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured in the
associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs
associated with I/O pins in the output mode. The device operates in the normal mode.
13
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3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
bypass scan
This instruction conforms to the IEEE Std 1149.1-1990 BYPASS instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the
normal mode.
control boundary to high impedance
This instruction conforms to the IEEE Std 1149.1a-1993 HIGHZ instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a
modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins
remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Std 1149.1a-1993 CLAMP instruction. The bypass register is selected in
the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O BSCs for
pins in the output mode is applied to the device I/O pins. The device operates in the test mode.
boundary-run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift register and
shadow latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising
edge of TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device
I/O pins on each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data
appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the
test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to
be executed.
14
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3.3-V ABT SCAN TEST DEVICES
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SCBS667B – JULY 1996 – REVISED JUNE 1997
boundary-control-register opcode description
TheBCRopcodesaredecodedfromBCRbits2–0asshowninTable4. Theselectedtestoperationisperformed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2 → BIT 0
MSB → LSB
DESCRIPTION
X00
X01
X10
011
111
Sample inputs/toggle outputs (TOPSIP)
Pseudo-random pattern generation/40-bit mode (PRPG)
Parallel-signature analysis/40-bit mode (PSA)
Simultaneous PSA and PRPG/20-bit mode (PSA/PRPG)
Simultaneous PSA and binary count up/20-bit mode (PSA/COUNT)
While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
theoutput-enableBSCs(bits47–46oftheBSR)controlthedrivestate(activeorhighimpedance)oftheselected
device output pins. These BCR instructions are only valid when the device is operating in one direction of data
flow (that is, OEAB ≠ OEBA). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
15
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SCBS667B – JULY 1996 – REVISED JUNE 1997
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 5 and 6 show the 40-bit linear-feedback shift-register algorithms through which the
patterns are generated. An initial seed value should be scanned into the BSR before performing this operation.
A seed value of all zeroes does not produce additional patterns.
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
=
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
Figure 5. 40-Bit PRPG Configuration (OEAB = 0, OEBA = 1)
16
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SCBS667B – JULY 1996 – REVISED JUNE 1997
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
=
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
Figure 6. 40-Bit PRPG Configuration (OEAB = 1, OEBA = 0)
17
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SCBS667B – JULY 1996 – REVISED JUNE 1997
parallel-signature analysis (PSA)
Data appearing at the selected device input-mode I/O pins is compressed into a 40-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the
selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8
show the 40-bit linear-feedback shift-register algorithms through which the signature is generated. An initial
seed value should be scanned into the BSR before performing this operation.
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
=
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
=
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
Figure 7. 40-Bit PSA Configuration (OEAB = 0, OEBA = 1)
18
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SCBS667B – JULY 1996 – REVISED JUNE 1997
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
=
=
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
Figure 8. 40-Bit PSA Configuration (OEAB = 1, OEBA = 0)
19
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SCBS667B – JULY 1996 – REVISED JUNE 1997
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the
shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, a 20-bit
pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on each
rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling
edge of TCK. Figures 9 and 10 show the 20-bit linear-feedback shift-register algorithms through which the
signature and patterns are generated. An initial seed value should be scanned into the BSR before performing
this operation. A seed value of all zeroes does not produce additional patterns.
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
=
=
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
Figure 9. 20-Bit PSA/PRPG Configuration (OEAB = 0, OEBA = 1)
20
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SCBS667B – JULY 1996 – REVISED JUNE 1997
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
=
=
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
Figure 10. 20-Bit PSA/PRPG Configuration (OEAB = 1, OEBA = 0)
21
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SCBS667B – JULY 1996 – REVISED JUNE 1997
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input-mode I/O pins is compressed into a 20-bit parallel signature in the
shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, a 20-bit
binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on each
rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling
edge of TCK. Figures 11 and 12 show the 20-bit linear-feedback shift-register algorithms through which the
signature is generated. An initial seed value should be scanned into the BSR before performing this operation.
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
MSB
B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
LSB
=
=
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
Figure 11. 20-Bit PSA/COUNT Configuration (OEAB = 0, OEBA = 1)
22
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B20-I/O B19-I/O B18-I/O B17-I/O B16-I/O B15-I/O B14-I/O B13-I/O B12-I/O B11-I/O
B10-I/O
B9-I/O
B8-I/O
B7-I/O
B6-I/O
B5-I/O
B4-I/O
B3-I/O
B2-I/O
B1-I/O
MSB
A20-I/O A19-I/O A18-I/O A17-I/O A16-I/O A15-I/O A14-I/O A13-I/O A12-I/O A11-I/O
LSB
=
=
A10-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
A1-I/O
Figure 12. 20-Bit PSA/COUNT Configuration (OEAB = 1, OEBA = 0)
23
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SCBS667B – JULY 1996 – REVISED JUNE 1997
timing description
Alltest operations of the ’LVTH18504A and ’LVTH182504A are synchronous to the TCK signal. Data on the TDI,
TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and
normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as
shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge
to TCK.
A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states to perform one instruction-register scan and one
data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used
to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details the
operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
1
Test-Logic-Reset
2
3
4
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
5
6
Capture-IR
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is seriallyscannedintotheIR.Atthesametime,the8-bitbinaryvalue10000001isseriallyscanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the instruction register scan
on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR
to Exit1-IR.
7–13
Shift-IR
14
15
16
Exit1-IR
Update-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
Select-DR-Scan
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
17
18
Capture-DR
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19–20
21
Shift-DR
Exit1-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
Select-IR-Scan
Test-Logic-Reset
24
25
Test operation completed.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TCK
TMS
TDI
TDO
TAP
Controller
State
3-State (TDO) or Don’t Care (TDI)
Figure 13. Timing Example
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V (see Note 1) . . . . . . . . . –0.5 V to 7 V
O
Current into any output in the low state, I : SN54LVTH18504A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN54LVTH182504A (A port or TDO) . . . . . . . . . . . . . . . . 96 mA
SN54LVTH182504A (B port) . . . . . . . . . . . . . . . . . . . . . . . 30 mA
SN74LVTH18504A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
SN74LVTH182504A (A port or TDO) . . . . . . . . . . . . . . . 128 mA
SN74LVTH182504A (B port) . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Current into any output in the high state, I (see Note 2): SN54LVTH18504A . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN54LVTH182504A (A port or TDO) . . . . 48 mA
SN54LVTH182504A (B port) . . . . . . . . . . . 30 mA
SN74LVTH18504A . . . . . . . . . . . . . . . . . . . . 64 mA
SN74LVTH182504A (A port or TDO) . . . . 64 mA
SN74LVTH182504A (B port) . . . . . . . . . . . 30 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
recommended operating conditions
SN54LVTH18504A SN74LVTH18504A
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
24
0.8
5.5
–32
32
V
IL
V
I
I
I
I
High-level output current
Low-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
mA
ns/V
°C
OH
OL
†
48
64
OL
∆t/∆v
Outputs enabled
10
10
T
A
–55
125
–40
85
†
Current duty cycle ≤ 50%, f ≥ 1 kHz
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH18504A
SN74LVTH18504A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
‡
= MIN to MAX ,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –3 mA
= –8 mA
= –24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
2.4
2.4
2
V
CC
–0.2
2.4
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
OH
2.4
V
V
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
CLK,
CLKEN,
LE, TCK
V
V
= 3.6 V,
V = V
or GND
±1
±1
CC
I
CC
‡
= 0 or MAX ,
V = 5.5 V
I
10
10
CC
V = 5.5 V
5
1
5
1
I
OE, TDI,
TMS
V
= 3.6 V
= 3.6 V
V = V
I CC
I
I
CC
CC
µA
V = 0
I
–25
–100
20
–25
–100
20
V = 5.5 V
I
A or B
V
V = V
I
1
1
CC
§
ports
V = 0
I
–5
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
500
–500
1
µA
µA
off
CC
I
O
V = 0.8 V
I
75
500
–500
1
75
150
A or B
ports
¶
= 3 V
CC
I(hold)
V = 2 V
I
–75
–75
–150
I
I
I
I
TDO
TDO
TDO
TDO
V
CC
V
CC
V
CC
V
CC
= 3.6 V,
V
O
V
O
V
O
V
O
= 3 V
µA
µA
µA
µA
OZH
= 3.6 V,
= 0.5 V
–1
–1
OZL
= 0 to 1.5 V,
= 1.5 V to 0,
= 0.5 V or 3 V
= 0.5 V or 3 V
±50
±50
2
±50
±50
2
OZPU
OZPD
Outputs high
Outputs low
0.6
19.5
0.6
0.6
19.5
0.6
V
I
= 3.6 V,
= 0,
CC
O
I
27
27
mA
CC
V = V
I
or GND
CC
Outputs disabled
2
2
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
#
0.5
0.5
mA
∆I
CC
or GND
CC
C
C
C
V = 3 V or 0
4
10
8
4
10
8
pF
pF
pF
i
I
V
= 3 V or 0
= 3 V or 0
io
o
O
O
V
†
‡
§
¶
#
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Unused pins at V
or GND
CC
The parameter I
includes the off-state output leakage current.
I(hold)
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (normal mode) (see Figure 14)
SN54LVTH18504A
= 3.3 V
SN74LVTH18504A
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency CLKAB or CLKBA
CLKAB or CLKBA high or low
100
80
100
80
MHz
ns
clock
4.4
3
5.6
3
4.4
3
5.6
3
Pulse duration
w
LEAB or LEBA high
A before CLKAB↑ or
B before CLKBA↑
2.4
2.8
2.4
2.8
CLK high
CLK low
1.5
1.6
2.8
1
0.7
1.6
3.4
0.8
1.1
3.5
0.2
1.5
1.6
2.8
1
0.7
1.6
3.4
0.8
1.1
3.5
0.2
t
Setup time
ns
ns
A before LEAB↓ or
B before LEBA↓
su
CLKEN before CLK↑
A after CLKAB↑
B after CLKBA↑
1.4
3.1
0.7
1.4
3.1
0.7
t
h
Hold time
A after LEAB↓ or B after LEBA↓
CLKEN after CLK↑
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (test mode) (see Figure 14)
SN54LVTH18504A
= 3.3 V
SN74LVTH18504A
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency TCK
50
40
50
40
MHz
ns
clock
Pulse duration
TCK high or low
9.5
10.5
9.5
10.5
w
A, B, CLK, CLKEN, LE, or OE
before TCK↑
6.5
7
6.5
7
t
Setup time
ns
ns
su
h
TDI before TCK↑
TMS before TCK↑
2.5
2.5
3.5
3.5
2.5
2.5
3.5
3.5
A, B, CLK, CLKEN, LE, or OE
after TCK↑
1.5
1
1.5
1
t
Hold time
TDI after TCK↑
TMS after TCK↑
Power up to TCK↑
1.5
1.5
50
1
1
1
1.5
1.5
50
1
1
1
t
t
Delay time
Rise time
50
1
50
1
ns
d
V
CC
power up
µs
r
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (normal mode) (see Figure 14)
SN54LVTH18504A
= 3.3 V
SN74LVTH18504A
= 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
PARAMETER
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
100
1.5
1.5
1.5
1.5
1.5
1.5
2
MAX
MIN
MAX
MIN
100
1.5
1.5
1.5
1.5
1.5
1.5
2
MAX
MIN
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
CLKAB or CLKBA
A or B
80
80
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
5.4
5.4
6.9
6.9
6.9
6.9
8.7
7.1
9.5
10
5.8
5.8
5.1
5.1
5.8
5.8
6.4
6.4
8.1
6.7
9.1
9.6
10.4
9.1
5.6
5.6
6.8
6.8
7.4
7.4
8.8
7.1
10
B or A
B
7.8
CLKAB
ns
ns
ns
ns
ns
7.8
7.8
CLKBA
A
7.8
9.5
LEAB or LEBA
OEAB or OEBA
OEAB or OEBA
B or A
B or A
B or A
2
7.4
2
2
10.5
10.8
12.7
9.9
2
2
2
10.4
11.2
9.5
2.5
2.5
12
2.5
2.5
9.6
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (test mode) (see Figure 14)
SN54LVTH18504A
= 3.3 V
SN74LVTH18504A
= 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
PARAMETER
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
50
2.5
2.5
1
MAX
MIN
MAX
MIN
50
2.5
2.5
1
MAX
MIN
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
TCK
40
40
MHz
ns
max
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
15
15
6
18
18
7
14
14
5.5
6.5
17
17
5.5
5.5
18
17
7
17
17
TCK↓
A or B
TDO
6.5
7.5
20
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
ns
ns
ns
ns
ns
1.5
4
7
8
1.5
4
18
18
6
21
21
7
A or B
TDO
4
4
20
1
1
6.5
6.5
20
1.5
4
6
7
1.5
4
19
18
7.5
7.5
21
19.5
9
A or B
TDO
4
4
18.5
8.5
8
1.5
1.5
1.5
1.5
8.5
7
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
recommended operating conditions
SN54LVTH182504A SN74LVTH182504A
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
CC
V
IH
V
IL
V
I
Supply voltage
3.6
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
–24
–12
24
0.8
5.5
–32
–12
32
A port, TDO
B port
I
High-level output current
Low-level output current
mA
mA
OH
A port, TDO
B port
I
I
OL
12
12
†
Low-level output current
A port, TDO
Outputs enabled
48
64
mA
ns/V
°C
OL
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
10
T
–55
125
–40
85
A
†
Current duty cycle ≤ 50%, f ≥ 1 kHz
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH182504A
SN74LVTH182504A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
‡
A, B, TDO
= MIN to MAX ,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –3 mA
= –8 mA
= –24 mA
= –32 mA
= –12 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
= 12 mA
V
CC
–0.2
2.4
2.4
2
V
CC
–0.2
2.4
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
2.4
A port,
TDO
V
OH
V
V
CC
= 3 V
2
2
B port
V
CC
V
CC
V
CC
= 3 V,
2
A, B, TDO
= 2.7 V,
= 2.7 V,
0.2
0.5
0.2
0.5
0.4
0.5
0.4
A port,
TDO
V
OL
0.5
V
V
CC
= 3 V
0.55
0.55
0.8
B port
V
V
= 3 V,
0.8
CC
CLK,
CLKEN,
LE, TCK
= 3.6 V,
V = V
I
or GND
±1
±1
CC
CC
‡
V
= 0 or MAX ,
V = 5.5 V
I
10
10
CC
CC
V = 5.5 V
I
5
1
5
1
OE,
TDI,
TMS
V
= 3.6 V
= 3.6 V
V = V
I
I
I
CC
µA
V = 0
I
–25
–100
20
–25
–100
20
V = 5.5 V
I
A or B
V
CC
V = V
I CC
1
1
§
ports
V = 0
I
–5
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
500
–500
1
µA
µA
off
CC
I
O
V = 0.8 V
I
75
500
–500
1
75
150
A or B
ports
¶
= 3 V
CC
I(hold)
V = 2 V
I
–75
–75
–150
I
I
I
I
TDO
TDO
TDO
TDO
V
CC
V
CC
V
CC
V
CC
= 3.6 V,
V
O
V
O
V
O
V
O
= 3 V
µA
µA
µA
µA
OZH
= 3.6 V,
= 0.5 V
–1
–1
OZL
= 0 to 1.5 V,
= 1.5 V to 0,
= 0.5 V or 3 V
= 0.5 V or 3 V
±50
±50
2
±50
±50
2
OZPU
OZPD
Outputs high
Outputs low
0.6
19.5
0.6
0.6
19.5
0.6
V
I
= 3.6 V,
= 0,
CC
O
I
27
27
mA
CC
V = V
I
or GND
CC
Outputs disabled
2
2
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
#
0.5
0.5
mA
∆I
CC
or GND
CC
C
C
C
V = 3 V or 0
4
10
8
4
10
8
pF
pF
pF
i
I
V
= 3 V or 0
= 3 V or 0
io
o
O
O
V
†
‡
§
¶
#
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Unused pins at V
or GND
CC
The parameter I
includes the off-state output leakage current.
I(hold)
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (normal mode) (see Figure 14)
SN54LVTH182504A
SN74LVTH182504A
V = 3.3 V
CC
± 0.3 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency CLKAB or CLKBA
CLKAB or CLKBA high or low
100
80
100
80
MHz
ns
clock
4.4
3
5.6
3
4.4
3
5.6
3
Pulse duration
w
LEAB or LEBA high
A before CLKAB↑ or
B before CLKBA↑
2.8
3
2.8
3
CLK high
CLK low
1.5
1.6
2.8
0.7
1.6
3.4
1.5
1.6
2.8
0.7
1.6
3.4
t
Setup time
ns
ns
A before LEAB↓ or
B before LEBA↓
su
h
CLKEN before CLK↑
A after CLKAB↑ or
B after CLKBA↑
1.4
1.1
1.4
1.1
t
Hold time
A after LEAB↓ or B after LEBA↓
CLKEN after CLK↑
3.1
0.7
3.5
0.2
3.1
0.7
3.5
0.2
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (test mode) (see Figure 14)
SN54LVTH182504A
SN74LVTH182504A
V = 3.3 V
CC
± 0.3 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency TCK
50
40
50
40
MHz
ns
clock
Pulse duration
TCK high or low
9.5
10.5
9.5
10.5
w
A, B, CLK, CLKEN, LE, or OE
before TCK↑
6.5
7
6.5
7
t
Setup time
ns
ns
su
h
TDI before TCK↑
TMS before TCK↑
2.5
2.5
3.5
3.5
2.5
2.5
3.5
3.5
A, B, CLK, CLKEN, LE, or OE
after TCK↑
1.5
1
1.5
1
t
Hold time
TDI after TCK↑
TMS after TCK↑
Power up to TCK↑
1.5
1.5
50
1
1
1
1.5
1.5
50
1
1
1
t
t
Delay time
Rise time
50
1
50
1
ns
d
V
CC
power up
µs
r
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (normal mode) (see Figure 14)
SN54LVTH182504A
= 3.3 V
SN74LVTH182504A
= 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
V
V
CC
± 0.3 V
CC
± 0.3 V
V
CC
= 2.7 V
V
CC
= 2.7 V
PARAMETER
UNIT
MIN
100
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
MAX
MIN
MAX
MIN
100
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
MAX
MIN
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLKAB or CLKBA
A
80
80
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
6.4
6.4
5.4
5.4
6.9
6.9
6.9
6.9
8.7
7.1
8.7
7.1
9.9
10.2
12
6.9
6.9
5.8
5.8
7.8
7.8
7.8
7.8
9.5
7.4
9.5
7.4
11.1
11
5.9
5.9
5.1
5.1
6.7
6.7
6.4
6.4
8.2
6.7
8.1
6.7
9.5
9.7
11.1
9.8
6.6
6.6
5.6
5.6
7.7
7.7
7.4
7.4
9.2
7.1
8.8
7.1
10.6
10.5
11.8
10
B
B
CLKAB
A
ns
ns
ns
ns
ns
ns
ns
B
A
CLKBA
LEAB
B
2
2
2
2
LEBA
A
2
2
2
2
B or A
B or A
OEAB or OEBA
OEAB or OEBA
2
2
2.5
2.5
12.7
11.2
2.5
2.5
11
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (test mode) (see Figure 14)
SN54LVTH182504A
= 3.3 V
SN74LVTH182504A
= 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
V
V
CC
± 0.3 V
CC
± 0.3 V
V
CC
= 2.7 V
V
CC
= 2.7 V
PARAMETER
UNIT
MIN
50
2.5
2.5
1
MAX
MIN
MAX
MIN
50
2.5
2.5
1
MAX
MIN
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
TCK
40
40
MHz
ns
max
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
15
15
6
18
18
7
14
14
5.5
6.5
17
17
5.5
5.5
18
17
7
17
17
TCK↓
A or B
TDO
6.5
7.5
20
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
ns
ns
ns
ns
ns
1.5
4
7
8
1.5
4
18
18
6
21
21
7
A or B
TDO
4
4
20
1
1
6.5
6.5
20
1.5
4
6
7
1.5
4
19
18
7.5
7.5
21
19.5
9
A or B
TDO
4
4
18.5
8.5
8
1.5
1.5
1.5
1.5
8.5
7
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
/t
S1
Open
S1
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
t
PLZ
t
t
t
PHL
PZL
PLH
PHL
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
Output
1.5 V
1.5 V
1.5 V
t
V
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
PZH
PHZ
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 14. Load Circuit and Voltage Waveforms
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1998, Texas Instruments Incorporated
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