SN54LVTH244AW_技术文档

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SCAS586J − DECEMBER 1996 − REVISED OCTOBER 2003

D

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

)

CC

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

= 3.3 V, T = 25°C

D

Latch-Up Performance Exceeds 500 mA Per

JESD 17

A

Support Unregulated Battery Operation

Down to 2.7 V

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

I

and Power-Up 3-State Support Hot

off

Insertion

SN74LVTH244A . . . RGY PACKAGE

(TOP VIEW)

SN54LVTH244A . . . J OR W PACKAGE

SN74LVTH244A . . . DB, DW, NS,

OR PW PACKAGE

SN54LVTH244A . . . FK PACKAGE

(TOP VIEW)

1

20

1

2

3

4

5

6

7

8

9

10

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

V

CC

20

19

18

17

16

15

14

3

2

1 20 19

18

19

18

17

16

15

14

13

12

2

3

4

5

6

7

8

9

1Y1

2A4

1Y2

2A3

1Y3

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

1A2

2Y3

1A3

2Y2

1A4

4

5

6

7

8

2OE

1Y1

2A4

1Y2

2A3

1Y3

17

16

15

14

9 10 11 12 13

13 2A2

12 1Y4

10

11

2A1

description/ordering information

These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) V

capability to provide a TTL interface to a 5-V system environment.

operation, but with the

CC

ORDERING INFORMATION

ORDERABLE

†

T

A

PACKAGE

TOP-SIDE MARKING

PART NUMBER

SN74LVTH244ARGYR

SN74LVTH244ADW

SN74LVTH244ADWR

SN74LVTH244ANSR

SN74LVTH244ADBR

SN74LVTH244APWR

SN74LVTH244AGQNR

SN74LVTH244AZQNR

SNJ54LVTH244AJ

QFN − RGY

SOIC − DW

Tape and reel

Tube

LXH244A

LVTH244A

Tape and reel

SOP − NS

LVTH244A

LXH244A

−40°C to 85°C

SSOP − DB

TSSOP − PW

VFBGA − GQN

VFBGA − ZQN (Pb-free)

CDIP − J

Tape and reel

LXH244A

Tube

SNJ54LVTH244AJ

SNJ54LVTH244AW

SNJ54LVTH244AFK

−55°C to 125°C

CFP − W

SNJ54LVTH244AW

SNJ54LVTH244AFK

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

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1

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SCAS586J − DECEMBER 1996 − REVISED OCTOBER 2003

description/ordering information (continued)

The ’LVTH244A devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When

OE is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the

high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

CC

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup

or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

SN74LVTH244A . . . GQN OR ZQN PACKAGE

(TOP VIEW)

terminal assignments

1

2

3

4

1

2

3

4

A

B

C

D

E

A

B

C

D

E

1A1

1A2

1A3

1A4

GND

1OE

2A4

2Y3

2A2

2Y1

V

2OE

1Y1

1Y2

1Y3

1Y4

CC

2Y4

2A3

2Y2

2A1

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

Y

OE

A

H

L

H

L

H

X

Z

2

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SCAS586J − DECEMBER 1996 − REVISED OCTOBER 2003

logic diagram (positive logic)

1

19

11

1OE

2OE

2A1

2

18

16

14

12

9

1Y1

1Y2

1Y3

1Y4

2Y1

1A1

4

13

15

17

7

2Y2

1A2

2A2

2A3

2A4

6

5

2Y3

1A3

8

3

2Y4

1A4

Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high-impedance

or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

O

CC

Current into any output in the low state, I : SN54LVTH244A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

O

SN74LVTH244A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Current into any output in the high state, I (see Note 2): SN54LVTH244A . . . . . . . . . . . . . . . . . . . . . . 48 mA

O

SN74LVTH244A . . . . . . . . . . . . . . . . . . . . . . 64 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

JA

(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W

(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W

(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W

(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

.

CC

O

3. The package thermal impedance is calculated in accordance with JESD 51-7.

4. The package thermal impedance is calculated in accordance with JESD 51-5.

3

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SCAS586J − DECEMBER 1996 − REVISED OCTOBER 2003

recommended operating conditions (see Note 5)

SN54LVTH244A SN74LVTH244A

UNIT

MIN

2.7

2

MAX

MIN

2.7

2

MAX

V

Supply voltage

3.6

V

CC

High-level input voltage

Low-level input voltage

Input voltage

IH

0.8

5.5

−24

48

0.8

5.5

−32

64

V

IL

V

I

High-level output current

Low-level output current

Input transition rise or fall rate

Power-up ramp rate

mA

ns/V

µs/V

°C

OH

OL

∆t/∆v

∆t/∆V

Outputs enabled

10

200

−55

200

−40

CC

T

A

Operating free-air temperature

125

85

NOTE 5: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

4

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SCAS586J − DECEMBER 1996 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LVTH244A

SN74LVTH244A

PARAMETER

TEST CONDITIONS

I = −18 mA

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

= 2.7 V,

−1.2

V

IK

CC

I

= 2.7 V to 3.6 V,

= 2.7 V,

I

= −100 µA

= −8 mA

= −24 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 48 mA

= 64 mA

V

−0.2

CC

2.4

V

−0.2

CC

2.4

OH

OL

V

OH

2

V

= 3 V

CC

2

0.2

0.5

0.2

0.5

0.4

0.5

V

= 2.7 V

0.4

V

OL

0.5

V

CC

= 3 V

0.55

10

1

V

= 0 or 3.6 V,

= 3.6 V,

V = 5.5 V

50

1

CC

I

Control inputs

V = V

or GND

CC

I

CC

I

µA

I

V = V

1

I

CC

Data inputs

V

= 3.6 V

= 0,

CC

V = 0

I

−5

100

V or V = 0 to 4.5 V

I

off

CC

O

V = 0.8 V

I

75

V

CC

V

CC

= 3 V

V = 2 V

I

−75

Data inputs

I(hold)

500

−750

‡

= 3.6 V ,

V = 0 to 3.6 V

I

V

= 3.6 V,

V

= 3 V

5

µA

OZH

CC

O

= 0.5 V

−5

OZL

O

= 0 to 1.5 V, V = 0.5 V to 3 V,

O

∗

100

µA

I

OZPU

OZPD

OE = don’t care

V

= 1.5 V to 0, V = 0.5 V to 3 V,

CC

OE = don’t care

O

∗

I

Outputs high

Outputs low

0.39

14

0.19

5

V

I

= 3.6 V,

CC

= 0,

I

mA

O

CC

V = V

I

or GND

CC

Outputs disabled

0.39

0.19

V

= 3 V to 3.6 V, One input at V − 0.6 V,

CC

Other inputs at V

§

0.2

∆I

CC

or GND

CC

C

V = 3 V or 0

3

7

3

7

pF

i

I

V

O

= 3 V or 0

o

∗

†

‡

§

On products compliant to MIL-PRF-38535, this parameter is not production tested.

All typical values are at V = 3.3 V, T = 25°C.

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

CC

A

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

CC

5

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SCAS586J − DECEMBER 1996 − REVISED OCTOBER 2003

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 1)

SN54LVTH244A

= 3.3 V

SN74LVTH244A

V

= 3.3 V

V

FROM

(INPUT)

TO

(OUTPUT)

CC

V

CC

= 2.7 V

PARAMETER

UNIT

CC

MIN

0.3 V

†

MIN

0.5

0.8

1.3

1.2

MAX

3.8

5

MIN

MAX

4.1

3.9

6

MIN TYP

MAX

3.5

3.3

4.5

4.4

MAX

3.8

3.6

5.3

4.9

4.5

4.4

t

1.1

1.3

1.1

1.4

1.9

1.8

2.3

2.1

2.5

2.7

2.8

2.9

PLH

PHL

PZH

PZL

PHZ

PLZ

A

Y

ns

OE

5

5.4

5.8

4.8

5.5

4.7

†

All typical values are at V

CC

= 3.3 V, T = 25°C.

A

6

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SCAS586J − DECEMBER 1996 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

6 V

TEST

S1

Open

GND

500 Ω

From Output

Under Test

t

/t

PLH PHL

Open

6 V

t

/t

PLZ PZL

C

= 50 pF

t

/t

GND

L

PHZ PZH

500 Ω

(see Note A)

2.7 V

0 V

LOAD CIRCUIT

Timing Input

Data Input

1.5 V

t

w

t

h

su

2.7 V

0 V

2.7 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

0 V

Output

Control

1.5 V

Input

t

PLZ

PZL

t

PHL

PLH

PHL

Output

Waveform 1

S1 at 6 V

3 V

V

OH

1.5 V

t

Output

V

+ 0.3 V

OL

V

OL

(see Note B)

t

PZH

PHZ

PLH

Output

Waveform 2

S1 at GND

V

OH

V

OH

− 0.3 V

OH

1.5 V

Output

≈0 V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

CFP

Drawing

5962-9584401Q2A

5962-9584401QRA

5962-9584401QSA

5962-9584401VRA

5962-9584401VSA

SN74LVTH244ADBLE

SN74LVTH244ADBR

ACTIVE

FK

J

20

1

None

Call TI

Level-NC-NC-NC

Call TI

ACTIVE

W

J

ACTIVE

CDIP

CFP

ACTIVE

W

DB

OBSOLETE

ACTIVE

SSOP

2000

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

SN74LVTH244ADW

SN74LVTH244ADWR

ACTIVE

SOIC

DW

20

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74LVTH244AGQNR

SN74LVTH244ANSR

ACTIVE

VFBGA

SO

GQN

NS

20

1000

2000

None

SNPB

Level-1-240C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

SN74LVTH244APW

ACTIVE

TSSOP

PW

20

70

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

SN74LVTH244APWLE

SN74LVTH244APWR

OBSOLETE TSSOP

PW

20

None

Call TI

ACTIVE

TSSOP

2000

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

SN74LVTH244ARGYR

SN74LVTH244AZQNR

QFN

RGY

ZQN

20

1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR

no Sb/Br)

VFBGA

1000

Pb-Free

(RoHS)

SNAGCU

Level-1-260C-UNLIM

SNJ54LVTH244AFK

SNJ54LVTH244AJ

SNJ54LVTH244AW

ACTIVE

LCCC

CDIP

CFP

FK

J

20

1

None

Call TI

Level-NC-NC-NC

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

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Use of such information may require a license from a third party under the patents or other intellectual property

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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dataconverter.ti.com

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dsp.ti.com

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Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

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Logic

interface.ti.com

logic.ti.com

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power.ti.com

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www.ti.com/opticalnetwork

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www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	SN54LVTH244AW
厂家：	TEXAS INSTRUMENTS
描述：	LVT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP20 驱动器输出元件
文件：	总20页 (文件大小：688K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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