SN54LVTR245J [TI]
3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 3.3 -V具有三态输出的八路ABT总线收发器
| 型号： | SN54LVTR245J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTR245, SN74LVTR245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS428 – OCTOBER 1993
SN54LVTR245 . . . J PACKAGE
SN74LVTR245 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
• State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
DIR
A1
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
• Supports Mixed-Mode Signal Operation
OE
B1
B2
B3
B4
B5
(5-V Input and Output Voltages With
A2
A3
A4
A5
3.3-V V
)
CC
• Supports Unregulated Battery Operation
Down to 2.7 V
• Typical V
(Output Ground Bounce)
A6
OLP
< 0.8 V at V
= 3.3 V, T = 25°C
A7
A8
13 B6
12 B7
CC
A
• Latch-Up Performance Exceeds 500 mA
11
GND
B8
Per JEDEC Standard JESD-17
• Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
SN54LVTR245 . . . FK PACKAGE
(TOP VIEW)
• Reduced Output Structure on A Port
Minimizes V
OHV
• Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic DIPs (J)
3
2
1
20 19
18
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
4
5
6
7
8
17
16
15
14
description
9 10 11 12 13
These octal bus transceivers are designed
specifically for low-voltage (3.3-V) V operation,
CC
but with the capability to provide a TTL interface to
a 5-V system environment.
The ′LVTR245 is designed for asynchronous communication between data buses. The device transmits data
from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectivelyisolated.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The A port is designed to minimize the undershoot exhibited on high to low transition during simultaneous
switching conditions.
The SN74LVTR245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVTR245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTR245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Copyright 1993, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTR245, SN74LVTR245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS428 – OCTOBER 1993
†
logic symbol
logic diagram (positive logic)
19
1
G3
OE
DIR
1
DIR
3EN1[BA]
3EN2[AB]
19
18
OE
B1
2
18
A1
B1
1
2
A1
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
To Seven Other Channels
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . –0.5 V to 7 V
O
Current into any output in the low state, I : SN54LVTR245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTR245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTR245 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTR245 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 W
A
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current will only flow when the output is in the high state and V > V
.
CC
O
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTR245, SN74LVTR245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS428 – OCTOBER 1993
recommended operating conditions
SN54LVTR245
SN74LVTR245
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
CC
V
IH
V
IL
V
I
Supply voltage
3.6
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
–24
–8
0.8
5.5
–32
–12
32
B port
A port
I
High-level output current
mA
OH
I
I
Low-level output current
24
mA
mA
OL
†
Low-level output current
48
64
OL
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
Outputs enabled
10
10
ns/V
°C
T
A
–55
125
–40
85
†
Current duty cycle ≤ 50%, f ≥ 1 kHz
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTR245, SN74LVTR245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS428 – OCTOBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTR245
SN74LVTR245
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
‡
= MIN to MAX ,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= – 8 mA
= – 24 mA
= –32 mA
= –100 µA
= – 1 mA
= – 3 mA
= – 8 mA
= –12 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
CC
2.4
2.4
B port
A port
2
V
CC
= 3 V
2
‡
V
OH
V
V
= MIN to MAX ,
V
CC
–0.2
V
CC
–0.2
V
CC
= 2.7 V,
2.4
2.4
CC
2.4
2
2.4
2
V
= 3 V
CC
CC
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
V
0.5
V
CC
= 3 V
0.55
0.55
±1
10
20
5
V
V
= 3.6 V,
V = V
I
or GND
±1
10
CC
CC
Control pins
‡
= 0 or MAX ,
V = 5.5 V
I
CC
I
I
V = 5.5 V
I
100
5
µA
µA
§
V
CC
= 3.6 V
V = V
I CC
A or B ports
A or B ports
V = 0
I
–5
–5
V = 0.8 V
I
75
75
I
V
CC
= 3 V
I(hold)
V = 2 V
I
–75
–75
I
I
V
V
= 3.6 V,
= 3.6 V,
V
= 3 V
1
–1
1
–1
µA
µA
OZH
CC
O
O
V
= 0.5 V
OZL
CC
Outputs high
Outputs low
0.13
8.8
0.5
14
0.13
8.8
0.19
12
V
= 3.6 V,
or GND
CC
I
= 0,
CC
O
I
mA
CC
V = V
I
Outputs
disabled
0.13
0.5
0.3
0.13
0.19
0.2
V
= 3 V to 3.6 V,
One input at V
or GND
– 0.6 V,
CC
CC
Other inputs at V
¶
∆I
CC
mA
CC
C
C
V = 3 V or 0
4
4
pF
pF
i
I
V
O
= 3 V or 0
10
10
io
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Unused pins at V or GND
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTR245, SN74LVTR245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS428 – OCTOBER 1993
switching characteristics, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54LVTR245
= –55°C to 125°C
SN74LVTR245
T = –40°C to 85°C
A
T
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
= 3.3 V
UNIT
CC
± 0.3 V
V
CC
= 2.7 V
V
CC
= 3.3 V ± 0.3 V
V
CC
= 2.7 V
†
MIN MAX
MIN
MAX
4.8
5.4
5.9
5.3
7
MIN TYP
MAX
4.2
4.4
4.6
4.1
5.5
6
MIN
MAX
4.7
5.3
5.8
5.1
6.7
8.3
8
B
A
B
A
B
A
B
A
B
A
B
A
1.1
1.4
1.1
1
4.3
4.5
4.7
4.2
5.9
6.1
6.7
6.5
6.5
6.2
5.6
5.5
1.1
1.4
1.1
1
2.5
2.7
2.6
2.3
3.1
3.6
3.9
3.8
4.2
4
A
B
A
B
t
ns
PLH
t
t
t
t
t
ns
ns
ns
ns
ns
PHL
PZH
PZL
PHZ
PLZ
1.3
1.6
2
1.3
1.6
2
OE
OE
OE
OE
8.4
8.1
7.7
7
6.6
6.4
6.1
5.8
5.2
5.2
1.8
2.7
2.5
2.4
2.4
1.8
2.7
2.5
2.4
2.4
7.6
6.7
6.4
5.4
5.3
6.8
5.6
5.6
3.7
3.7
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTR245, SN74LVTR245
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS428 – OCTOBER 1993
PARAMETER MEASUREMENT INFORMATION
7 V
S1
500 Ω
Open
GND
From Output
Under Test
TEST
S1
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
2.7 V
0 V
Output
Control
1.5 V
1.5 V
t
PZL
2.7 V
t
PLZ
Input
(see Note B)
Output
Waveform 1
S1 at 7 V
3 V
1.5 V
1.5 V
1.5 V
0 V
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
(see Note C)
t
t
PHL
PLH
t
PHZ
t
V
PZH
OH
Output
Waveform 2
S1 at Open
(see Note C)
1.5 V
V
OH
1.5 V
Output
OH
V
OL
1.5 V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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