SN54SLC8T245PWTSEP [TI]
抗辐射、8 位、0.65V 至 3.3V 方向控制电平转换器 | PW | 24 | -55 to 125;
| 型号： | SN54SLC8T245PWTSEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 抗辐射、8 位、0.65V 至 3.3V 方向控制电平转换器 | PW | 24 | -55 to 125 转换器 电平转换器 |
| 文件： | 总22页 (文件大小：1208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54SLC8T245-SEP
ZHCSPJ9A –FEBRUARY 2022 –REVISED SEPTEMBER 2022
SN54SLC8T245-SEP 具有可配置电压转换和三态输出的8 位双电源总线收发器
1 特性
3 说明
• VID V62/22604
• 抗辐射：
SN54SLC8T245-SEP 器件是一款 8 位同相总线收发
器，可解决在最新电压节点（0.7V、0.8V 和 0.9V）和
业界通用电压节点（1.8V、2.5V 和 3.3V）上运行的器
件间的电压电平不匹配问题。
– 单粒子锁定(SEL) 在125°C 下的抗扰度可达
43MeV-cm2/mg
– 每个晶圆批次的辐射批次验收测试(RLAT) 电离
辐射总剂量(TID) 高达20krad(Si)
• 通过认证且完全可配置的双电源轨设计允许各个端
口在0.65V 至3.6V 的电源电压范围内运行
• 工作温度范围为-55°C 至+125°C
• 多向控制引脚，支持同步升降转换
• 从1.8V 转换到3.3V 时，支持高达380Mbps 的转
换速率
• VCC 隔离功能可在断电情况下有效隔离两条总线
• 局部断电模式可在断电情况下限制回流电流
• 闩锁性能超过100mA，符合JESD 78 II 类规范
• ESD 保护性能超过JESD 22 规范要求
器件通过两条独立电源轨（VCCA 和 VCCB）运行，工
作电压可低至 0.65V。数据引脚 A1 至 A8 均用于跟踪
VCCA，可承受 0.65V 至 3.6V 的电源电压。数据引脚
B1 至 B8 均用于跟踪 VCCB，可承受 0.65V 至 3.6V 的
电源电压。
SN54SLC8T245-SEP 器件旨在实现数据总线之间的异
步通信。根据方向控制输入（DIR1 和 DIR2）的逻辑
电平，此器件将数据从 A 总线传输至 B 总线，或者将
数据从 B 总线传输至 A 总线。输出使能 (OE) 输入可
用于禁用输出，从而有效隔离总线。
SN54SLC8T245-SEP 器件旨在使控制引脚（DIR 和
OE）以VCCA 为基准。
– 8000V 人体放电模型
– 1000V 充电器件模型
该器件专用于使用 Ioff 的局部断电应用。当器件断电
时，Ioff 电路将会禁用输出。这会抑制电流反流到器件
中，从而防止损坏器件。
2 应用
• 支持近地轨道(LEO) 航天应用
• 太空雷达和通信
• 航天卫星有效载荷
VCC 隔离功能可确保当任一 VCC 输入电源低于 100mV
时，所有电平转换器输出都将禁用并处于高阻抗状态。
3.3 V
1.5 V
为了确保电平转换器I/O 在上电或断电期间处于高阻抗
状态，应将 OE 通过上拉电阻器连接到 VCCA；此电阻
器的最小值由驱动器的灌电流能力决定。
Processor
VCCA DIR1 DIR2
VCCB
B1
Power Management
A1
A2
A3
Control Block
B2
B3
B4
B5
B6
B7
B8
A4
SN54SLC8T245-SEP
Data Block
Interrupts
Register Map
Sensor Block
A5
A6
A7
封装信息
封装尺寸（标称
封装(1)
器件型号
A8
值）
GND
GND
SN54SLC8T245-SEP PW (TSSOP, 24)
4.40mm × 7.80mm
典型应用原理图
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES946
SN54SLC8T245-SEP
ZHCSPJ9A –FEBRUARY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
Table of Contents
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................12
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................14
11 Layout...........................................................................15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 Receiving Notification of Documentation Updates..16
12.3 Support Resources................................................. 16
12.4 Trademarks.............................................................16
12.5 Electrostatic Discharge Caution..............................16
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCCA = 0.7 V..................... 7
6.7 Switching Characteristics, VCCA = 0.8 V..................... 7
6.8 Switching Characteristics, VCCA = 0.9 V..................... 7
6.9 Switching Characteristics, VCCA = 1.2 V..................... 8
6.10 Switching Characteristics, VCCA = 1.5 V................... 8
6.11 Switching Characteristics, VCCA = 1.8 V................... 8
6.12 Switching Characteristics, VCCA = 2.5 V................... 9
6.13 Switching Characteristics, VCCA = 3.3 V................... 9
6.14 Operating Characteristics......................................... 9
7 Parameter Measurement Information..........................10
Information.................................................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (February 2022) to Revision A (September 2022)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Pin Configuration and Functions
VCCA
DIR1
A1
1
24
23
22
21
20
19
18
17
VCCB
VCCB
OE
B1
2
3
A2
4
A3
5
B2
A4
6
B3
A5
7
B4
A6
8
B5
A7
9
16
15
14
13
B6
A8
10
11
12
B7
DIR2
GND
B8
GND
图5-1. PW Package, 24-Pin TSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR1
3
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Input/output A1. Referenced to VCCA
Input/output A2. Referenced to VCCA
Input/output A3. Referenced to VCCA
Input/output A4. Referenced to VCCA
Input/output A5. Referenced to VCCA
Input/output A6. Referenced to VCCA
Input/output A7. Referenced to VCCA
Input/output A8. Referenced to VCCA
Input/output B1. Referenced to VCCB
Input/output B2. Referenced to VCCB
Input/output B3. Referenced to VCCB
Input/output B4. Referenced to VCCB
Input/output B5. Referenced to VCCB
Input/output B6. Referenced to VCCB
Input/output B7. Referenced to VCCB
Input/output B8. Referenced to VCCB
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
5
6
7
8
9
10
21
20
19
18
17
16
15
14
2
Direction-control signal 1. Referenced to VCCA
.
Direction-control signal 2. Referenced to VCCA. Tie to GND to maintain backward
compatibility with SN74AVC8T245 device.
DIR2
GND
11
I
12
13
Ground
—
—
Ground
Output Enable. Pull to GND to enable all outputs. Pull to VCCA to place all outputs in high-
OE
22
I
impedance mode. Referenced to VCCA
.
VCCA
1
A-port supply voltage. 0.65 V ≤VCCA ≤3.6 V
B-port supply voltage. 0.65 V ≤VCCB ≤3.6 V
B-port supply voltage. 0.65 V ≤VCCB ≤3.6 V
—
—
—
23
24
VCCB
(1) I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–50
MAX
4.2
4.2
4.2
4.2
4.2
4.2
4.2
UNIT
V
Supply voltage, VCCA
Supply voltage, VCCB
V
I/O ports (A port)
I/O ports (B port)
Control inputs
A port
(2)
Input voltage, VI
V
V
Voltage applied to any output
in the high-impedance or power-off state, VO
(2)
B port
A port
VCCA + 0.2
VCCB + 0.2
(2) (3)
Voltage applied to any output in the high or low state, VO
V
B port
Input clamp current, IIK
VI < 0
mA
mA
mA
mA
°C
Output clamp current, IOK
VO < 0
–50
Continuous output current, IO
Continuous current through VCCA, VCCB, or GND
Junction Temperature, TJ
50
–50
100
150
150
–100
Storage temperature, Tstg
°C
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±8000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
0.65
MAX
3.6
UNIT
V
VCCA
VCCB
Supply voltage
Supply voltage
0.65
3.6
V
VCCI × 0.70
VCCI × 0.70
VCCI × 0.65
1.6
VCCI = 0.65 V –0.75 V
VCCI = 0.76 V –1 V
VCCI = 1.1 V –1.95 V
VCCI = 2.3 V –2.7 V
VCCI = 3 V –3.6 V
Data inputs
2
VIH
High-level input voltage
V
VCCA × 0.70
VCCA × 0.70
VCCA × 0.65
1.6
VCCA = 0.65 V –0.75 V
VCCA = 0.76 V –1 V
VCCA = 1.1 V –1.95 V
VCCA = 2.3 V –2.7 V
VCCA = 3 V –3.6 V
VCCI = 0.65 V –0.75 V
VCCI = 0.76 V –1 V
VCCI = 1.1 V –1.95 V
VCCI = 2.3 V –2.7 V
VCCI = 3 V –3.6 V
Control inputs
(DIR, OE)
Referenced to VCCA
2
VCCI × 0.30
VCCI × 0.30
VCCI × 0.35
0.7
Data inputs
0.8
VIL
Low-level input voltage
V
VCCA × 0.30
VCCA × 0.30
VCCA × 0.35
0.7
VCCA = 0.65 V –0.75 V
VCCA = 0.76 V –1 V
VCCA = 1.1 V –1.95 V
VCCA = 2.3 V –2.7 V
VCCA = 3 V –3.6 V
Control inputs
(DIR, OE)
Referenced to VCCA
0.8
VI
Input voltage(3)
Output voltage
0
0
0
3.6
V
V
(2)
Active state
Tri-state
VCCO
VO
3.6
10
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
Δt/Δv
TA
125
–55
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the Implications of Slow or
Floating CMOS Inputs application report.
6.4 Thermal Information
SN54SLC8T245-SEP
THERMAL METRIC
PW (TSSOP)
24 PINS
102.9
45.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
58.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.9
ψJT
57.8
ψJB
RθJC(bot)
N/A
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MAX UNIT
6.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –50 µA
IOH = –200 µA
IOH = –500 µA
IOH = -3 mA
IOH = -6 mA
IOH = -8 mA
IOH = -9 mA
IOH = -12 mA
IOL = 100 µA
IOL = 50 µA
VCCA
0.7 V –3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
VCCB
0.7 V –3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
MIN
CCO –0.1
0.55
TYP(2)
V
0.58
0.65
High-level output
voltage
VOH
VI = VIH
V
0.85
1.4 V
1.4 V
1.05
1.65 V
2.3 V
1.65 V
2.3 V
1.2
1.75
3 V
3 V
2.3
0.1
0.1
0.7 V –3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.7 V –3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
IOL = 200 µA
IOL = 500 µA
IOL = 3 mA
0.18
0.2
Low-level output
voltage
VOL
VI = VIL
V
0.25
0.35
0.45
0.55
0.7
IOL = 6 mA
1.4 V
1.4 V
IOL = 8 mA
1.65 V
2.3 V
1.65 V
2.3 V
IOL = 9 mA
IOL = 12 mA
3 V
3 V
Input leakage
current
Control Inputs (DIR, OE):
VI = VCCA or GND
II
1
55
55
µA
µA
0.65 V –3.6 V
0.65 V –3.6 V
0 V –3.6 V
0 V
−1
−35
−35
A Port:
VI or VO = 0 V –3.6 V
0 V
Partial power
down current
Ioff
B Port:
VI or VO = 0 V –3.6 V
0 V –3.6 V
A Port:
VO = VCCO or GND, VI = VCCI or GND,
OE = VIH
3.6 V
3.6 V
3.6 V
8
−8
−8
High-impedance
state output
current
IOZ
µA
B Port:
VO = VCCO or GND, VI = VCCI or GND,
OE = VIH
3.6 V
8
40
0.65 V –3.6 V
0 V
0.65 V –3.6 V
3.6 V
VCCA supply
current
ICCA
VI = VCCI or GND, IO = 0 mA
µA
µA
−12
−12
3.6 V
0 V
35
38
0.65 V –3.6 V
0.65 V –3.6 V
VCCB supply
current
ICCB
VI = VCCI or GND, IO = 0 mA
VI = VCCI or GND, IO = 0 mA
0 V
3.6 V
0 V
35
3.6 V
ICCA
ICCB
+
Combined supply
current
70
µA
pF
0.65 V –3.6 V
0.65 V –3.6 V
Control Inputs (DIR, OE):
VI = 3.3 V or GND
Ci
Input capacitance
3.3 V
3.3 V
4.5
5.7
Ports A and B:
OE = VCCA, VO = 1.65 V DC +
1 MHz -16 dBm sine wave
Data I/O
capacitance
Cio
3.3 V
3.3 V
pF
(1) VCCO is the VCC associated with the output port.
(2) All typical values are for TA = 25°C
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6.6 Switching Characteristics, VCCA = 0.7 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ± 1.5 V ± 1.8 V ± 2.5 V ± 3.3 V ±
PARAMETER
TEST CONDITIONS
UNIT
0.1 V
TYP
23
0.1 V
TYP
21
0.15 V 0.2 V
0.3 V
TYP
TYP
TYP
TYP
TYP
TYP
68
47
34
21
23
From input A to output B
27
25
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
67
55
46
32
26
25
From input B to output A
From input OE to output A
From input OE to output B
28
100
34
100
111
100
86
100
73
100
38
100
34
100
33
100
36
105
127
From input OE to output A
From input OE to output B
105
78
105
56
105
39
105
36
105
36
105
39
105
47
Enable time
6.7 Switching Characteristics, VCCA = 0.8 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ±
0.1 V
1.5 V ±
0.1 V
1.8 V ±
0.15 V
2.5 V ±
0.2 V
3.3 V ±
0.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
TYP
From input A to output B
From input B to output A
From input OE to output A
From input OE to output B
From input OE to output A
From input OE to output B
55
38
26
16
14
13
13
14
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
47
71
38
32
21
71
32
64
30
17
71
28
64
27
15
71
27
64
26
14
71
25
64
26
14
71
26
64
28
71
79
71
66
105
64
64
69
64
47
Enable time
118
6.8 Switching Characteristics, VCCA = 0.9 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ±
0.1 V
1.5 V ±
0.1 V
1.8 V ±
0.15 V
2.5 V ±
0.2 V
3.3 V ±
0.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
TYP
From input A to output B
From input B to output A
From input OE to output A
From input OE to output B
From input OE to output A
From input OE to output B
45
31
21
13
10
9
9
9
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
35
55
27
55
74
41
63
23
55
61
41
41
15
55
26
41
24
11
55
23
41
20
10
55
22
41
19
9
8
55
20
41
18
55
20
41
19
99
41
Enable time
108
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6.9 Switching Characteristics, VCCA = 1.2 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ±
0.1 V
1.5 V ±
0.1 V
1.8 V ±
0.15 V
2.5 V ±
0.2 V
3.3 V ±
0.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
TYP
From input A to output B
From input B to output A
From input OE to output A
From input OE to output B
From input OE to output A
From input OE to output B
33
21
14
8
6
5
5
5
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
24
19
92
19
96
16
19
66
19
53
13
19
53
19
33
8
6
5
4
4
19
20
19
17
19
17
19
12
19
16
19
11
19
14
19
10
19
14
19
10
Enable time
6.10 Switching Characteristics, VCCA = 1.5 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ±
0.1 V
1.5 V ±
0.1 V
1.8 V ±
0.15 V
2.5 V ±
0.2 V
3.3 V ±
0.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
TYP
From input A to output B
From input B to output A
From input OE to output A
From input OE to output B
From input OE to output A
From input OE to output B
29
17
11
6
5
4
4
3
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
23
15
89
12
92
14
15
64
12
49
10
15
50
12
29
6
5
4
3
3
15
18
12
14
15
15
12
10
15
15
12
8
15
12
12
7
15
13
12
7
Enable time
6.11 Switching Characteristics, VCCA = 1.8 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ±
0.1 V
1.5 V ±
0.1 V
1.8 V ±
0.15 V
2.5 V ±
0.2 V
3.3 V ±
0.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
TYP
From input A to output B
From input B to output A
From input OE to output A
From input OE to output B
From input OE to output A
From input OE to output B
28
15
9
5
4
4
3
3
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
23
14
89
9
13
14
63
9
9
5
4
14
15
9
4
14
14
9
3
14
12
9
2
14
12
9
14
49
9
14
17
9
Enable time
91
47
28
13
9
7
6
6
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6.12 Switching Characteristics, VCCA = 2.5 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ±
0.1 V
1.5 V ±
0.1 V
1.8 V ±
0.15 V
2.5 V ±
0.2 V
3.3 V ±
0.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
TYP
From input A to output B
From input B to output A
From input OE to output A
From input OE to output B
From input OE to output A
From input OE to output B
27
14
8
4
3
3
2
2
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
26
11
88
6
13
11
62
6
8
5
4
11
13
6
3
11
13
6
2
11
11
6
2
11
11
6
11
48
6
11
16
6
Enable time
89
46
26
12
8
7
5
5
6.13 Switching Characteristics, VCCA = 3.3 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
0.7 V ±
0.05 V
0.8 V ±
0.04 V
0.9 V ±
0.045 V
1.2 V ±
0.1 V
1.5 V ±
0.1 V
1.8 V ±
0.15 V
2.5 V ±
0.2 V
3.3 V ±
0.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
TYP
TYP
From input A to output B
From input B to output A
From input OE to output A
From input OE to output B
From input OE to output A
From input OE to output B
27
13
8
4
3
2
2
2
tpd
tdis
ten
Propagation delay
Disable time
ns
ns
ns
31
11
87
5
14
11
61
5
9
5
11
16
5
3
11
13
5
3
11
12
5
2
11
11
5
2
11
11
5
11
48
5
Enable time
89
45
26
11
8
6
5
4
6.14 Operating Characteristics
TA = 25°C, CL = 0, RL = Open, f = 1 MHz, tr = tf = 1 ns
SUPPLY VOLTAGE (VCCA = VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V
0.8 V
TYP
0.9 V
TYP
1.2 V
TYP
1.5 V
TYP
1.8 V
TYP
2.5 V
TYP
3.3 V
UNIT
TYP
1.2
1.1
9.3
2.6
9.3
2.6
1.2
1.1
TYP
2.5
2.1
18.1
3.9
18
A to B: Ouputs Enabled
A to B: Ouputs Disabled
B to A: Ouputs Enabled
B to A: Ouputs Disabled
A to B: Ouputs Enabled
A to B: Ouputs Disabled
B to A: Ouputs Enabled
B to A: Ouputs Disabled
1.8
1.8
1.8
1.8
1.7
1.7
12
1.7
1.7
1.7
1.7
13
2
2
pF
pF
pF
pF
pF
pF
pF
pF
VCCA Power
dissipation
capacitance per
transceiver
CpdA
11.8
1.2
11.8
1.1
12.2
1.2
16.4
1.6
16.3
16.3
2
1.2
11.9
11.9
1.7
1.7
1.3
12.9
12.9
1.7
1.7
11.7
11.7
1.8
11.8
11.8
1.8
12.2
12.2
1.7
VCCB Power
dissipation
capacitance per
transceiver
3.9
2.5
2.1
CpdB
1.8
1.8
1.7
2
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7 Parameter Measurement Information
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f =1 MHz
• Z0 = 50 Ω
• dv / dt ≤1 ns/V
Measurement Point
VCCO
RL
CL
VTP
Parameter
tpd
S1
Open
2 X VCCO
Open
S1
1.1 V - 3.6 V
2 kꢀ 15 pF
N/A
N/A
RL
Open
0.65 V - 0.95 V 20 kꢀ 15 pF
3 V - 3.6 V 2 kꢀ 15 pF
1.65 V - 2.7 V 2 kꢀ 15 pF
1.1 V - 1.6 V
0.65 V - 0.95 V 20 kꢀ 15 pF
3 V - 3.6 V 2 kꢀ 15 pF
1.65V - 2.7 V 2 kꢀ 15 pF
1.1 V - 1.6 V 2 kꢀ 15 pF
0.65 V - 0.95 V 20 kꢀ 15 pF
Output Pin
Under Test
2 X VCCO
2 X VCCO
0.3 V
0.15 V
0.1 V
0.1 V
GND
(1)
ten(1), tdis
(1)
CL
RL
2 kꢀ 15 pF 2 X VCCO
2 X VCCO
GND
0.3 V
GND
0.15 V
(2)
ten(2), tdis
A. CL includes probe and jig capacitance.
GND
GND
0.1 V
0.1 V
图7-1. Load Circuit
A. Output waveform on the conditions that input is driven to a valid
Logic Low.
B. Output waveform on the condition that input is driven to a valid
Logic High.
图7-2. Load Circuit Conditions
(1)
VCCI
VCCA
OE
VCCA / 2
VCCA / 2
VCCI / 2
VCCI / 2
An, Bn Input
GND
GND
tpd
tpd
tdis
ten
(2)
VOH
(3)
VCCO
Output(1)
VCCO / 2
VCCO / 2
Bn, An Output
VCCO / 2
(2)
VOL
VOL + VTP
(4)
VOL
A. VCCI is the supply pin associated with the input port.
(4)
VOH
B. VOH and VOL are typical output voltage levels with specified RL,
CL, and S1.
VOH - VTP
Output(2)
VCCO / 2
图7-3. Propagation Delay
GND
A. Output waveform on the condition that input is driven to a valid
Logic Low.
B. Output waveform on the condition that input is driven to a valid
Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL,
CL, and S1.
图7-4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN54SLC8T245-SEP device is an 8-bit, dual-supply non-inverting transceiver with bidirectional voltage level
translation. The I/O pins labeled with A and the control pins (DIR1, DIR2, and OE) are supported by VCCA, and
the I/O pins labeled with B are supported by VCCB. The A port and the B port are able to accept I/O voltages
ranging from 0.65 V to 3.6 V.
8.2 Functional Block Diagram
OE
VCCA
Control Block To Enable or
Disable Outputs (Note: Inputs
on each buffer are always
enabled)
DIR1
VCCB
DIR2
GND
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
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8.3 Feature Description
8.3.1 Up-Translation and Down-Translation From 0.65 V to 3.6 V
Both supply pins are configured from 0.65 V to 3.6 V, which makes the device suitable for translating between
any of the low voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.2 Multiple Direction Control Pins
Two control pins are used to configure the 8 data I/Os. I/O channels 1 through 4 are grouped together and I/O
channels 5 through 8 are banked together. The benefit of this is to permit simultaneous up-translation and down-
translation within one device. This eliminates the need for multiple devices, where each device can only provide
up-translation or down-translation sequentially. Simultaneous up and down translation is supported when both
VCCA and VCCB are at least 1.40 V.
8.3.3 Ioff Supports Partial-Power-Down Mode Operation
This feature is to limit the leakage current of an I/O pin being driven to a voltage as large as 3.6 V while having
its corresponding power supply rail powered down. This is represented by the Ioff parameter in the Electrical
Characteristics table.
8.4 Device Functional Modes
All control inputs are referenced to VCCA and must be driven to a valid Logic High or Logic Low (that is, not
floating) to assure proper device operation and to prevent excessive power consumption. 表8-1 summarizes the
possible modes of device operation based on the configuration of the control inputs.
表8-1. Function Table
CONTROL INPUTS(1)
SIGNAL DIRECTION
OE
H
L
DIR1
DIR2
Bits 1:4
Bits 5:8
X
L
X
L
Disabled (Hi-Z)
B to A
L
L
H
L
B to A
A to B
A to B
B to A
L
H
H
A to B
L
H
(1) Input circuits of the data I/Os are always active and must be driven to a valid logic level.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN54SLC8T245-SEP device can be used in level-translation applications for interfacing devices or systems
operating at different voltage nodes. 图 9-1 depicts an application in which the SN54SLC8T245-SEP device is
up-translating a 0.7 V input to a 3.3 V output to interface between a system controller and a peripheral device.
9.2 Typical Application
0.7 V
3.3 V
0.1 µF
0.1 µF
10
kΩ
10
kΩ
VCCA
VCCB
OE
DIR1
DIR2
GND
10
kΩ
Controller
SN54SLC8T245-SEP
Peripheral
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
图9-1. Typical Application Schematic
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9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
0.65 V to 3.6 V
0.65 V to 3.6 V
Input voltage range
Output voltage range
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN54SLC8T245-SEP device to determine the input
voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low,
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN54SLC8T245-SEP device is driving to determine the
output voltage range.
9.2.3 Application Curve
图9-2. Translation Up (0.7 V to 3.3 V) at 2.5 MHz
10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. There are no additional requirements for power supply
sequencing.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of level
translators, see the Power Sequencing for AXC Family of Devices application report.
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11 Layout
11.1 Layout Guidelines
To assure reliability of the device, follow common printed-circuit board layout guidelines:
• Use bypass capacitors on power supplies.
• Use short trace lengths to avoid excessive loading.
• Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane (Inner Layer)
VIA to GND Plane (Inner Layer)
Bypass Capacitor
VCCA
Bypass
Capacitor
1
2
VCCA
DIR1
A1
24
23
22
21
20
19
18
17
16
15
14
13
VCCB
VCCB
OE
B1
From Source
From Source
From Source
From Source
From Source
From Source
From Source
From Source
3
To Destination
4
A2
To Destination
To Destination
5
A3
B2
6
A4
B3
SN54SLC8T245-SEP
(PW Package)
To Destination
To Destination
7
A5
B4
8
A6
B5
To Destination
To Destination
9
A7
B6
10
11
12
A8
B7
To Destination
DIR2
GND
B8
GND
图11-1. SN54SLC8T245-SEP Device Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN54SLC8T245PWTSEP
V62/22604-01XE
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
24
24
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
SLC8T245E
SLC8T245E
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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26-Mar-2023
Addendum-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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