SN64BCT126ANSR [TI]
Quadruple Bus Buffer Gate With 3-State Outputs 14-SO -40 to 85;型号: | SN64BCT126ANSR |
厂家: | TEXAS INSTRUMENTS |
描述: | Quadruple Bus Buffer Gate With 3-State Outputs 14-SO -40 to 85 输出元件 |
文件: | 总5页 (文件大小:83K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JULY 1998
D OR N PACKAGE
(TOP VIEW)
State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
3-State Outputs Drive Bus Lines or
Buffer-Memory Address Registers
1OE
1A
1Y
2OE
2A
2Y
1
2
3
4
5
6
7
14
13
12
11
10
9
V
4OE
4A
4Y
3OE
3A
CC
ESD Protection Exceeds 2000 V
Per MIL-STD-883 Method 3015
High-Impedance State During Power Up
and Power Down
Package Options Include Plastic
Small-Outline (D) and Standard Plastic
300-mil DIPs (N)
GND
8
3Y
description
The SN64BCT126A bus buffer features independent line drivers with 3-state outputs. Each output is disabled
when the associated output-enable (OE) input is low.
The SN64BCT126A is characterized for operation from – 40°C to 85°C and 0°C to 70°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
†
logic symbol
logic diagram (positive logic)
1
1
1
1OE
2
EN
3
6
1OE
1Y
2Y
1A
4
2
3
6
2OE
5
1A
1Y
2Y
3Y
4Y
2A
10
4
3OE
9
8
2OE
3Y
4Y
3A
5
13
11
2A
4OE
12
4A
10
3OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
9
8
3A
13
4OE
12
11
4A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JULY 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Current into any output in the low state, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
CC
O
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative voltage rating may be exceeded if the input clamp current rating is observed.
2. ThepackagethermalimpedanceiscalculatedinacordanewithJESD51,exceptforthrough-holepackages,whichuseatracelength
of zero.
recommended operating conditions (see Note 3)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
–15
64
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
–40
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JULY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
= 4.5 V,
= 4.5 V
–1.2
V
IK
CC
I
I
I
I
= –3 mA
= –15 mA
= 64 mA
= 2.7 V
2.4
2
3.3
3.1
OH
OH
OH
V
OH
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
0.42
0.55
50
V
OL
I
I
= 5.5 V,
V
µA
µA
OZH
O
O
= 5.5 V,
V
= 0.5 V
–50
50
OZL
= 0 to 1.3 V (power up)
I
V
O
= 2.7 V or 0.5 V,
µA
OE at 2 V
OZ
= 1.3 V to 0 (power down)
50
I
I
I
I
I
I
= 0,
V = 7 V
I
0.1
25
mA
µA
I
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
= 5.5 V
V = 2.7 V
I
IH
IL
V = 0.5 V
I
–20
–225
51
µA
‡
V
O
= 0
–100
mA
mA
mA
OS
35
21
CCL
CCH
33
I
V
CC
V
CC
V
CC
= 5.5 V
= 5 V,
= 5 V,
5
4
9
10
mA
pF
pF
CCZ
C
C
V = 2.5 V or 0.5 V
I
i
V
O
= 2.5 V or 0.5 V
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V
= 50 pF,
CC
L
V
C
= 5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
T
A
= –40°C
to 85°C
T = 0°C
A
to 70°C
= 25°C
MIN
1.5
2.7
2.6
3.7
3.2
3.4
TYP
3.6
5.3
4.8
6.4
6.6
6.5
MAX
4.9
6.9
6.4
8.3
8.2
8
MIN MAX
MIN MAX
t
t
t
t
t
t
1.5
2.7
2.6
3.7
3.2
3.4
6.3
7.7
1.5
2.7
2.6
3.7
3.2
3.4
6.3
7.4
7.9
10
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
7.9
OE
OE
10.5
10
10
12.3
10.7
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SN64BCT126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCBS051C – AUGUST 1990 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
7 V (t
, t
, O.C.)
PZL PLZ
Open
(all others)
S1
From Output
Under Test
Test
Point
C
L
R1
R1
(see Note A)
From Output
Under Test
Test
Point
C
L
R2
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
R
= R1 = R2
L
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3 V
0 V
1.5 V
1.5 V
3 V
Timing Input
(see Note B)
1.5 V
t
w
0 V
3 V
0 V
3 V
0 V
t
h
Low-Level
Pulse
t
su
1.5 V
1.5 V
Data Input
(see Note B)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level enable)
3 V
1.5 V
1.5 V
Input
(see Note B)
1.5 V
1.5 V
0 V
PHL
t
t
PZL
t
t
PLZ
t
PLH
3.5 V
In-Phase
Output
(see Note D)
V
OH
1.5 V
Waveform 1
(see Notes C and D)
1.5 V
1.5 V
1.5 V
t
V
OL
V
OL
0.3 V
t
PHZ
PLH
t
PHL
PZH
V
OH
V
OH
Out-of-Phase
Output
(see Note D)
Waveform 2
(see Notes C and D)
1.5 V
1.5 V
0.3 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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