SN64BCT241 [TI]
OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS; 八路缓冲器/驱动器，具有三态输出
| 型号： | SN64BCT241 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
DW OR N PACKAGE
(TOP VIEW)
State-of-the-Art BiCMOS Design
Substantially Reduces Standby Current
3-State Outputs Drive Bus Lines or
Buffer-Memory Address Registers
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
ESD Protection Exceeds 2000 V
Per MIL-STD-883 Method 3015
High-Impedance State During Power Up
and Power Down
Package Options Include Small-Outline
(DW) and Standard Plastic DIPs (N)
description
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state
memoryaddressdrivers, clockdrivers, andbus-orientedreceiversandtransmitters. WiththeSN64BCT240and
SN64BCT244, these devices provide the choice of selected combinations of inverting and noninverting outputs,
symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs.
The SN64BCT241 is characterized for operation from –40°C to 85°C and 0°C to 70°C.
FUNCTION TABLES
INPUTS
OUTPUT
1Y
1OE
1A
H
L
L
H
L
L
H
X
Z
INPUTS
OUTPUT
2Y
2OE
H
2A
H
H
L
H
L
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
†
logic symbol
logic diagram (positive logic)
1
1
1OE
EN
1OE
2
4
6
8
18
16
14
12
2
18
16
1A1
1Y1
1Y2
1Y3
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
4
1A2
6
14
12
1A3
19
2OE
EN
8
1A4
1Y4
11
13
15
17
9
7
5
3
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
19
2OE
11
9
7
5
3
†
2A1
2Y1
2Y2
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
13
2A2
15
2A3
2Y3
2Y4
17
2A4
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
Current into any output in the low state, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
O
CC
O
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative voltage rating may be exceeded if the input clamp current rating is observed.
2. ThepackagethermalimpedanceiscalculatedinacordanewithJESD51,exceptforthrough-holepackages,whichuseatracelength
of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
recommended operating conditions (see Note 3)
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
V
0.8
–18
–15
64
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
T
A
–40
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
= 4.5 V,
= 4.5 V
I = –18 mA
–1.2
V
IK
CC
I
I
I
I
I
= –3 mA
= –15 mA
= –3 mA
= 64 mA
= 2.7 V
2.4
2
3.3
3.1
OH
OH
OH
OH
CC
V
OH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
2.7
= 4.5 V,
0.42
0.55
50
V
OL
I
I
= 5.5 V,
V
µA
µA
OZH
O
O
= 5.5 V,
V
= 0.5 V
–50
50
OZL
= 0 to 2.3 V (power up)
= 1.8 V to 0 (power down)
= 5.5 V,
1OE at 0.8 V,
2OE at 2 V
I
V
O
= 2.7 V or 0.5 V,
µA
OZ
50
I
I
V = 7 V
I
0.1
20
mA
I
= 5.5 V,
V = 2.7 V
I
µA
IH
1OE or 2OE
Any A input
–1
I
V
= 5.5 V,
V = 0.5 V
mA
IL
CC
I
–1.6
–225
43
‡
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5 V,
V = 0
O
–100
mA
mA
mA
mA
pF
OS
Output open
Output open
Output open
23
53
4
CCL
CCH
CCZ
85
10
C
C
V = 2.5 V or 0.5 V
I
6
i
= 5 V,
V
O
= 2.5 V or 0.5 V
11
pF
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
V
C
= 5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
PARAMETER
TO
(OUTPUT)
UNIT
(INPUT)
T
A
= –40°C
to 85°C
T = 0°C
A
to 70°C
= 25°C
MIN
0.5
1
MAX
4.5
5.4
7.8
8.6
6.8
8.1
MIN MAX
MIN MAX
t
t
t
t
t
t
0.5
1
5.2
6.3
9.1
10
0.5
1
4.9
5.9
8.7
9.4
8.1
9.9
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
1
1
1
1OE or 2OE
1OE or 2OE
1
1
1
1
1
8.4
11
1
1
1
1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
7 V (t
, t
, O.C.)
PZL PLZ
Open
(all others)
S1
From Output
Under Test
Test
Point
C
L
R1
R1
(see Note A)
From Output
Under Test
Test
Point
C
L
R2
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3 V
0 V
1.5 V
1.5 V
3 V
Timing Input
(see Note B)
1.5 V
t
w
0 V
3 V
0 V
3 V
0 V
t
h
Low-Level
Pulse
t
su
1.5 V
1.5 V
Data Input
(see Note B)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level enable)
3 V
1.5 V
1.5 V
Input
(see Note B)
1.5 V
1.5 V
0 V
PHL
t
t
PZL
t
t
PLZ
t
PLH
3.5 V
In-Phase
Output
(see Note D)
V
OH
1.5 V
Waveform 1
(see Notes C and D)
1.5 V
1.5 V
1.5 V
t
V
OL
V
OL
0.3 V
t
PHZ
PLH
t
PHL
PZH
V
OH
V
OH
Out-of-Phase
Output
(see Note D)
Waveform 2
(see Notes C and D)
1.5 V
1.5 V
0.3 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
PDIP
Drawing
SN64BCT241DW
SN64BCT241N
OBSOLETE
OBSOLETE
DW
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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