SN6501-Q1 [TI]
适用于隔离电源的汽车类低噪声、350mA、410kHz 变压器驱动器;
| 型号： | SN6501-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于隔离电源的汽车类低噪声、350mA、410kHz 变压器驱动器 变压器 驱动 驱动器 |
| 文件： | 总36页 (文件大小：3309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN6501-Q1
ZHCSB64C –JUNE 2013 –REVISED MARCH 2021
SN6501-Q1 用于隔离电源的变压器驱动器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性
SN6501-Q1 是一款单片振荡器/电源驱动器，特别设计
用于隔离接口应用中的小外形尺寸隔离电源。该器件可
驱动来自 3.3V 或者 5V 直流 (DC) 电源的薄型中间抽
头的变压器初级。根据变压器的匝数比，变压器的次级
可被卷绕以提供任意隔离电压。
– 器件温度等级1：–40°C 至125°C 环境工作温
度范围
– 器件人体放电模型(HBM) 静电防护(ESD) 分类
等级H2
SN6501-Q1 包含一个振荡器，之后是一个栅极驱动电
路，此电路提供互补输出信号，用于驱动以地为基准的
N 沟道开关管。此内部逻辑电路确保了两个开关之间的
先开后和操作。
– 器件CDM ESD 分类等级C4B
• 提供功能安全
– 有助于进行功能安全系统设计的文档
• 用于小型变压器的推挽驱动器
• 3.3V 或5V 单电源
SN6501-Q1 采用小型 SOT-23 (5) 封装，其额定运行
温度范围为-40°C 至125°C。
• 初级侧高电流驱动：
– 5V 电源：350mA（最大值）
– 3.3V 电源：150mA（最大值）
• 整流输出上的低纹波允许使用小型输出电容器
• 小型5 引脚SOT-23 封装
器件信息
器件型号(1)
SN6501-Q1
封装尺寸（标称值）
封装
SOT-23 (5)
2.90mm x 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 用于控制器局域网(CAN)，RS-485，RS-422，
RS-232，串行外设接口(SPI)，I2C，低功耗局域网
(LAN) 的隔离接口电源
• 工业自动化
• 过程控制
• 医疗设备
简化版原理图
输出电压和效率与输出电流间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEF3
SN6501-Q1
ZHCSB64C –JUNE 2013 –REVISED MARCH 2021
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................27
11 Layout...........................................................................28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 Device Support....................................................... 29
12.2 Trademarks.............................................................29
12.3 静电放电警告.......................................................... 29
12.4 术语表..................................................................... 29
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Handling Ratings.........................................................4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Typical Characteristics................................................6
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (October 2020 ) to Revision C (March 2021)
Page
• Added a short-circuit protection note to SN6501 Drive Capability ...................................................................15
• Changed 方程式4 ........................................................................................................................................... 18
• Removed duplicate equation labeled as (5) in Revision B............................................................................... 18
• Added 17 line items to Recommended Isolation Transformers Optimized for SN6501 ...................................20
Changes from Revision A (September 2014) to Revision B (October 2020)
Page
• 添加了“功能安全”要点.................................................................................................................................... 1
Changes from Revision * (June 2013) to Revision A (September 2014)
Page
• 添加了引脚配置和功能部分、处理等级表、特性说明部分、器件功能模式、应用和实施部分、电源相关建议
部分、布局部分、器件和文档支持部分以及机械、封装和可订购信息部分......................................................1
• Changed 方程式10 ......................................................................................................................................... 18
• Changed 方程式11 ..........................................................................................................................................18
• Changed 表9-4, From: Wuerth-Elektronik / Midcom To: Wurth Electronics Midcom Inc..................................22
• Changed 图9-16 ............................................................................................................................................. 22
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5 Pin Configuration and Functions
D1
1
2
3
5
4
GND
GND
VCC
D2
图5-1. 5-Pin SOT-23 DBV Package Top View
表5-1. Pin Functions
DESCRIPTION
PIN
NUMBER
1
NAME
TYPE
D1
OD
Open Drain output 1. Connect this pin to one end of the transformer primary side.
Supply voltage input. Connect this pin to the center-tap of the transformer primary side. Buffer this
voltage with a 1 μF to 10 μF ceramic capacitor.
VCC
2
P
D2
3
OD
P
Open Drain output 2. Connect this pin to the other end of the transformer primary side.
Device ground. Connect this pin to board ground.
GND
4,5
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6
UNIT
V
VCC
Supply voltage
–0.3
VD1, VD2 Output switch voltage
14
V
ID1P, ID2P Peak output switch current
500
250
170
mA
mW
°C
PTOT
TJ
Continuous power dissipation
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under 节6.3 is not implied. Exposure to
absolute-maximum-rated conditions for extended periods affects device reliability.
6.2 Handling Ratings
MIN
–65
–2
MAX
150
2
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM) AEC-Q100 Classification Level H2, all pins
Charged device model (CDM) AEC-Q100 Classification Level C4B, all pins
kV
V
Electrostatic
discharge
V(ESD)
750
–750
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6.3 Recommended Operating Conditions
MIN TYP MAX UNIT
VCC
Supply voltage
3
0
0
5.5
11
V
VCC = 5 V ± 10%,
VCC = 3.3 V ± 10%
When connected to Transformer with
primary winding Center-tapped
VD1, VD2 Output switch voltage
V
7.2
VD1, VD2 Swing ≥3.8 V,
see 图6-32 for typical characteristics
VCC = 5 V ± 10%
350
D1 and D2 output switch
ID1, ID2
mA
°C
current –Primary-side
VD1, VD2 Swing ≥2.5 V,
see 图6-31 for typical characteristics
VCC = 3.3 V ± 10%
150
125
TA
Ambient temperature
–40
6.4 Thermal Information
SN6501
DBV 5-PINS
208.3
87.1
THERMAL METRIC(1)
UNIT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
θJA
θJCtop
θJB
Junction-to-board thermal resistance
40.4
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.2
ψJT
39.7
ψJB
N/A
θJCbot
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX UNIT
3
VCC = 3.3 V ± 10%, See 图7-4
VCC = 5 V ± 10%, See 图7-4
VCC = 3.3 V ± 10%, no load
VCC = 5 V ± 10%, no load
VCC = 2.4 V, See 图7-4
RON
Switch-on resistance
Ω
0.6
150
300
300
360
410
2
400
µA
700
ICC
fST
Average supply current(1)
Startup frequency
kHz
250
300
495
kHz
620
VCC = 3.3 V ± 10%, See 图7-4
VCC = 5 V ± 10%, See 图7-4
fSW
D1, D2 Switching frequency
(1) Average supply current is the current used by SN6501 only. It does not include load current.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
70
MAX UNIT
tr-D
D1, D2 output rise time
ns
VCC = 3.3 V ± 10%, See 图7-4
VCC = 5 V ± 10%, See 图7-4
VCC = 3.3 V ± 10%, See 图7-4
VCC = 5 V ± 10%, See 图7-4
VCC = 3.3 V ± 10%, See 图7-4
VCC = 5 V ± 10%, See 图7-4
80
tf-D
D1, D2 output fall time
Break-before-make time
110
60
ns
ns
tBBM
150
50
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6.7 Typical Characteristics
TP1 Curves are measured with the Circuit in 图 7-1; whereas, TP1 and TP2 Curves are measured with Circuit in
图7-3 (TA = 25°C unless otherwise noted). See 表9-3 for Transformer Specifications.
90
80
70
60
50
40
30
20
10
0
TP1
5
4
3
2
1
0
TP1
T1 = 760390011 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
T1 = 760390011 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-1. Output Voltage vs Load Current
图6-2. Efficiency vs Load Current
6
90
80
TP1
5
TP1
70
60
50
40
30
20
10
0
4
3
2
T1 = 760390012 (2.5kV)
VIN = 5V, VOUT = 5V
1
T1 = 760390012 (2.5kV)
VIN = 5V, VOUT = 5V
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-3. Output Voltage vs. Load Current
图6-4. Efficiency vs Load Current
6
90
TP1
80
70
60
50
40
30
20
10
0
TP1
5
4
3
2
T1 = 760390013 (2.5kV)
VIN = 3.3V, VOUT = 5V
1
T1 = 760390013 (2.5kV)
VIN = 3.3V, VOUT = 5V
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-6. Efficiency vs Load Current
图6-5. Output Voltage vs Load Current
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90
80
70
60
50
40
30
20
10
0
TP1
TP2
5
4
3
2
1
0
TP1
TP2
T1 = 760390014 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
T1 = 760390014 (2.5kV)
VIN = 3.3V, VOUT = 3.3V
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-7. Output Voltage vs Load Current
图6-8. Efficiency vs Load Current
8
7
90
TP1
80
TP1
70
60
50
40
30
20
10
0
TP2
6
5
TP2
4
3
2
T1 = 760390014 (2.5kV)
VIN = 5V, VOUT = 5V
T1 = 760390014 (2.5kV)
VIN = 5V, VOUT = 5V
1
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-10. Efficiency vs Load Current
图6-9. Output Voltage vs Load Current
7
TP1
6
5
TP2
4
3
2
T1 = 760390015 (2.5kV)
VIN = 3.3V, VOUT = 5V
1
0
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
图6-11. Output Voltage vs Load Current
图6-12. Efficiency vs Load Current
90
80
70
60
50
40
30
20
10
0
TP1
5
TP2
4
3
2
1
0
TP1
TP2
T1 = 750313710 (2.5kV)
VIN = 5V, VOUT = 3.3V
T1 = 750313710 (2.5kV)
VIN = 5V, VOUT = 3.3V
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-13. Output Voltage vs Load Current
图6-14. Efficiency vs Load Current
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6
5
90
80
70
60
50
40
30
20
10
0
TP1
4
TP1
3
2
T1 = 750313734 (5kV)
VIN = 3.3V, VOUT = 3.3V
1
T1 = 750313734 (5kV)
VIN = 3.3V, VOUT = 3.3V
0
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
0
10 20 30 40 50 60 70 80 90
100
图6-15. Output Voltage vs Load Current
图6-16. Efficiency vs Load Current
6
90
80
TP1
5
TP1
70
60
50
40
30
20
10
0
4
3
2
T1 = 750313734 (5kV)
VIN = 5V, VOUT = 5V
1
T1 = 750313734 (5kV)
VIN = 5V, VOUT = 5V
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-18. Efficiency vs Load Current
图6-17. Output Voltage vs Load Current
图6-19. Output Voltage vs Load Current
图6-20. Efficiency vs Load Current
6
90
TP1
TP2
80
70
5
TP1
4
60
50
40
30
3
2
1
0
TP2
20
T1 = 750313638 (5kV)
VIN = 3.3V, VOUT = 3.3V
T1 = 750313638 (5kV)
VIN = 3.3V, VOUT = 3.3V
10
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-21. Output Voltage vs Load Current
图6-22. Efficiency vs Load Current
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8
7
6
5
4
3
2
1
0
90
80
70
60
50
40
30
20
10
0
TP1
TP1
TP2
TP2
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 5V
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 5V
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-23. Output Voltage vs Load Current
图6-24. Efficiency vs Load Current
8
7
90
80
70
60
50
40
30
20
10
0
TP1
TP2
TP1
6
5
TP2
4
3
2
T1 = 750313626 (5kV)
VIN = 3.3V, VOUT = 5V
T1 = 750313626 (5kV)
VIN = 3.3V, VOUT = 5V
1
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
ILOAD - mA
图6-25. Output Voltage vs Load Current
图6-26. Efficiency vs Load Current
6
90
80
70
60
50
40
30
20
10
0
TP1
5
4
TP2
TP1
3
2
1
0
TP2
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 3.3V
T1 = 750313638 (5kV)
VIN = 5V, VOUT = 3.3V
0
10 20 30 40 50 60 70 80 90 100
ILOAD - mA
0
10 20 30 40 50 60 70 80 90 100
图6-27. Output Voltage vs Load Current
图6-28. Efficiency vs Load Current
350
460
V
= 5V
300
250
200
150
100
50
440
CC
V
CC
= 5V
420
400
380
360
340
320
V
= 3.3V
CC
V
= 3.3V
CC
0
-55 -35 -15
5
25 45 65 85 105 125
-55 -35 -15
5
25 45 65 85 105 125
TA - Free Air Temperature - o
C
TA - Free Air Temperature - o
C
图6-29. Average Supply Current vs Free-Air
图6-30. D1, D2 Switching Frequency vs Free-Air
Temperature
Temperature
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3.30
3.25
5.00
4.95
4.90
4.85
4.80
4.75
4.70
4.65
4.60
4.55
V
CC
= 5V
V
CC
= 3.3V
3.20
3.15
3.10
3.05
3.00
0
50
100
150
200
0
100
200
300
400
ID1, ID2 - Switching Current - mA
ID1, ID2 - Switching Current - mA
图6-31. D1, D2 Primary-Side Output Switch Voltage
图6-32. D1, D2 Primary-Side Output Switch Voltage
Swing vs Current
Swing vs Current
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7 Parameter Measurement Information
7.1
图7-2. Timing Diagram
图7-1. Measurement Circuit for Unregulated
Output (TP1)
图7-3. Measurement Circuit for regulated Output (TP1 and TP2)
图7-4. Test Circuit For RON, FSW, FSt, Tr-D, Tf-D, TBBM
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8 Detailed Description
8.1 Overview
The SN6501-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters
utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals with a 50% duty cycle. A subsequent break-before-make logic inserts a dead-time
between the high-pulses of the two signals. The resulting output signals, present the gate-drive signals for the
output transistors. As shown in the functional block diagram, before either one of the gates can assume logic
high, there must be a short time period during which both signals are low and both transistors are high-
impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of
the primary.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Push-Pull Converter
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary
(see 图8-1).
CR
CR
1
1
V
V
OUT
OUT
C
C
R
R
L
L
V
V
IN
IN
CR
CR
2
2
Q
Q
Q
Q
1
2
1
2
图8-1. Switching Cycles of a Push-Pull Converter
When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative
voltage potential at the lower primary end with regards to the VIN potential at the center-tap.
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive
with regards to the center-tap in order to maintain the previously established current flow through Q2, which now
has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a
voltage potential at the open end of the primary of 2×VIN with regards to ground.
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Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The
positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current
starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load
impedance RL back to the center-tap.
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.
Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2
is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,
charging the capacitor and returning through the load to the center-tap.
8.3.2 Core Magnetization
图 8-2 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as
the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2
conducts the flux is pulled back from A’to A. The difference in flux and thus in flux density is proportional to the
product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈VP × tON
.
B
V
V
P
IN
A’
H
R
V
DS
DS
A
V
= V +V
P DS
IN
图8-2. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)
This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.
If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from
the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the
transformer slowly creeps toward the saturation region.
Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of the
SN6501 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged
current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher
resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is the
difference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS
,
VP is gradually reduced and V-t balance restored.
8.4 Device Functional Modes
The functional modes of the SN6501 are divided into start-up, operating, and off-mode.
8.4.1 Start-Up Mode
When the supply voltage at Vcc ramps up to 2.4V typical, the internal oscillator starts operating at a start
frequency of 300 kHz. The output stage begins switching but the amplitude of the drain signals at D1 and D2 has
not reached its full maximum yet.
8.4.2 Operating Mode
When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations
over supply voltage and operating temperature can vary the switching frequencies at D1 and D2 between 250
kHz and 495 kHz for VCC = 3.3 V ±10%, and between 300 kHz and 620 kHz for VCC = 5 V ±10%.
8.4.3 Off-Mode
The SN6501 is deactivated by reducing VCC to 0 V. In this state both drain outputs, D1 and D2, are high-
impedance.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN6501-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC-DC converters
utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
图9-1. SN6501-Q1 Block Diagram
The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gate-
drive signals for the output transistors Q1 and Q2. As shown in 图9-2, before either one of the gates can assume
logic high, there must be a short time period during which both signals are low and both transistors are high-
impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of
the primary.
fOSC
S
S
G1
G2
Q1
Q2
图9-2. Detailed Output Signal Waveforms
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9.2 Typical Application
图9-3. Typical Application Schematic (SN6501-Q1)
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1 as design parameters.
表9-1. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
3.3 V ± 3%
5 V
Maximum load current
100 mA
9.2.2 Detailed Design Procedure
The following recommendations on components selection focus on the design of an efficient push-pull converter
with high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter
output drops significantly over a wide range in load current. The characteristic curve in 图 6-11 for example
shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a transceiver’s
supply range. Therefore, in order to provide a stable, load independent supply while maintaining maximum
possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised.
The final converter circuit is shown in 图 9-7. The measured VOUT and efficiency characteristics for the regulated
and unregulated outputs are shown in 图6-1 to 图6-28.
9.2.2.1 SN6501 Drive Capability
The SN6501 transformer driver is designed for low-power push-pull converters with input and output voltages in
the range of 3 V to 5.5 V. While converter designs with higher output voltages are possible, care must be taken
that higher turns ratios don’t lead to primary currents that exceed the SN6501 specified current limits.
Unlike SN6505 devices, SN6501 does not have soft-start, internal current limit, or thermal shutdown (TSD)
features. Therefore, unregulated large currents exceeding device absolute maximum current ratings may
damage the device or affect its long-term reliability. In addition, high capacitive loads at the isolated power
supply output may appear as short circuits to SN6501 during power-up and may exceed the device's maximum
current ratings. When using SN6501, it is recommended to incorporate LDOs with low short-circuit current limits
or soft-start features to ensure excessive current is not drawn from SN6501.
9.2.2.2 LDO Selection
The minimum requirements for a suitable low dropout regulator are:
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• Its current drive capability should slightly exceed the specified load current of the application to prevent the
LDO from dropping out of regulation. Therefore for a load current of 100 mA, choose a 100 mA to 150 mA
LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout
voltages that will reduce overall converter efficiency.
• The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain
efficiency. For a low-cost 150 mA LDO, a VDO of 150 mV at 100 mA is common. Be aware however, that this
lower value is usually specified at room temperature and can increase by a factor of 2 over temperature,
which in turn will raise the required minimum input voltage.
• The required minimum input voltage preventing the regulator from dropping out of line regulation is given
with:
VI-min = VDO-max + VO-max
(1)
This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO
and VO specified in the LDO data sheet for rated output current (i.e., 100 mA) and add them together. Also
specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than
VI-min. If it is not, the LDO will lose line-regulation and any variations at the input will pass straight through to
the output. Hence below VI-min the output voltage will follow the input and the regulator behaves like a simple
conductor.
• The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this
condition there is no secondary current reflected back to the primary, thus making the voltage drop across
RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point the
secondary reaches its maximum voltage of
VS-max = VIN-max × n
(2)
with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the
LDO from damage the maximum regulator input voltage must be higher than VS-max. 表 9-2 lists the maximum
secondary voltages for various turns ratios commonly applied in push-pull converters with 100 mA output drive.
表9-2. Required Maximum LDO Input Voltages for Various Push-Pull Configurations
PUSH-PULL CONVERTER
LDO
VI-max [V]
6 to 10
10
CONFIGURATION
3.3 VIN to 3.3 VOUT
3.3 VIN to 5 VOUT
5 VIN to 5 VOUT
VIN-max [V]
TURNS-RATIO
1.5 ± 3%
VS-max [V]
5.6
3.6
3.6
5.5
2.2 ± 3%
8.2
1.5 ± 3%
8.5
10
9.2.2.3 Diode Selection
A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output
as possible. When used in high-frequency switching applications, such as the SN6501 however, the diode must
also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly
recommended in push-pull converter designs. A good choice for low-volt applications and ambient temperatures
of up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mA
forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher
DC blocking voltage of 30 V.
Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the above
Schottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifier
output voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such as
RB168M-40.
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1
1
TJ = 125°C
25°C
0°C
-40°C
75°C
-25°C
TJ = 100°C
25°C
75°C
0.1
0.1
0.01
0.01
0.2
0.3
0.4
0.5
0.1
0.2
0.3
0.4
0.5
Forward Voltage, VF - V
Forward Voltage, VF - V
图9-4. Diode Forward Characteristics for MBR0520L (Left) and MBR0530 (Right)
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9.2.2.4 Capacitor Selection
The capacitors in the converter circuit in 图9-7 are multi-layer ceramic chip (MLCC) capacitors.
As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF.
The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast
switching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with a
dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4-
layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the
supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a
reference plane or to the primary center-tap.
The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 1 μF to 10 μF.
The small capacitor at the regulator input is not necessarily required. However, good analog design practice
suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise
rejection.
The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The
choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in
most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.
9.2.2.5 Transformer Selection
9.2.2.5.1 V-t Product Calculation
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied
by the SN6501. The maximum voltage delivered by the SN6501 is the nominal converter input plus 10%. The
maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified
input voltage. Therefore, the transformer’s minimum V-t product is determined through:
T
V
IN-max
max
Vt
³ V
´
=
min
IN-max
2
2 ´ f
min
(3)
Inserting the numeric values from the data sheet into the equation above yields the minimum V-t products of
3.6 V
Vtmin
³
= 7.2 Vμs
for 3.3 V, and
2 ´ 250 kHz
5.5 V
Vtmin
³
= 9.1Vμs for 5 V applications.
2 ´ 300 kHz
(4)
Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical
footprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as
little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only.
While Vt-wise all of these transformers can be driven by the SN6501, other important factors such as isolation
voltage, transformer wattage, and turns ratio must be considered before making the final decision.
9.2.2.5.2 Turns Ratio Estimate
Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that the
transformer choosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer
websites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pull
converter to operate flawlessly over the specified current and temperature range. This minimum transformation
ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction
factor that takes the transformer’s typical efficiency of 97% into account.
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vs-min
nmin = 1.031ì
vp-min
(5)
VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still
provide sufficient input voltage for the regulator to remain in regulation. From the LDO SELECTION section, this
minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:
VS-min = VF-max + VDO-max + VO-max
(6)
V
F
V
DO
V
V
O
I
V
R
S
L
V
V
IN
P
V
DS
R
Q
DS
图9-5. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min
Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible
drain-source voltage of the SN6501, VDS-max, from the minimum converter input voltage VIN-min
:
VP-min = VIN-min –VDS-max
(7)
VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the
SN6501 data sheet:
VDS-max = RDS-max × IDmax
(8)
Then inserting 方程式8 into 方程式7 yields:
VP-min = VIN-min - RDS-max x IDmax
(9)
and inserting 方程式9 and 方程式6 into 方程式5 provides the minimum turns ration with:
VF-max + VDO-max + VO-max
nmin = 1.031 ´
VIN-min - RDS-max ´ ID-max
(10)
Example:
For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO TPS76350, the data
sheet values taken for a load current of 100 mA and a maximum temperature of 85°C are VF-max = 0.2 V,
VDO-max = 0.2 V, and VO-max = 5.175 V.
Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2%
accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at
3.3 V are taken from the SN6501 data sheet with RDS-max = 3 Ωand ID-max = 150 mA.
Inserting the values above into 方程式10 yields a minimum turns ratio of:
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0.2V + 0.2V + 5.175 V
3.234 V - 3 Ω ´ 150 mA
nmin = 1.031 ´
= 2
(11)
Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3
with a common tolerance of ±3%.
9.2.2.5.3 Recommended Transformers
Depending on the application, use the minimum configuration in 图9-6 or standard configuration in 图9-7.
图9-7. Regulated Output for Stable Supplies and
图9-6. Unregulated Output for Low-Current Loads
High Current Loads
With Wide Supply Range
The Wurth Electronics Midcom isolation transformers in 表 9-3 are optimized designs for the SN6501, providing
high efficiency and small form factor at low-cost.
The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents.
These applications operate without LDO, thus achieving further cost-reduction.
表9-3. Recommended Isolation Transformers Optimized for SN6501
Turns
Ratio
V x T
(Vμs)
Isolation
(VRMS
Dimensions
(mm)
Application
LDO
Figures
Order No.
Manufacturer
)
图6-1
图6-2
1:1.1 ±2%
1:1.1 ±2%
1:1.7 ±2%
7
760390011
3.3 V →3.3 V
图6-3
图6-4
No
Yes
No
760390012
760390013
5 V →5 V
图6-5
图6-6
3.3 V →5 V
图6-7
图6-8
图6-9
图6-10
2500
6.73 x 10.05 x 4.19
3.3 V →3.3 V
5 V →5 V
1:1.3 ±2%
11
760390014
图6-11
图6-12
1:2.1 ±2%
1.23:1 ±2%
1:1.1 ±2%
1:1.1 ±2%
1:1.7 ±2%
760390015
750313710
750313734
750313734
750313769
3.3 V →5 V
5 V →3.3 V
3.3 V →3.3 V
5 V →5 V
图6-13
图6-14
Wurth
Electronics/
Midcom
图6-15
图6-16
图6-17
图6-18
图6-19
图6-20
3.3 V →5 V
图6-21
图6-22
图6-23
图6-24
11
5000
9.14 x 12.7 x 7.37
3.3 V →3.3 V
5 V →5 V
1:1.3 ±2%
750313638
Yes
图6-25
图6-26
1:2.1 ±2%
1.3:1 ±2%
750313626
750313638
3.3 V →5 V
5 V →3.3 V
图6-27
图6-28
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表9-3. Recommended Isolation Transformers Optimized for SN6501 (continued)
Turns
Ratio
V x T
(Vμs)
Isolation
(VRMS
Dimensions
(mm)
Application
LDO
Figures
Order No.
Manufacturer
)
1:1.1 ±2%
1:1.1 ±2%
EPC3804G-L
7
No
No
1500
N/A
N/A
3.3 V →3.3V
EPC3805G-L
EPC3806G-L
11
11
5V →5V
No / Yes
3.3V →5V
1:1.7 ±2%
1:1.3 ±2%
N/A
N/A
7.1 x 11 x 4.19
3.3V →3.3V
PCA Electronics
Yes
2500
3.3V →3.3V
5V →5V
11
EPC3807G-L
1:2 ±2%
N/A
N/A
EPC3808G-L
EPC3809G-L
11
Yes
No
3.3V →5V
5V →5V
1:1.1 ±2%
4.3
8.6 x 12.5 x 5.97
3.3V →3.3V
5V →5V
1:1
No
N/A
HCTSM80101AAL
1:2
2:1
N/A
N/A
HCTSM80102AAL
HCTSM80201AAL
Yes
Yes
Yes
3.3V →5V
5V →1.8V
3.3V →3.3V
5V →5V
3:4
N/A
HCTSM80304BAL
N/A
N/A
N/A
N/A
N/A
N/A
N/A
HCTSM80305BAL
HCTSM80308BAL
HCTSM80403AAL
HCTSM80803AAL
HCTSM80809AAL
HCTSM80910BAL
HCTSM81017CAL
3:5
3:8
No
Yes
No
3.3V →5V
5V →12V
5V →3.3V
5V →1.8V
11
4200
10.8 x 15.2 x 6.6
Bourns
4:3
8:3
No
8:9
3.3V →3.3V
5V →5V
No
9:10
10:17
Yes
3.3V →5V
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9.2.3 Application Curve
See 表9-3 for application curves.
9.2.4 Higher Output Voltage Designs
The SN6501 can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of
up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to
5, requires different rectifier topologies to achieve high output voltages. 图 9-8 to 图 9-11 show some of these
topologies together with their respective open-circuit output voltages.
n
n
V
OUT+
= n·V
IN
V
V =2n·V
OUT IN
V
IN
IN
图9-9. Bridge Rectifier Without Center-Tapped
V
OUT-
= n·V
IN
Secondary Performs Voltage Doubling
图9-8. Bridge Rectifier With Center-Tapped
Secondary Enables Bipolar Outputs
V
OUT+
=2n·V
IN
V
=4n·V
IN
n
OUT
n
V
V
IN
IN
V
OUT-
=2n·V
IN
图9-10. Half-Wave Rectifier Without Center-Tapped
Secondary Performs Voltage Doubling, Centered
Ground Provides Bipolar Outputs
图9-11. Half-Wave Rectifier Without Centered
Ground and Center-Tapped Secondary Performs
Voltage Doubling Twice, Hence Quadrupling VIN
9.2.5 Application Circuits
The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated
micro-controller supply. For 5 V input voltages requiring different turn ratios refer to the transformer
manufacturers and their websites listed in 表9-4.
表9-4. Transformer Manufacturers
Coilcraft Inc.
http://www.coilcraft.com
Halo-Electronics Inc.
Murata Power Solutions
Wurth Electronics Midcom Inc
http://www.haloelectronics.com
http://www.murata-ps.com
http://www.midcom-inc.com
Certain components might not possess AEC-Q100 Q1 qualification. For more detailed information on qualified
components for automotive applications please refer to the automotive web page: http://www.ti.com/lsds/ti/apps/
automotive/applications.page.
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图9-12. Isolated RS-485 Interface
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图9-13. Isolated Can Interface
图9-14. Isolated RS-232 Interface
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图9-15. Isolated Digital Input Module
图9-16. Isolated SPI Interface for an Analog Input Module With 16 Inputs
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图9-17. Isolated I2C Interface for an Analog Data Acquisition System With 4 Inputs and 4 Outputs
V
S
0.1 ꢀF
3.3 V
2
MBR0520L
1:1.33
3.3VISO
10 ꢀF
3
1
1
3
5
2
V
CC
D2
D1
IN
OUT
GND
TPS76333
SN6501
4.7 ꢀF 0.1 ꢀF
EN
GND
4, 5
10 ꢀF
MBR0520L
0.1 ꢀF
0.1 ꢀF
20 ꢁ
ISO-BARRIER
0.1 ꢀF
LOOP+
15
3
0.1 ꢀF
0.1 ꢀF
VA
VD
10
8
16
LOW
BASE
OUT
1
8
0.1 ꢀF 1 ꢀF
2
ERRLVL
V
V
CC2
CC1
DAC161P997
DV
CC
7
5
4
5
22 ꢁ
OUTA
INB
INA
DBACK
DIN
11
12
2
3
XOUT
P3.0
P3.1
ISO7421
9
MSP430
G2132
6
OUTB
6
LOOPœ
C1 C2 C3 COMA COMD
XIN
GND1
GND2
5
14 13 12
1
2
DV
SS
3 × 22 nF
4
4
图9-18. Isolated 4-20 mA Current Loop
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ZHCSB64C –JUNE 2013 –REVISED MARCH 2021
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10 Power Supply Recommendations
10.1
The device is designed to operate from an input voltage supply range between 3.3 V and 5 V nominal. This input
supply must be regulated within ±10%. If the input supply is located more than a few inches from the SN6501 a
0.1μF by-pass capacitor should be connected as possible to the device VCC pin, and a 10 μF capacitor should
be connected close to the transformer center-tap pin.
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SN6501-Q1
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11 Layout
11.1 Layout Guidelines
• The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum
and a X5R or X7R dielectric.
• The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area
formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See 图11-1 for a PCB layout
example.
• The connections between the device D1 and D2 pins and the transformer primary endings, and the
connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum
trace inductance.
• •The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-
ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The
capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
• The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
• The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
• The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range
to maximize efficiency.
• The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum
and a X5R or X7R dielectric.
11.2 Layout Example
图11-1. Layout Example of a 2-Layer Board (SN6501)
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 Trademarks
所有商标均为其各自所有者的财产。
12.3 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.4 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN6501-Q1
PACKAGE OPTION ADDENDUM
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27-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN6501QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SBRQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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27-Feb-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN6501QDBVRQ1
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Feb-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
SN6501QDBVRQ1
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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