SN6505B-Q1 [TI]
适用于隔离电源的汽车类低噪声、1A、420kHz 变压器驱动器;
| 型号： | SN6505B-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于隔离电源的汽车类低噪声、1A、420kHz 变压器驱动器 变压器 驱动 驱动器 |
| 文件： | 总40页 (文件大小：1751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
适用于隔离电源的SN6505x-Q1 低噪声1A 变压器驱动器
幅降低辐射的应用；而SN6505B-Q1 和SN6505D-Q1
有420kHz 内部振荡，适用于需要更高效率和更小变压
器尺寸的应用。SN6505x-Q1 采用小型 6 引脚
SOT23/DBV 封装。该器件的运行温度范围为-40°C 至
125°C。
1 特性
• 符合面向汽车应用的AEC-Q100（1 级）标准
– 器件温度等级1：–40°C 至+125°C，TA
• 提供功能安全
– 可提供用于功能安全系统设计的文档：
SN6505A-Q1，SN6505B-Q1，SN6505D-Q1
• 用于变压器的推挽式驱动器
• 宽输入电压范围：2.25V 至5.5V
• 高输出驱动：5V 电源下为1A
• 低RON，4.5V 电源时的最大值为0.25Ω
• 降低了传导和辐射EMI
器件信息
器件型号(1)
SN6505A-Q1
封装尺寸（标称值）
封装
SN6505B-Q1
SN6505D-Q1
2.90mm × 1.60mm
SOT23（6 引脚）
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
• 扩频时钟
SN6505
• 精密内部振荡器选项：160kHz (SN6505A-Q1) 和
420kHz (SN6505B-Q1 和SN6505D-Q1)
• 通过外部时钟输入同步多个器件
• 转换率控制
VOUT
4
3
2
1
GND
EN
D2
VCC
Enable
5
6
V
CC
Ext Clock
CLK
D1
• 1.7A 限流
10µF 0.1µF
• 低关断电流：< 1μA
• 热关断
10µF
• 小型6 引脚SOT23 (DBV) 封装
• 启用软启动（SN6505A-Q1 和SN6505B-Q1）可减
小浪涌电流，禁用软启动(SN6505D-Q1) 可实现快
速启动
Copyright © 2016, Texas Instruments Incorporated
简化版原理图
2 应用
• 用于以下应用的隔离式电源：
– 牵引逆变器和电机控制
– 直流/直流转换器
– 电池管理系统(BMS)
– 车载充电器(OBC)
3 说明
SN6505x-Q1 是一款低噪声、低 EMI 的推挽式变压器
驱动器，专为小型隔离式电源而设计。该器件通过
2.25V 至5V 的直流电源来驱动薄型、
中间抽头的变压器。通过输出开关电压的转换速率控制
和扩频时钟 (SSC) 可实现非常低的噪声和 EMI。
SN6505x-Q1 包含一个振荡器，然后是一个栅极驱动
器电路，此电路提供补偿输出信号以驱动接地参考 N
通道电源开关。该器件包含两个 1A 电源 MOSFET 开
关，以确保在重负载条件下正常启动。开关时钟也可由
外部提供，以准确放置开关谐波或者在与多个变压器驱
动器搭配工作时。内部保护特性包括1.7 A 限流、欠压
锁定、热关断和先断后合电路。SN6505A-Q1 和
SN6505B-Q1 具有软启动功能，可防止大负载电容器
在上电过程中出现高浪涌电流。对于需要快速输出启动
的应用， SN6505D-Q1 中禁用了软启动功能。
SN6505A-Q1 有 160kHz 内部振荡器，适用于需要大
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................17
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 19
10 Power Supply Recommendations..............................29
11 Layout...........................................................................30
11.1 Layout Guidelines................................................... 30
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................31
12.1 Device Support....................................................... 31
12.2 Documentation Support.......................................... 31
12.3 Related Links.......................................................... 31
12.4 接收文档更新通知................................................... 31
12.5 支持资源..................................................................31
12.6 Trademarks.............................................................31
12.7 静电放电警告.......................................................... 31
12.8 术语表..................................................................... 31
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................6
6.7 Typical Characteristics, SN6505A-Q1 ........................7
6.8 Typical Characteristics, SN6505B-Q1 or
SN6505D-Q1 ................................................................9
7 Parameter Measurement Information..........................13
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................15
Information.................................................................... 32
4 Revision History
Changes from Revision C (August 2019) to Revision D (October 2020)
Page
• 添加了“功能安全”要点....................................................................................................................................1
Changes from Revision B (July 2019) to Revision C (August 2019)
Page
• Added UNIT V to EN, CLK Voltage specification in Absolute Maximum Ratings table...................................4
• Changed '<' or 'less than' sign to '≤' or 'less than or equal' sign in VCC range description at multiple location
for better clarity...................................................................................................................................................5
• Added Revision History comments for data sheet Revision B........................................................................ 6
• Added 'Power up time' or tPWRUP specification for two VCC TEST CONDITIONS............................................. 6
Changes from Revision A (April 2019) to Revision B (July 2019)
Page
• Split 'Soft-start time' or tSS specification for SN6505A-Q1 and SN6505B-Q1.................................................... 6
Changes from Revision * (November 2018) to Revision A (April 2019)
Page
• 将器件状态更改为“量产数据”.........................................................................................................................1
• Added DA2303-AL transformer to 表9-3 table.................................................................................................25
• Added DA2304-AL transformer to 表9-3 table.................................................................................................25
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Product Folder Links: SN6505A-Q1 SN6505B-Q1 SN6505D-Q1
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
5 Pin Configuration and Functions
6
5
4
D1
CLK
EN
1
2
3
VCC
GND
D2
图5-1. DBV Package SOT-23 (6 Pin) Top View
表5-1. Pin Functions
PIN
NO.
DESCRIPTION
NAME
TYPE
Open drain output of the first power MOSFETs. Typically connected to the outer terminals of the
center tap transformer. Because large currents flow through these pins, their external traces
should be kept short.
D1
1
2
3
O
This is the device supply pin. It should be bypassed with a 4.7 μF or greater, low ESR capacitor.
When VCC ≤2.25 V, an internal undervoltage lockout circuit trips and turns both outputs off.
VCC
D2
P
Open drain output of the second power MOSFETs. Typically connected to the outer terminals of
the center tap transformer. Because large currents flow through these pins, their external traces
should be kept short.
O
GND is connected to the source of the power MOSFET switches via an internal sense circuit.
Because large currents flow through it, the GND terminals must be connected to a low-inductance
quality ground plane.
GND
4
P
The EN pin turns the device on or off. Grounding or leaving this pin floating disables all internal
EN
5
6
I
I
circuitry. If unused this pin should be tied directly to VCC
.
This pin is used to run the device with external clock. Internally it is pulled down to GND. If valid
clock is not detected on this pin, the device shifts automatically to internal clock.
CLK
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Product Folder Links: SN6505A-Q1 SN6505B-Q1 SN6505D-Q1
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1). All typical values are at TA = 25°C, VCC = 5 V.
MIN
–0.5
–0.5
MAX
UNIT
V
Supply voltage (2)
VCC
6
Voltage
EN, CLK
D1, D2
VCC + 0.5(3)
V
Output switch voltage
Peak output switch current
Junction temperature, TJ
Storage temperature range, Tstg
16
2.4
V
I(D1)Pk, I(D2)Pk
A
-40
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under 节6.3 is not implied. Exposure to
absolute-maximum-rated conditions for extended periods affects device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND) and are peak voltage values.
(3) Maximum voltage must not exceed 6V. A strongly driven EN or CLK input signal can weakly power the floating VCC via an internal
protection diode and cause undetermined output.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 3A
±6000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
TYP
MAX
5.5
UNIT
VCC
Supply voltage
2.25
V
0.75
1
2.25 V ≤VCC ≤2.8 V
2.8 V < VCC ≤5.5 V
ID1, ID2
TA
Output switch current - Primary side
Ambient temperature
A
125
°C
–40
6.4 Thermal Information
SN6505x-Q1
DBV (SOT-23)
6 PINS
137.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
57.7
Junction-to-board thermal resistance
46.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
13.4
ψJT
44.9
ψJB
RθJC(bottom)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Product Folder Links: SN6505A-Q1 SN6505B-Q1 SN6505D-Q1
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
6.5 Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE SUPPLY
Supply Current (2.8 V ≤VCC ≤5.5 V)
(SN6505A-Q1)
1
1.4
mA
mA
RL = 50 Ω
RL = 50 Ω
I(Vcc)
Supply Current (2.8 V ≤VCC ≤5.5 V)
(SN6505B-Q1 and SN6505D-Q1)
1.56
2.3
20
IIH
Leakage Current on EN and CLK pin
VCC current for EN = 0
EN / CLK = VCC
10
µA
µA
IDIS
0.1
ILKG(D1)
ILKG(D2)
Leakage Current on D1, D2 for EN=0
Voltage of D1, D2 = VCC
0.1
µA
VCC+ (UVLO)
VCC- (UVLO)
Positive-going UVLO threshold
Negative-going UVLO threshold
2.25
0.7
V
V
1.7
0.3
VHYS (UVLO1) UVLO threshold hysteresis
0.3
0.2
V
VIN(ON)
VIN(OFF)
VIN(HYS)
CLK
EN, CLK pin logic high threshold
EN, CLK pin logic low threshold
EN, CLK pin threshold hysteresis
VCC
VCC
VCC
D1, D2 average switching Frequency (SN6505A-
Q1)
138
363
100
100
160
424
203
517
Khz
kHz
kHz
kHz
RL = 50 Ωto VCC; Refer to 图7-3
RL = 50 Ωto VCC; Refer to 图7-3.
FSW
D1, D2 average switching Frequency (SN6505B-
Q1 and SN6505D-Q1)
External clock frequency on CLK pin (SN6505A-
Q1)
600
F(EXT)
External clock frequency on CLK pin (SN6505B-
Q1 and SN6505D-Q1)
1600
OUTPUT STAGE
DMM
Average ON time mismatch between D1 and D2
0%
0.16
0.19
0.21
RL = 50 Ω
VCC = 4.5 V, ID1, ID2 = 1 A
VCC = 2.8 V, ID1, ID2 = 1 A
VCC = 2.25 V, ID1, ID2 = 0.5 A
0.25
0.31
0.45
Ω
Ω
Ω
R(ON)
Output switch on resistance
Voltage slew rates on D1 and D2 for SN6505A-
Q1
V(SLEW)
48
11
V/µs
A/µs
V/µs
A/µs
RL = 50 Ωto VCC; Refer to 图7-3
RL = 5 Ωthrough transformer;
Refer to 图7-4
I(SLEW)
Current slew rates at D1 and D2 for SN6505A-Q1
Voltage slew rates on D1 and D2 for SN6505B-
Q1 and SN6505D-Q1
V(SLEWHF)
152
RL = 50 Ωto VCC; Refer to 图7-3
Current slew rates at D1 and D2 for SN6505B-Q1 RL = 5 Ωthrough transformer;
and SN6505D-Q1
I(SLEWHF)
41
Refer to 图7-4
1.42
0.65
1.75
2.15
1.85
A
A
Current clamp limit (2.8 V < VCC ≤5.5V )
Current clamp limit (2.25 V ≤VCC ≤2.8 V)
ILIM
THERMAL SHUT DOWN
TSD+
TSD-
TSD-
TSD turn on temperature
154
135
13
168
150
17
181
166
°C
°C
°C
TSD turn off temperature
TSD hysteresis
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Product Folder Links: SN6505A-Q1 SN6505B-Q1 SN6505D-Q1
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CLK
tCLKTIMER
OUTPUT STAGE
Break-before-make time(SN6505A-
Duration after which device switches to internal clock in case of invalid external clock
10
25
µs
Measured as voltage with RL = 50 Ωto VCC
,
,
115
90
ns
ns
Q1)
Refer to 图7-3
tBBM
Break-before-make time (SN6505B-
Q1 and SN6505D-Q1)
Measured as voltage with RL = 50 Ωto VCC
Refer to 图7-3
SOFT-START ENABLED (SN6505A-Q1 AND SN6505B-Q1)
10% to 90% transition time on VOUT With
transformer CLOAD = 40 µF
RL = 5 Ω
Soft-start time (SN6505A-Q1)
Soft-start time (SN6505B-Q1)
Soft-start time delay
1
1
2.2
4.25
8.5
8
8
ms
ms
ms
tSS
10% to 90% transition time on VOUT With
transformer CLOAD = 40 µF
RL = 5 Ω
From power up to 90% transition time on VOUT With
transformer CLOAD = 40 µF
RL = 5 Ω
tSSdelay
3.5
18
SOFT-START DISABLED (SN6505D-Q1)
From EN=1 to full drive-current available at D1 and
D2; 2.25 V ≤VCC < 3 V
75
60
1
160
100
5
µs
µs
µs
tPWRUP
Power up time
From EN=1 to full drive-current available at D1 and
D2; 3 V ≤VCC ≤5.5 V
From EN=0 to output MOSFETs off (no current on
D1 and D2)
tPWRDN
Power down time
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Product Folder Links: SN6505A-Q1 SN6505B-Q1 SN6505D-Q1
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
6.7 Typical Characteristics, SN6505A-Q1
6
100
90
80
70
60
50
40
30
20
10
0
5
4
3
2
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
1
25
25
125 225 325 425 525 625 725 825 925
Load Current (mA)
125 225 325 425 525 625 725 825 925
Load Current (mA)
D006
SN6505A-Q1 + Wurth 750315240
SN6505A-Q1 + Wurth 750315240
图6-1. Output Voltage vs Load Current
图6-2. Efficiency vs Load Current
7
100
90
80
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D029
Load Current (mA)
D028
Load Current (mA)
SN6505A-Q1 + Wurth 750316031
VCC = 3.3 V
SN6505A-Q1 + Wurth 750316031
VCC = 3.3 V
图6-4. Efficiency vs Load Current
图6-3. Output Voltage vs Load Current
7
100
90
80
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D031
D030
Load Current (mA)
Load Current (mA)
SN6505A-Q1 + Wurth 750316032
VCC = 3.3 V
SN6505A-Q1 + Wurth 750316032
VCC = 3.3 V
图6-6. Efficiency vs Load Current
图6-5. Output Voltage vs Load Current
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Product Folder Links: SN6505A-Q1 SN6505B-Q1 SN6505D-Q1
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
7
6.5
6
100
90
80
70
60
50
40
30
20
10
0
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D033
Load Current (mA)
D032
Load Current (mA)
SN6505A-Q1 + Wurth 750316033
VCC = 5 V
SN6505A-Q1 + Wurth 750316033
VCC = 5 V
图6-8. Efficiency vs Load Current
图6-7. Output Voltage vs Load Current
170
1.6
1.4
1.2
1
VCC = 2.25 V
VCC = 5.5 V
VCC = 2.25 V
VCC = 5.5 V
165
160
155
150
0.8
0.6
0.4
0.2
0
-75
-25
25
Temperature (èC)
75
125
100
200
300 400
External Frequency (kHz)
500
600
D003
D001
图6-9. Frequency vs Free-Air Temperature
图6-10. Current vs External Frequency
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Product Folder Links: SN6505A-Q1 SN6505B-Q1 SN6505D-Q1
English Data Sheet: SLLSF95
SN6505A-Q1, SN6505B-Q1, SN6505D-Q1
ZHCSJ04D –NOVEMBER 2018 –REVISED OCTOBER 2020
www.ti.com.cn
6.8 Typical Characteristics, SN6505B-Q1 or SN6505D-Q1
6
5
4
3
2
1
100
90
80
70
60
50
40
30
20
10
0
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
25
125 225 325 425 525 625 725 825 925
Load Current (mA)
25
125 225 325 425 525 625 725 825 925
Load Current (mA)
D008
D007
SN6505B/D-Q1 + Wurth 750315371
SN6505B/D-Q1 + Wurth 750315371
图6-12. Efficiency vs Load Current
图6-11. Output Voltage vs Load Current
4
100
90
80
70
60
50
40
30
20
10
0
3.5
3
2.5
2
1.5
1
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D011
D010
SN6505B/D-Q1 + Wurth 760390011
VCC = 3.3 V
SN6505B/D-Q1 + Wurth 760390011
VCC = 3.3 V
图6-14. Efficiency vs Load Current
图6-13. Output Voltage vs Load Current
6
100
90
80
70
60
50
40
30
20
10
0
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D013
D012
SN6505B/D-Q1 + Wurth 760390012
VCC = 5 V
SN6505B/D-Q1 + Wurth 760390012
VCC = 5 V
图6-16. Efficiency vs Load Current
图6-15. Output Voltage vs Load Current
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6
5.5
5
100
90
80
70
60
50
40
30
20
10
0
4.5
4
3.5
3
2.5
2
1.5
1
0
0
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D013
D014
SN6505B/D-Q1 + Wurth 760390013
VCC = 3.3 V
SN6505B/D-Q1 + Wurth 760390013
VCC = 3.3 V
图6-18. Efficiency vs Load Current
图6-17. Output Voltage vs Load Current
5
100
90
80
70
60
50
40
30
20
10
0
4.5
4
3.5
3
2.5
2
1.5
1
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D017
D016
SN6505B/D-Q1 + Wurth 760390014
VCC = 3.3 V
SN6505B/D-Q1 + Wurth 760390014
VCC = 3.3 V
图6-20. Efficiency vs Load Current
图6-19. Output Voltage vs Load Current
7
100
90
80
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D019
D018
SN6505B/D-Q1 + Wurth 760390014
VCC = 5 V
SN6505B/D-Q1 + Wurth 760390014
VCC = 5 V
图6-22. Efficiency vs Load Current
图6-21. Output Voltage vs Load Current
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7
6.5
6
100
90
80
70
60
50
40
30
20
10
0
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D021
D020
SN6505B/D-Q1 + Wurth 760390015
VCC = 3.3 V
SN6505B/D-Q1 + Wurth 760390015
VCC = 3.3 V
图6-24. Efficiency vs Load Current
图6-23. Output Voltage vs Load Current
7
100
90
80
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D021
D022
Load Current (mA)
Load Current (mA)
SN6505B/D-Q1 + Wurth 750316028
VCC = 3.3 V
SN6505B/D-Q1 + Wurth 750316028
VCC = 3.3 V
图6-26. Efficiency vs Load Current
图6-25. Output Voltage vs Load Current
7
100
90
80
70
60
50
40
30
20
10
0
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
100 200 300 400 500 600 700 800 900
Load Current (mA)
0
100 200 300 400 500 600 700 800 900
Load Current (mA)
D025
D024
SN6505B/D-Q1 + Wurth 750316029
VCC = 3.3 V
SN6505B/D-Q1 + Wurth 750316029
VCC = 3.3 V
图6-28. Efficiency vs Load Current
图6-27. Output Voltage vs Load Current
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4.5
4
100
90
80
70
60
50
40
30
20
10
0
3.5
3
2.5
2
1.5
1
D027
Load Current (mA)
D026
Load Current (mA)
SN6505B/D-Q1 + Wurth 7503160030
VCC = 5 V
SN6505B/D-Q1 + Wurth 7503160030
VCC = 5 V
图6-30. Efficiency vs Load Current
图6-29. Output Voltage vs Load Current
450
3
2.5
2
VCC = 2.25 V
VCC = 5.5 V
VCC = 2.25 V
VCC = 5.5 V
440
430
420
410
400
1.5
1
0.5
0
-75
-25
25
Temperature (èC)
75
125
100
400
700 1000
External Frequency (kHz)
1300
1600
D004
D002
图6-31. Frequency vs Free-Air Temperature
图6-32. Current vs External Frequency
Time 2.5 ms/div
图6-33. Scope Capture of SN6505 Switching from External to Internal Clock
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7 Parameter Measurement Information
SN6505
VOUT
4
3
2
1
GND
EN
D2
VCC
Enable
5
6
V
CC
Ext Clock
CLK
D1
10µF 0.1µF
10µF
Copyright © 2016, Texas Instruments Incorporated
图7-1. Measurement Circuit for Unregulated Output (TP1)
图7-2. Timing Diagram
VCC
SN6505
50ꢀ
4
3
2
1
GND
EN
D2
Enable
5
6
V
CC
50ꢀ
Ext Clock
CLK
D1
10µF
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图7-3. Test Circuit for FSW, V(slew), tBBM
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VCC
C1
V
(Current)
SN6505
VCC
4
3
2
1
GND
EN
D 2
5
6
Vcc
D 1
CLK
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图7-4. I(slew) Test Setup
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8 Detailed Description
8.1 Overview
The SN6505x-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters
utilizing the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
The output frequency of the oscillator is divided down by two . A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. Before either one of the gates can assume logic high, the
BBM logic ensures a short time period during which both signals are low and both transistors are high-
impedance. This short period, is required to avoid shorting out both ends of the primary. The resulting output
signals, present the gate-drive signals for the output transistors.
8.2 Functional Block Diagram
EN
D2 D1
V
CC
UVLO
TEMP
SSC
OSC
÷ 2
MOSFET
Driver
CLK
I-LIM
Ext CLK
Detect
GND GND
8.3 Feature Description
8.3.1 Push-Pull Converter
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary
(see 图8-1).
CR
CR
1
1
V
V
OUT
OUT
C
C
R
R
L
L
V
V
IN
IN
CR
CR
2
2
Q
Q
Q
Q
1
2
1
2
图8-1. Switching Cycles of a Push-Pull Converter
When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative
voltage potential at the lower primary end with regards to the VIN potential at the center-tap.
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive
with regards to the center-tap in order to maintain the previously established current flow through Q2, which now
has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a
voltage potential at the open end of the primary of 2×VIN with regards to ground.
Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The
positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current
starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load
impedance RL back to the center-tap.
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When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.
Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2
is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,
charging the capacitor and returning through the load to the center-tap.
8.3.2 Core Magnetization
图 8-2 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as
the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2
conducts the flux is pulled back from A’to A. The difference in flux and thus in flux density is proportional to the
product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈VP × tON
.
B
V
V
P
IN
A’
H
R
V
DS
DS
A
V
= V +V
P DS
IN
图8-2. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)
This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.
If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from
the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the
transformer slowly creeps toward the saturation region.
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8.4 Device Functional Modes
The functional modes of the device are divided into start-up, operating, and off-mode.
8.4.1 Start-Up Mode
When the supply voltage at VCC ramps up to 2.25 V , the internal oscillator starts operating . The output stage
begins switching but the amplitude of the drain signals at D1 and D2 has not reached its full maximum yet.
8.4.1.1 Soft-Start
SN6505A-Q1 and SN6505B-Q1 devices support soft-start feature. Upon power up or when EN pin transitions
from Low to High, the gate drive of the output power-MOSFET is gradually increased over a period of time from
0 V to VCC. Soft-start prevents high inrush current from VCC while charging large secondary side decoupling
capacitors, and also prevents overshoot in secondary voltage during power-up. For applications that need quick
power-up, the SN6505D-Q1, that has soft-start disabled, can be used.
8.4.2 Operating Mode
When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations
over supply voltage and operating temperature can vary the switching frequencies at D1 and D2.
8.4.3 Shutdown-Mode
The device has a dedicated enable pin to put the device in very low power mode to save power when not in use.
Enable pin has an internal pull down resistor which keeps device disabled when not driven. When disabled or
when VCC is < 1.7 V , both drain outputs, D1 and D2, are tri-stated.
8.4.4 Spread Spectrum Clocking
Radiated emissions is an important concern in high current switching power supplies. SN6505 addresses this by
modulating its internal clock in such a way that the emitting energy is spread over multiple frequency bins. This
Spread Spectrum clocking feature greatly improves the emissions performance of the entire power supply block
and hence relieves the system designer from one major concern in isolated power supply design.
8.4.5 External Clock Mode
The SN6505x-Q1 has a CLK pin which can be used to synchronize the device with system clock and in turn with
other SN6505x-Q1 devices so that the system can control the exact switching frequency of the device. The
Rising edge of the CLK is used to divide a clock by two and used to drive the gates. 图 9-2 shows the timing
diagram for the same. The device also has external clock fail safe feature which automatically switches the
device to the internal clock if a valid input clock is not present for long (tCLKTIMER). The in-built emissions
reduction scheme of Spread Spectrum clocking is disabled when external clock is present.
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9 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN6505x-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters
using the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
Vcc
SN6505
Q off
2
Q off
1
D2
D1
S
S
G
G
2
Q
2
Freq.
Divider
BBM
Logic
fOSC
OSC
1
Q
1
Q on
1
Q on
2
tBBM
GND
GND
Copyright © 2016, Texas Instruments Incorporated
图9-1. Block Diagram and Output Timing With Break-Before-Make Action
The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gate-
drive signals for the output transistors Q1 and Q2. As shown in 图9-2, before either one of the gates can assume
logic high, there must be a short time period during which both signals are low and both transistors are high-
impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of
the primary.
图9-2. Detailed Output Signal Waveforms
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9.2 Typical Application
VIN = 3.3V
10µF
SN6505
TPS76350
MBR0520L
VOUT
1:2.2
VOUT-REG = 5V
4
5
6
3
2
1
1
2
3
5
4
GND
EN
D2
Vcc
D1
IN
OUT
GND
EN
ENABLE
CLOCK
10µF 0.1µF
10µF
NC
CLK
MBR0520L
Copyright © 2016, Texas Instruments Incorporated
图9-3. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1 as design parameters.
表9-1. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
3.3 V ± 3%
5 V
Maximum load current
100 mA
9.2.2 Detailed Design Procedure
The following recommendations on components selection focus on the design of an efficient push-pull converter
with high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter
output drops significantly over a wide range in load current. The characteristic curve in 图 6-1 and 图 6-11 for
example, shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a
transceiver’s supply range. Therefore, in order to provide a stable, load independent supply while maintaining
maximum possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised.
The final converter circuit is shown in 图 9-8. The measured VOUT and efficiency characteristics for the regulated
and unregulated outputs are shown in 图6-2 and 图6-12.
9.2.2.1 Drive Capability
The transformer driver is designed for low-power push-pull converters with input and output voltages in the range
of 2.25 V to 5.5 V. While converter designs with higher output voltages are possible, care must be taken that
higher turns ratios don’t lead to primary currents that exceed the specified current limits of the device.
9.2.2.2 LDO Selection
The minimum requirements for a suitable low dropout regulator are:
• Its current drive capability should slightly exceed the specified load current of the application to prevent the
LDO from dropping out of regulation. Therefore, for a load current of 600 mA, choose a 600 mA to 750 mA
LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout
voltages that will reduce overall converter efficiency.
• The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain
efficiency. For a low-cost 750 mA LDO, a VDO of 600 mV at 750 mA is common. Be aware; however, that this
lower value is usually specified at room temperature and can increase by a factor of 2 over temperature,
which in turn will raise the required minimum input voltage.
• The required minimum input voltage preventing the regulator from dropping out of line regulation is given
with:
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VI-min = VDO-max + VO-max
(1)
This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO
and VO specified in the LDO data sheet for rated output current (that is, 600 mA) and add them together. Also
specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than
VI-min. If it is not, the LDO will lose line-regulation and any variations at the input passes straight through to
the output. Hence, below VI-min the output voltage follows the input and the regulator behaves like a simple
conductor.
• The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this
condition there is no secondary current reflected back to the primary, thus making the voltage drop across
RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point, the
secondary reaches its maximum voltage of
VS-max = VIN-max × n
(2)
with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the
LDO from damage the maximum regulator input voltage must be higher than VS-max. 表 9-2 lists the maximum
secondary voltages for various turns ratios commonly applied in push-pull converters.
表9-2. Required Maximum LDO Input Voltages for Various Push-Pull Configurations
PUSH-PULL CONVERTER
LDO
VI-max [V]
6 to 10
10
CONFIGURATION
3.3 VIN to 3.3 VOUT
3.3 VIN to 5 VOUT
5 VIN to 5 VOUT
VIN-max [V]
TURNS-RATIO
1.5 ± 3%
VS-max [V]
5.6
3.6
3.6
5.5
2.2 ± 3%
8.2
1.5 ± 3%
8.5
10
9.2.2.3 Diode Selection
A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output
as possible. When used in high-frequency switching applications, such as the SN6505x-Q1 however, the diode
must also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly
recommended in push-pull converter designs. A good choice for low-volt applications and ambient temperatures
of up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mA
forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher
DC blocking voltage of 30 V.
Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the above
Schottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifier
output voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such as
RB168MM-40.
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1
1
TJ = 125°C
25°C
0°C
-40°C
75°C
-25°C
TJ = 100°C
25°C
75°C
0.1
0.1
0.01
0.01
0.2
0.3
0.4
0.5
0.1
0.2
0.3
0.4
0.5
Forward Voltage, VF - V
Forward Voltage, VF - V
图9-5. Diode Forward Characteristics MBR0530
图9-4. Diode Forward Characteristics for
MBR0520L
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9.2.2.4 Capacitor Selection
The capacitors in the converter circuit in 图9-8 are multi-layer ceramic chip (MLCC) capacitors.
As with all high speed CMOS ICs, the device requires a bypass capacitor in the range of 10 nF to 100 nF.
The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast
switching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with a
dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4-
layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the
supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a
reference plane or to the primary center-tap.
The bulk capacitor at the rectifier output smooths the output voltage. Make this capacitor 1 μF to 10 μF.
The small capacitor at the regulator input is not necessarily required. However, good analog design practice
suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise
rejection.
The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The
choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in
most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.
9.2.2.5 Transformer Selection
9.2.2.5.1 V-t Product Calculation
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied
by the device. The maximum voltage delivered by the device is the nominal converter input plus 10%. The
maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified
input voltage. Therefore, the transformer’s minimum V-t product is determined through:
T
V
IN-max
max
Vt
³ V
´
=
min
IN-max
2
2 ´ f
min
(3)
Taking an example of fmin as 138 kHz for SN6505A-Q1 and 363 kHZ for SN6505B-Q1 or SN6505D-Q1 with a 5
V supply, 方程式3 yields the minimum V-t products of:
5.5 V
= 20 Vµs for SN6505A-Q1, and
Vtmin
≥
≥
2 x 138 kHz
5.5 V
= 7.6 Vµs for SN6505B/D-Q1 applications.
Vtmin
2 x 363 kHz
(4)
Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical
footprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as
little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only.
While Vt-wise all of these transformers can be driven by the device, other important factors such as isolation
voltage, transformer wattage, and turns ratio must be considered before making the final decision.
9.2.2.5.2 Turns Ratio Estimate
Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that the
transformer chosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer
web sites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pull
converter to operate flawlessly over the specified current and temperature range. This minimum transformation
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ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction
factor that takes the transformer’s typical efficiency of 97% into account:
VP-min = VIN-min - VDS-max
(5)
VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still
provide sufficient input voltage for the regulator to remain in regulation. From the 节 9.2.2.2 section, this
minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:
VS-min = VF-max + VDO-max + VO-max
(6)
V
F
V
DO
V
V
O
I
V
R
S
L
V
V
IN
P
V
DS
R
Q
DS
图9-6. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min
Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible
drain-source voltage of the device, VDS-max, from the minimum converter input voltage VIN-min
:
VP-min = VIN-min –VDS-max
(7)
VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the data
sheet:
VDS-max = RDS-max × IDmax
(8)
Then inserting 方程式8 into 方程式7 yields:
VP-min = VIN-min - RDS-max x IDmax
(9)
and inserting 方程式9 and 方程式6 into 方程式5 provides the minimum turns ration with:
VF-max + VDO-max + VO-max
nmin = 1.031 ´
VIN-min - RDS-max ´ ID-max
(10)
Example:
For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO, the data sheet values
taken for a load current of 600 mA and a maximum temperature of 85°C are VF-max = 0.2 V,
VDO-max = 0.5 V, and VO-max = 5.1 V.
Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2%
accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at
3.3 V are taken from the data sheet with RDS-max = 0.31 Ωand ID-max = 1 A.
Inserting the values above into 方程式10 yields a minimum turns ratio of:
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0.2 V + 0.5 V + 5.1V
nmin = 1.031 ´
3.234 V - 0.31 Ω ´ 1 A
= 2.05
(11)
Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3
with a common tolerance of ±3%.
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9.2.2.5.3 Recommended Transformers
Depending on the application, use the minimum configuration in 图9-7 or standard configuration in 图9-8.
图9-7. Unregulated Output for Low-Current Loads With Wide Supply Range
图9-8. Regulated Output for Stable Supplies and High Current Loads
The Wurth Electronics Midcom isolation transformers in 表 9-3 are optimized designs for the device, providing
high efficiency and small form factor at low-cost.
The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents.
These applications operate without LDO, thus achieving further cost-reduction.
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表9-3. Recommended Isolation Transformers Optimized for the Device
TURNS
RATIO
V × T
(Vμs)
ISOLATION
DIMENSIONS
APPLICATION
LDO(1)
ORDER NO.
MANUFACTURER
(VRMS
)
(mm)
3.3 V →3.3 V, 100mA, SN6505B/D-Q1
Refer to 图6-13 and 图6-14
1:1.1 ±2%
7
760390011
5 V →5 V, 100mA, SN6505B/D-Q1
Refer to 图6-15 and 图6-16
1:1.1 ±2%
1:1.7 ±2%
1:1.3 ±2%
1:1.3 ±2%
No
760390012
760390013
760390014
760390014
3.3 V →5 V, 100mA, SN6505B/D-Q1
Refer to 图6-17 and 图6-18
6.73 x 10.05 x 4.19
3.3 V →3.3 V, 100mA, SN6505B/D-Q1
Refer to 图6-19 and 图6-20
11
5 V →5 V, 100mA, SN6505B/D-Q1
Refer to 图6-21 and 图6-22
Yes
3.3 V →5 V, 100mA, SN6505B/D-Q1
Refer to 图6-23 and 图6-24
1:2.1 ±2%
1.23:1 ±2%
1:1.7 ±2%
2500
760390015
750313710
750316028
5 V →3.3 V, 100mA, SN6505B/D-Q1
3.3 V →3.3 V, 1A, SN6505B/D-Q1
Refer to 图6-25 and 图6-26
8.9
3.3 V →5 V, 1A, SN6505B/D-Q1
Refer to 图6-27 and 图6-28
1:2.1 ±2%
1.3:1 ±2%
750316029
750316030
8.3 x 12.6 x 4.1
5 V →3.3 V, 1A, SN6505B/D-Q1
Refer to 图6-29 and 图6-30
10.8
8.6
Wurth Electronics /
Midcom
3.3 V →3.3 V , 1A , SN6505B/D-Q1
5 V →5 V , 1A , SN6505B/D-Q1
Refer to 图6-11 and 图6-12
No
1:1.1 ±2%
750315371
1:1.1 ±2%
1:1.1 ±2%
1:1.7 ±2%
750313734
750313734
750313769
3.3 V →3.3 V, 100mA, SN6505B/D-Q1
5 V →5 V, 100mA, SN6505B/D-Q1
3.3 V →5 V, 100mA, SN6505B/D-Q1
11
9.14 x 12.7 x 7.37
3.3 V →3.3 V, 100mA, SN6505B/D-Q1
5 V →5 V, 100mA, SN6505B/D-Q1
1:1.3 ±2%
750313638
Yes
1:2.1 ±2%
1.3:1 ±2%
750313626
750313638
3.3 V →5 V, 100mA, SN6505B/D-Q1
5 V →3.3 V, 100mA , SN6505B/D-Q1
No
5000
3.3 V →3.3 V, 1A, SN6505A-Q1
Refer to 图6-3 and 图6-4
1:1.75 ±2%
1:2 ±2%
Yes
750316031
750316032
750316033
41
3.3 V →5 V, 1A, SN6505A-Q1
Refer to 图6-5 and 图6-6
12.32 x 15.41 x 11.05
5.0 V →3.3 V, 1A, SN6505A-Q1
Refer to 图6-7 and 图6-8
1.3:1 ±2%
42
23
11
No
3.3 V →3.3 V, 1A, SN6505A-Q1
5 V →5 V, 1A , SN6505A-Q1
Refer to 图6-1 and 图6-2
1:1.1 ±2%
1:1.3 ±3%
12.32 x 15.41 x 11.89
10.4 x 12.2 x 6.1
750315240
3.3 V →3.3 V, 300mA, SN6505B/D-Q1
5 V →5 V, 300mA , SN6505B/D-Q1
5000
No
HCT-SM-1.3-8-2
Bourns
3.3 V →3.3 V, 1A, SN6505A/B/D-Q1
5 V →5 V, 1A , SN6505A/B/D-Q1
1:1.5 ±3%
1:2.2 ±3%
34.4
21.5
2500
2500
10 x 12.07 x 5.97
10 x 12.07 x 5.97
DA2303-AL
DA2304-AL
Yes
Coilcraft
3.3 V →5 V, 1A, SN6505A/B/D-Q1
(1) For configurations with LDO, a higher voltage than the required output voltage is generated, to allow for LDO drop-out. Figures show
the voltage and efficiency at the LDO input.
9.2.3 Application Curves
See the 节 6.7 and 节 6.8 for application curves with transformers optimized for the device, providing high
efficiency and small form factor at low-cost.
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9.2.4 System Examples
9.2.4.1 Higher Output Voltage Designs
The device can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of
up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to
5, requires different rectifier topologies to achieve high output voltages. 图 9-9 to 图 9-11 show some of these
topologies together with their respective open-circuit output voltages.
n
n
V
VOUT = +n·VIN
V
=2n·V
IN
V
IN
OUT
IN
图9-10. Bridge Rectifier Without Center-Tapped
VOUT = -n·VIN
Secondary Performs Voltage Doubling
图9-9. Bridge Rectifier With Center-Tapped
Secondary Enables Bipolar Outputs
V
=4n·V
IN
OUT
n
V
IN
图9-11. Half-Wave Rectifier Without Centered Ground and Center-Tapped Secondary Performs Voltage
Doubling Twice, Hence Quadrupling VIN
9.2.4.2 Application Circuits
The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated
microcontroller supply. For 5 V input voltages requiring different turn ratios refer to the transformer
manufacturers and their web sites listed in 表9-4.
表9-4. Transformer Manufacturers
MANUFACTURER
MORE INFORMATION
Coilcraft Inc.
http://www.coilcraft.com
Halo-Electronics Inc.
Murata Power Solutions
Wurth Electronics Midcom Inc
http://www.haloelectronics.com
http://www.murata-ps.com
http://www.midcom-inc.com
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4
8
1
3
5
4
GND
D2
IN
OUT
EN
SN6505-Q1
3
2
7
6
3.3 V
TPS76350-Q1
EN
VCC
D1
2
GND
NC
1
5
CLK
8
3.3 V
1
VCC1
TXD
VCC2
VDD
7
6
2
3
CANH
TXD
MCU
RXD
CANL
ISO1042-Q1
RXD
Optional bus
protection
function
DGND
4
5
GND2
GND1
Galvanic
Isolation Barrier
Digital
Ground
ISO
Ground
图9-12. Isolated CAN Interface
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10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5 V nominal. This input
supply must be regulated within ±10%. If the input supply is located more than a few inches from the device, a
0.1 μF by-pass capacitor should be connected as close as possible to the device VCC pin and a 10 μF
capacitor should be connected close to the transformer center-tap pin.
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11 Layout
11.1 Layout Guidelines
• The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum
and a X5R or X7R dielectric.
• The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area
formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See 图11-1 for a PCB layout
example.
• The connections between the device D1 and D2 pins and the transformer primary endings, and the
connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum
trace inductance.
• The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-
ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The
capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
• The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
• The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
• The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range
to maximize efficiency.
• The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum
and a X5R or X7R dielectric.
11.2 Layout Example
图11-1. Layout Example of a 2-Layer Board
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to Isolate Signal and Power in Isolated CAN Systems TI TechNote
• Texas Instruments, Small Form-Factor Reinforced Isolated IGBT Gate Drive Reference Design for 3-Phase
Inverter TI Design
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
SN6505A-Q1
SN6505B-Q1
SN6505D-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.8 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN6505AQDBVRQ1
SN6505AQDBVTQ1
SN6505BQDBVRQ1
SN6505BQDBVTQ1
SN6505DQDBVRQ1
SN6505DQDBVTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
65AQ
65AQ
65BQ
65BQ
65DQ
65DQ
Samples
Samples
Samples
Samples
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN6505A-Q1, SN6505B-Q1 :
Catalog : SN6505A, SN6505B
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN6505AQDBVRQ1
SN6505AQDBVRQ1
SN6505AQDBVTQ1
SN6505BQDBVRQ1
SN6505BQDBVTQ1
SN6505BQDBVTQ1
SN6505DQDBVRQ1
SN6505DQDBVRQ1
SN6505DQDBVTQ1
SN6505DQDBVTQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.23
3.2
3.17
3.2
1.37
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3.23
3.23
3.2
3.17
3.17
3.2
1.37
1.37
1.4
3000
250
250
3.23
3.2
3.17
3.2
1.37
1.4
3000
3000
250
3.23
3.2
3.17
3.2
1.37
1.4
250
3.23
3.17
1.37
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN6505AQDBVRQ1
SN6505AQDBVRQ1
SN6505AQDBVTQ1
SN6505BQDBVRQ1
SN6505BQDBVTQ1
SN6505BQDBVTQ1
SN6505DQDBVRQ1
SN6505DQDBVRQ1
SN6505DQDBVTQ1
SN6505DQDBVTQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
3000
3000
250
213.0
210.0
213.0
213.0
210.0
213.0
210.0
213.0
210.0
213.0
191.0
185.0
191.0
191.0
185.0
191.0
185.0
191.0
185.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
250
3000
3000
250
250
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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Copyright © 2023，德州仪器 (TI) 公司
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