SN6507DGQRQ1 [TI]
具有占空比控制的汽车级低辐射 36V 推挽式变压器驱动器 | DGQ | 10 | -55 to 125;
| 型号： | SN6507DGQRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有占空比控制的汽车级低辐射 36V 推挽式变压器驱动器 | DGQ | 10 | -55 to 125 变压器 驱动 驱动器 |
| 文件： | 总44页 (文件大小：2809K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN6507-Q1
ZHCSND7 –SEPTEMBER 2022
SN6507-Q1 适用于隔离式电源且具有占空比控制功能的低发射36V 推挽式变压
器驱动器
1 特性
3 说明
• 提供功能安全
SN6507-Q1 是一款高压、高频推挽式变压器驱动器，
以小尺寸解决方案提供隔离电源。该器件具有推挽式拓
扑结构的简单性、低 EMI 和磁通消除等优点，可防止
变压器饱和。采用占空比控制技术来减少宽输入范围的
元件数量，同时选择高开关频率来缩小变压器尺寸，从
而进一步节省空间。
– 可提供用于功能安全系统设计的文档：SN6507-
Q1
• 符合面向汽车应用的AEC-Q100（1 级）标准
• 使用SN6507-Q1 并借助WEBENCH® Power
Designer 创建定制设计方案
• 用于隔离变压器的推挽式驱动器
• 宽输入电压范围：3V 至36V
– 输入电压容差高达60V
– 用于线路调节的占空比控制
• 具有可编程电流限制的0.5A 开关
• 宽开关频率范围：100kHz 至2MHz
该器件集成了控制器和两个异相切换的0.5A NMOS 电
源开关。其输入工作范围通过精密欠压锁定进行编程。
该器件通过过流保护 (OCP) 、可调节欠压锁定
(UVLO)、过压锁定 (OVLO)、热关断 (TSD) 和先断后
通型电路来防止出现故障条件。
可编程软启动 (SS) 可尽可能减少浪涌电流，并为满足
关键的上电要求提供电源时序。展频时钟 (SSC) 和引
脚可配置的压摆率控制 (SRC) 进一步降低了辐射和传
导发射，以满足超低EMI 要求。
– 与小尺寸变压器兼容
– 可编程开关频率
– 外部时钟同步选项
• 低噪声和发射
– 对称推挽式拓扑
– 展频时钟
– 引脚可配置压摆率控制
• 保护特性
SN6507-Q1 可采用 10 引脚 HVSSOP DGQ 封装。该
器件的运行温度范围为–55°C 至125°C。
封装信息
封装(1)
封装尺寸（标称值）
器件型号
– 可调节欠压锁定(UVLO)
– 可编程过流保护(OCP)
– 过压锁定(OVLO)
HVSSOP（10 引
脚）
SN6507-Q1
3.00mm × 3.00mm
– 热关断(TSD)
(1) 有关所有的可用封装，请参阅数据表末尾的可订购产品附录。
• 宽温度范围：-55°C 至125°C
• 可编程软启动，可减小浪涌电流
• 带有散热焊盘的10 引脚HVSSOP (DGQ) 封装
2 应用
适用于以下应用的隔离式电源：
• 电池管理系统(BMS)
• 车载充电器
• 直流/直流转换器
• 逆变器和电机控制
VIN
CIN
VOUT
EN/UVLO
DC
SW1
VCC
Optional
COUT
SR
SS/ILIM
CLK
SW2
GND
RLIM
CSS
RDC RSR
GND
Optional
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFM1
SN6507-Q1
ZHCSND7 –SEPTEMBER 2022
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Table of Contents
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 23
9.3 Power Supply Recommendations.............................32
9.4 Layout....................................................................... 32
10 Device and Documentation Support..........................34
10.1 Documentation Support.......................................... 34
10.2 Receiving Notification of Documentation Updates..34
10.3 Community Resources............................................34
10.4 Trademarks.............................................................34
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................7
6.7 Typical Characteristics, SN6507-Q1 ..........................8
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
September 2022
*
Initial Release
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5 Pin Configuration and Functions
DGQ PACKAGE
(TOP VIEW)
SW2
GND
1
10
9
SW1
GND
VCC
2
Thermal
Pad
(11)
3
SS/ILIM
CLK
8
7
EN/UVLO
DC
4
5
SR
6
图5-1. DGQ Package, 10-Pin HVSSOP (Top View)
表5-1. Pin Functions
PIN
NO.
DESCRIPTION
NAME
TYPE(1)
Open drain output of the first power MOSFET, switch 1. Typically connected to either of the outer
terminals of the center tap transformer. Because large currents flow through these pins, their
external traces should be kept short.
SW1
1
O
Ground connection of internal control circuits and power MOSFET. Pin 2 and Pin 9 must be
shorted on PCB for optimzed emissions and efficiency.
GND
VCC
2
3
GND
P
The VCC pin is the main supply pin for the power and analog circuits. Short duration, high-current
pulses are produced during the turn on and turn off of the power switches.
Enable input and undervoltage lockout (UVLO) programming pin.
•
•
•
If the pin voltage is above EN_UVLO threshold , the device is enabled and will start switching
when VCC is above VCC_UVLO threshold.
If the pin is shorted to VCC, the device is self-started when VCC is above VCC_UVLO
threshold.
EN/UVLO
4
I
If the pin is floating, or the pin voltage is below EN_UVLO threshold, the device stops
switching.
Duty cycle control pin to compensate input variation. A resistor on this pin to GND sets the duty
cycle. If unused, leave the pin floating, the duty cycle is set to the default value (48%). Duty cyle
control is disabled in SYNC mode.
DC
5
6
7
I
I
I
Slew rate control pin to further optimize emission performance. This pin adjusts slew rate of SW1
and SW2 by connecting a resistor to GND. If the pin is left floating, the device switches at the
default slew rate.
SR
This pin is used to sync the device with an external clock (SYNC mode) or program the switching
frequency by connecting the pin to ground through a resistor. If shorted to GND, the device will
switch at its default frequency (1MHz typical). If left floating, the device will stop switching.
CLK
Multifunction Soft-Start (SS) and Current-Limit (ILIM) input pin.
•
•
A capacitor to GND is needed to set the output soft-start time and input inrush current.
A resistor to GND is needed to protect the device through the programmable current limit.
SS/ILIM
8
I
Ground connection of internal control circuits and power MOSFET. Pin 2 and Pin 9 must be
shorted on PCB for optimized emissions and efficiency.
GND
9
GND
O
Open drain output of the second power MOSFET, switch 2. Typically connected to either of the
outer terminals of the center tap transformer. Because large currents flow through these pins, their
external traces should be kept short.
SW2
10
11
GND pins (Pin 2 and Pin 9) must be electrically connected to the power pad (Pin 11) on the
printed circuit board for proper operation.
PowerPAD
GND
(1) I = input, O = output, P = power, GND = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
.
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
Supply voltage (2)
VCC
60
VCC + 0.5
6
Voltage
EN/UVLO
V
Voltage
SS/ILIM, CLK, DC
SW1, SW2
I(D1)Pk, I(D2)Pk
V
Output switch voltage
Peak output switch current
Junction temperature, TJ
Storage temperature range, Tstg
85
V
1.6
A
-55
150
°C
°C
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the local ground terminal (GND) and are peak voltage values.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 3A
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
36
UNIT
VCC
Input Voltage
3
V
3 V < VCC < 6 V
6 V < VCC < 36 V
0.4
0.5
125
150
10
ISW1, ISW2
Output switch current - Primary side
A
TA
Ambient temperature
°C
°C
µF
kΩ
kΩ
kΩ
–55
–55
0.05
18
TJ
Junction temperature
CSS
RILIM
RSR
RCLK
Soft-start capacitor on SS/ILIM pin
Current limiting resistor on SS/ILIM pin
Resistor on SR pin for Slew rate control
Resistor on CLK pin for programmable frequency
261
21
4.8
4
111
6.4 Thermal Information
SN6507
THERMAL METRIC(1)
DGQ (HVSSOP)
UNIT
10 PINS
48.2
61.6
18.4
1.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJT
18.3
5.8
ψJB
RθJC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Minimum and maximum limits apply over the recommended junction temperature range, unless otherwise indicated. All
typical values are at TA = 25°C, VCC = 24 V, CLK FSW = 1 MHz and VEN/UVLO=2.5 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN Supply Current (3 V < VC C < 36V) , not
including switch drive currents
Icc
3
4
mA
VEN/UVLO=2.5 V, RL = 50 Ω
ISHUTDOWN
ILKG(SS/ILIM)
VIN shutdown current
0.8
2.5
0.7
µA
µA
VEN/UVLO=0 V, RL = 50 Ω
Leakage Current on SS/ILIM pin
VEN/UVLO = 0 V, Voltage of SS/ILIM = 5 V
ENABLE AND UVLO
VCCUVLO-
VCC Positive-going UVLO threshold
VCC Negative-going UVLO threshold
VCC rising , EN/UVLO is shorted to VCC
2.8
2.9
V
RISING
VCCUVLO-
VCC falling, EN/UVLO is shorted to VCC
EN/UVLO is shorted to VCC
EN/UVLO rising
2.5
0.1
1.4
2.67
0.12
1.5
V
V
V
FALLING
VCCUVLO-HYS VCC UVLO threshold hysteresis
ENUVLO-
EN/UVLO Positive-going UVLO threshold
1.6
RISING
ENUVLO-
EN/UVLO Negative-going UVLO threshold
EN/UVLO falling
1.25
0.14
1.35
0.15
1.45
V
V
FALLING
ENUVLO-HYS
EN/UVLO UVLO threshold hysteresis
POWER STAGE
Average ON time mismatch between SW1 and
SW2
RL = 50 Ωto VCC, Pull-Up Resistor Test Circuit
Configuration
DMM
R(ON)
0
%
Output switch ON resistance
VCC = 24 V, ISW1, ISW2 = 0.5 A
0.45
1
Ω
RL = 50 Ωto VCC, VCC = 12 V; RSR = 9.6 kΩ
(Default), Pull-Up Resistor Test Circuit
Configuration
V(SLEW)
Voltage slew rates on SW1 and SW2
Voltage slew rates on SW1 and SW2
298
369
V/µs
V/µs
RL = 50 Ωto VCC, VCC = 12 V; RSR = 9.6 kΩ
(Default), Pull-Up Resistor Test Circuit
Configuration
V(SLEW)
CLK
RL = 50 Ω, RCLK = 0 kΩ, Pull-Up Resistor Test
FSW
D1, D2 average switching Frequency (Default)
External clock frequency on CLK pin
780
200
1000
1296
kHz
kHz
Circuit Configuration
External clock applied on CLK pin for SYNC
mode. SW1/SW2 switches at 1/2 the external
CLK frequency
F(SYNC)
4000
1.8
VCLK(High)
VCLK(Low)
SOFT-START
ISS
CLK pin logic high threshold
CLK pin logic low threshold
1.6
1.2
V
V
1.0
SS ext capacitor charging current
SS ext capacitor range
275
µA
µF
CSS Range
0.05
5
CURRENT LIMIT
ILIM
ILIM
ILIM
SW1 and SW2 Current Limit
1.00
0.56
0.06
1.30
0.79
0.10
1.59
1.02
0.14
A
A
A
RLIM = 18.2 kΩ, 5 V < VCC < 36 V
RLIM = 30.1 kΩ, 5 V < VCC < 36 V
RLIM = 261 kΩ, 5 V < VCC < 36 V
SW1 and SW2 Current Limit
SW1 and SW2 Current Limit
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Minimum and maximum limits apply over the recommended junction temperature range, unless otherwise indicated. All
typical values are at TA = 25°C, VCC = 24 V, CLK FSW = 1 MHz and VEN/UVLO=2.5 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC CONTROL
DC pin floating (Default), FSW = 300KHz, Timing
Diagram
Dsw1, Dsw2
Switching Duty Cycle on SW1 and SW2
Switching Duty Cycle on SW1 and SW2
48
48
%
%
External CLK (SYNC mode), FSW
300KHz, Timing Diagram
=
Dsw1, Dsw2
INPUT OVLO
VCCOVLO-
Input Over-voltage Lockout Rising Threshold
Input Over-voltage Lockout Falling Threshold
VCC rising
36.9
38.7
40.5
40.0
V
RISING
VCCOVLO-
VCC falling
36.5
0.47
38.2
0.57
V
V
FALLING
VCCOVLO-HYS Input Over-voltage Lockout Hysteresis
VCC hysteresis voltage
THERMAL SHUT DOWN
TSD+
TSD turn on temperature
TSD turn off temperature
TSD hysteresis
TJ rising
TJ falling
170
135
32
184
147
37
198
159
42
°C
°C
°C
TSD-
TSD-HYST
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6.6 Switching Characteristics
Minimum and maximum limits apply over the recommended junction temperature range, unless otherwise indicated. All
typical values are at TA = 25°C, VCC = 24 V, CLK FSW = 1 MHz and VEN/UVLO=2.5 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE AND UVLO
TEN_glitch
EN glitch filter
5
µs
POWER STAGE
Measured at 0.5VCC with RL = 50 Ω, FSW = 1
MHz, RSR = 9.6 kΩ (or Default), Timing Diagram
tBBM
Break-before-make time
70
ns
SOFT-START
tPWRUP
CSS = 0 µF, from EN = High to full drive-current
available at SW1 and SW2
Power-up time
300
400
30
µs
µs
CSS = 0 µF, from EN = Low to output MOSFETs
tPWRDN
Power-down time
off (no current on SW1 and SW2
)
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6.7 Typical Characteristics, SN6507-Q1
16
15.9
15.8
15.7
15.6
15.5
15.4
15.3
15.2
15.1
15
17
16.95
16.9
16.85
16.8
16.75
16.7
16.65
16.6
16.55
16.5
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Load current (A)
Load current (A)
SN6507-Q1 + Wurth 750319696
VIN = 24 V
SN6507-Q1 + Wurth 750319692
VIN = 12 V
图6-2. Output Voltage vs Load Current
图6-1. Output Voltage vs Load Current
91
92
90
88
86
84
82
80
78
76
74
90.5
90
89.5
89
88.5
88
87.5
87
86.5
86
85.5
0.1
0.15
0.2
0.25
Load current (A)
0.3
0.35
0.4
0.45
0.5
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Load current (A)
SN6507-Q1 + Wurth 750319692
VIN = 12 V
SN6507-Q1 + Wurth 750319696
VIN = 24 V
图6-3. Efficiency vs Load Current
图6-4. Efficiency vs Load Current
1077500
1077000
1076500
1076000
1075500
1075000
1074500
1074000
1073500
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (C)
0
250 500 750 1000 1250 1500 1750 2000 2250
Fsw (kHz)
RCLK = 0 kΩ
图6-6. ICC vs Switching Frequency
图6-5. Switching Frequency vs Free-Air
Temperature
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39.2
2.85
2.8
VCCOVLO-RISING
VCCOVLO-FALLING
VCCUVLO-RISING
VCCUVLO-FALLING
39
38.8
38.6
38.4
38.2
2.75
2.7
2.65
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Junction temperature (C)
Junction temperature (C)
图7-3
RL = 50 Ω
图7-3
RL = 50 Ω
图6-7. VCC OVLO Thresholds vs Junction
图6-8. VCC UVLO Thresholds vs Junction
Temperature
Temperature
1.6
ENUVLO-RISING
ENUVLO-FALLING
1.55
1.5
1.45
1.4
1.35
-60 -40 -20
0
20
40
60
80 100 120 140
Junction temperature (C)
图7-3
RL = 50 Ω
图7-3
RL = 50 Ω
图6-9. EN/UVLO Thresholds vs Junction
图6-10. RON vs Junction Temperature
Temperature
60
55
50
45
40
35
30
25
-55C
25C
125C
SN6507-Q1 + Wurth 750319696
CSS = 50 nF
图7-1
0
5
10
15
20
VCC (V)
25
30
35
40
VIN = 24 V
RILIM = 18.2 kΩ
图7-3
RL = 50 Ω
图6-12. Output Voltage During Soft Start with 50-
图6-11. Break-Before-Make Time vs VCC
mA, 250-mA, and 500-mA Loads
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SN6507-Q1 + Wurth 750319696
CSS = 500 nF
图7-1
SN6507-Q1 + Wurth 750319696
RILIM = 18.2 kΩ CSS = 5 μF
图7-1
VIN = 24 V
RILIM = 18.2 kΩ
VIN = 24 V
图6-13. Output Voltage During Soft Start with 50-
图6-14. Output Voltage During Soft Start with 50-
mA, 250-mA, and 500-mA Loads
mA, 250-mA, and 500-mA Loads
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7 Parameter Measurement Information
VIN
10 µF
VOUT
SW1
EN/UVLO
DC
Enable
10 µF
0.1 µF
Adjustable RDC
Adjustable RSR
VCC
SR
0.1 µF
10 µF
SS/ILIM
CLK
Adjustable RILIM and CSS
Adjustable CLK
SW2
GND
GND
图7-1. Measurement Circuit for Output
1/fsw
tr
Q1 On
Q1 Off
Q2 Off
Q2 On
tf
tBBM
图7-2. Timing Diagram
RL
EN/UVLO SW1
DC
Adjustable RDC
Adjustable RSR
VIN
SR
VCC
10 µF
SS/ILIM
CLK
Adjustable RILIM and CSS
Adjustable CLK
RL
SW2
GND
GND
图7-3. Pull-Up Resistor Test Circuit Configuration
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8 Detailed Description
8.1 Overview
The SN6507-Q1 is a 36-V, 0.5-A push-pull transformer driver with two integrated n-channel power MOSFETs. It
is designed for low cost, small size, low EMI isolated DC/DC power supplies.
The device includes an oscillator that feeds a gate-drive circuit. The gate-drive, comprising a frequency divider
and a break-before-make (BBM) logic, provides two complementary output signals which alternately turn the two
output NMOS transistors on and off. A subsequent break-before-make logic inserts a dead-time between the
high-pulses of the two signals to avoid shorting out both ends of the transformer's primary windings. The
resulting output signals drive an isolation transformer and rectifier, converting the input voltage to an isolated
output voltage.
To improve performance at wide-input applications, the device implements a Duty Cycle Control (DCC) feature
that the duty cyle is dynamically adjusted to compensate for the input variation. It removes the need of pre-
regulation if the input variation is within a certain degree. Or even if at wide input conditions where the input
variation is out of regulation range, it saves secondary-side LDO size and power loss. The wide switching
frequency range allows for better efficiency and smaller output ripple, as well as size optimization when selecting
the transformers.
The transformer driver comes with multiple protection features to ensure robust operation, such as
programmable overcurrent protection (OCP), input OVP, input UVLO and TSD. The device minimizes excessive
output overvoltage transients by taking advantage of the overvoltage comparator. When the overvoltage
comparator is activated, the MOSFETs are turned off and prevented from turning on until the overvoltage
condition is removed. The device implements overload protection for both MOSFETs which help control the
transformer current and avoid transformer saturation. It also shuts down if the junction temperature is higher than
the thermal shutdown trip point. A programmable soft-start period reduces the inrush current during start-up and
fault recovery.
For ultra-low EMI applications, the slew rate control feature provides design flexibility and simplicity to further
improve emissions with a resistor-programmable option.
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8.2 Functional Block Diagram
VCC
Internal
Bias
LDO
Bandgap
SW1
SW2
+
+
–
UVLO
TSD
Thermal
Detection
VREF_OV
–
VREF_UVLO
RENT
OVP
EN/UVLO
+
Control Logic
MOSFET
Driver
EN
VREF_EN
–
RENB
External
CLK Detect
OCP
CLK
RCLK
÷2
ILIM
IBIAS
MUX
Oscillator with SSC and
Duty Cycle Control
Soft Start
ILIM Sensor
SS
SS/ILIM
DC
GND
SR
GND
RDC
RSR
RILIM
CSS
8.3 Feature Description
8.3.1 Push-Pull Converter
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary
as shown in 图8-1. When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus
creating a negative voltage potential at the lower primary end with regards to the VIN potential at the center-tap. .
CR
CR
1
1
V
V
OUT
OUT
C
C
R
R
L
L
V
V
IN
IN
CR
CR
2
2
Q
Q
Q
Q
1
2
1
2
图8-1. Switching Cycles of a Push-Pull Converter
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive
with regards to the center-tap in order to maintain the previously established current flow through Q2, which now
has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a
voltage potential at the open end of the primary of 2×VIN with regards to ground.
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Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The
positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current
starting from the upper secondary end flows through CR1, charges capacitor C, and returns through the load
impedance RL back to the center-tap.
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.
Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2
is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,
charging the capacitor and returning through the load to the center-tap.
8.3.2 Core Magnetization
图 8-2 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H as
the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2
conducts the flux is pulled back from A’to A. The difference in flux and thus in flux density is proportional to the
product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈VP × tON
.
B
V
V
P
IN
A’
H
R
V
DS
DS
A
V
= V +V
P DS
IN
图8-2. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)
This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.
If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from
the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the
transformer slowly creeps toward the saturation region.
Fortunately, due to the positive temperature coefficient of a MOSFET’s on-resistance, the output FETs of the
SN6507-Q1 have a self-correcting effect on V-t imbalance. In the case of a slightly longer on-time, the prolonged
current flow through a FET gradually heats the transistor which leads to an increase in RDS-on. The higher
resistance then causes the drain-source voltage, VDS, to rise. Because the voltage at the primary is the
difference between the constant input voltage, VIN, and the voltage drop across the MOSFET, VP = VIN – VDS
,
VPis gradually reduced and V-t balance restored.
8.3.3 Duty Cycle Control
The SN6507-Q1 implements a duty cycle control feature to provide line regulation to a certain degree through a
resistor on DC pin. By making the DC pin voltage a function of the input, the duty cycle will adjust with VIN, so
that VOUT can be kept constant. Compared to fixed duty cycle transformer drivers, this dynamic duty cycle
control feature reduces LDO power loss for wide VIN variations by pseudo-regulating the output. For applications
where input variation is within a certain range, this feature can eliminate the post-regulation LDO. Another
benefit of duty cycle control is to reduce the transformer cost and size because of the limited input range to
primary side of the transformer.
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VCC
IL
ILOAD
CIN
EN/UVLO
DC
SW1
VCC
RLOAD
COUT
SR
RDC
SS/ILIM
CLK
SW2
GND
RLIM
CSS
GND
RCLK
图8-3. Schematic with duty cycle control
The calculation of DC pin resistor is shown in 方程式1, where both RDC and RCLK are in kΩ.
R
= 0.816 × D × VCC × R
+ 1 − 1
(1)
DC
CLK
For fixed oscillator cases where RCLK is shorted to GND, a value of RCLK = 9.6kΩ should be used in the equation
above to calculate RDC
.
The duty cycle control can compensate for input variation up to ±35%, where line regulation within ±5% can be
achieved. To achieve this range, it is recommended that duty cycle at nominal VIN is centered at 25% (D = 0.25).
The transformer turns ratio needs take this duty cycle into calculation to ensure the expected output voltage level
at all VIN voltages, as discussed in 节9.2.2.5.
The duty cycle control features supports up to a certain duty cycle and VIN range. The minimum duty cycle is
determined by the charge and discharge time of the gate capacitance of Power FETs, while the maximum duty
cycle is limtied by the dead time (70 ns typical). For example, at 1 MHz, the adjustable duty cycle is between
10% and 43%. Exceeding above duty cycle range, the line regulation may saturate and input compensation
does not work anymore. Meanwhile, if the duty cycle is lower than the minimum spec, the part may hit current
limit at heavy loads. The VIN range that duty cycle feature is applicable is from 6 V to 36 V.
To enable the duty cycle control feature, an inductor is required on the output side. The selection of the output
inductor should make sure the inductor current will not go into discountinous conduction mode (DCM), meaning
the inductor current ramp should not drop to zero at any time. The minimum inductance LMIN is therefore
calculated by the conditions that the part stays in continuous conduction mode (CCM) where the load DC current
is smaller than half the current ramp amplitude seen on the inductor. Therefore LMIN is a function of the load
current and switching frequency as shown by below equation where Iload is in A, fSW is in Hz, D is the duty cycle
as a decimal (for 25% duty cycle, 0.25 would be used), and Lmin is in H.
1 − 2 × D × V
4 × I
/V
IN TYP IN MAX
L
= V
×
(2)
MIN
OUT
× f
LOAD MIN
SW
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SW1
SW2
SW2 on
SW1 on
ISW
TON
TOFF
IL
ILPK
ILOAD
Iripple
0
图8-4. Waveforms in Continuous Conduction Mode (CCM)
SW1
SW2
SW1 on
SW2 on
ISW
TON
TOFF
IL
ILPK
ILOAD
Iripple
0
图8-5. Waveforms in Discontinuous conduction Mode (DCM)
Programmable Switching Frequency
SN6507-Q1 has an internal oscillator to set the switching frequency of the power stage. As the two power
switches are out of phase, the oscillator frequency is twice of the actual switching frequency of each power
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switch. The duty cycle is fixed with 70 ns deadtime to avoid shoot-through. The duty cycle is changeable if duty
cycle feature is enabled. Please refer to 节8.3.3.
SN6507-Q1 has a wide switching frequency range from 100 kHz up to 2 MHz, which is pin-programmable
through a resistor (RCLK) to GND. Below table lists the value of RCLK to achieve certain operating frequencies
(fSW). The choice of switching frequency is a trade-off between power efficiency and size of capacitive and
inductive components. For example, when operating at higher switching frequency, the size of the transformer
and inductor is reduced, resulting in a smaller design footprint and lower cost. However, higher frequency
increases switching losses and consequently degrades the overall power supply efficiency.
表8-1. Recommended 1% RCLK values and fSW Look-up Table
RCLK
fSW (Typical)
105 kHz
111 kΩ
523 kHz
21 kΩ
1.07 MHz
9.6 kΩ
2.13 MHz
4.1 kΩ
Default (1 MHz)
0 kΩ (Short to GND)
图8-6 can also be used to estimate the programmable switching frequency, fSW, using an external resistor value,
R
CLK, where RCLK is in kΩ and fSW is in kHz:
2000
1000
500
100
4
6
8 10
30
50
70 90 110
RCLK (k)
图8-6. Approximate SN6507-Q1 Switching Frequency, FSW, for RCLK Range
If CLK pin is shorted to GND, the part switches at its default frequency, FSW. CLK pin floating is not a valid state
of operation and will cause the part to stop switching until an external clock signal is present.
8.3.4 Spread Spectrum Clocking
Radiated emissions is an important concern in high current switching power supplies. Due to the periodicity of
the digital clock signals, the energy concentrates in one particular frequency and also in its odds harmonics,
causing EMI issues. SN6507-Q1 implements Spread spectrum clocking (SSC) to reduce the radiated emissions
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of digital clock signals. The device modulates its internal clock in such a way that the emitting energy is spread
over multiple frequency bins. This feature greatly improves the emissions performance of the entire power
supply block and hence relieves the system designer from one major concern in isolated power supply design.
8.3.5 Slew Rate Control
To allow optimization of EMI with respect to efficiency, the SN6507-Q1 is designed to allow a resistor (RSR) to
select the strength of the driver of PowerFETs turning on. As shown in 图 8-7 below, the slew rate of the
switching edges is controllable with the resistor. Rolling off harmonics through slew rate control can eliminate the
need for shielding and common mode chokes in many applications.
The EMI benefit of slew rate control may result in slightly reduced efficiency and higher peak current (ISW_SR).
When the feature slows down the charging and discharging of the gate capacitance, the extended transition
times of the FETs increases the transition losses during each switching cycle. This increases power dissipation,
which decreases efficiency and exacerbates thermal concerns. This will limit how much the slew rate can be
reduced. Another cost is the peak current of each cyle will be increased. It is because the slow edges reduce the
on-time (ION_SR) and eventually the peak current (ISW_SR) will increase to deliver the same average current to the
load on each cycle.
VSW
SR1
SR2
TON_SR2
TON_SR1
ISW_SR2
ISW_SR1
ISW
图8-7. Slew Rate Control Scheme
The slew rate at different VIN is programmed by RSR. Higher RSR values configure SN6507-Q1 for slower slew
rates across VCC levels while lower RSR values configure SN6507-Q1 for faster slew rates. The relationship
between VCC and the slew rate for 12 V and 24 V cases are listed in 表 8-2 below. As the slew rate is
independent of the switching frequency, care must be taken that at high frequencies, the slew rate should be fast
enough to maximize the output power delivery to the load. If the SR pin is left floating, the slew rate will be set to
the default value. An SR pin short to GND is read as a fault condition, and the device will stop switching.
表8-2. Slew Rate Control Look-up Table
VCC (V)
RSR (kΩ)
Typical SLEW RATE (V/μs)
5
5
5
5
4.8
337
Floating (Default)
263
224
198
15
21
12
12
12
12
4.8
424
298
237
199
Floating (Default)
15
21
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表8-2. Slew Rate Control Look-up Table (continued)
VCC (V)
24
RSR (kΩ)
Typical SLEW RATE (V/μs)
4.8
583
369
273
218
24
Floating (Default)
24
15
21
24
8.3.6 Protection Features
SN6507-Q1 is protected by multiple protection features to improve the system level robustness and reliability.
The protection features include programmable input undervoltage protection (UVLO), input over-voltage
protection (OVP), programmable over current protection (OCP), and over-temperature protection (TSD).
8.3.6.1 Over Voltage Protection (OVP)
As SN6507-Q1 is a open-loop transformer driver, the over voltage protection feature is implemented to prevent
the output voltage from rising too high. The overvoltage protection threshold is a fixed value and cannot be
programmed. If the VCC pin voltage exceeds the overvoltage rising threshold, device stops switching after a 550
ns (typical) response time. To recover from an over voltage event, the input voltage must drop below the OVP
falling threshold.
8.3.6.2 Over Current and Short Circuit Protection (OCP)
The SN6507-Q1 is protected from overcurrent conditions with cycle-by-cycle current limiting on both NMOS
switches. OCP is disabled during soft-start. After soft-start finishes, the OCP is enabled, and the threshold is set
at the programmed value. The switch current is sensed and compared to the current threshold that is
programmed by the external resistor on SS/ILIM pin, RILIM. Common current limit thresholds (ILIM) and their
corresponding resistor values for RILIM are listed in 表 8-3 below. Leaving the ILIM/SS pin floating is not
recommended for this device.
表8-3. Recommended 1% RILIM values
RILIM
18 kΩ
20 kΩ
22 kΩ
24 kΩ
27 kΩ
30 kΩ
35 kΩ
40 kΩ
50 kΩ
62 kΩ
85 kΩ
127 kΩ
261 kΩ
ILIM (Typical)
1.3 A
1.2 A
1.1 A
1.0 A
900 mA
800 mA
700 mA
600 mA
500 mA
400 mA
300 mA
200 mA
100 mA
In case of an extreme over-load condition on the isolated output due to a short circuit, the device behaves as
follows:
• In the event of a transient overload or short circuit, if the resulting voltage dip is lower than 2.5 V (typical) on
the SS/ILIM pin, the device considers it as a “soft-short”condition. In soft-shorts, the converter goes into
hiccup mode: on hitting the programmed OCP threshold, the driver will be shut-off for 100 ns (typical), and
then retry driving. If the OCP trips again, the cycle continues. This retry keeps occurring for entire TON time of
SW1 and SW2 until OCP does not trip or a "hard-short" is triggered. During the OCP retry events, both FETs
are turned OFF, and the transient peak current may go higher than OCP limit.
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• If the voltage dip is more than 2.5 V (typical), the devices considers it as a “hard-short”condition. The
hard-short OCP threshold is fixed at 5 A (typical). If a hard-short condition lasts more than 200 μs, it
indicates that the system is in a serious short-circuit fault condition, the device will fully discharge the soft-
start cap and enters soft start once the short circuit is cleared. Note there is a 65 ns (typ.) response time to
trigger hard-short OCP.
8.3.6.3 Under Voltage Lock-Out (UVLO)
Start-up and shutdown are controlled by the both EN/UVLO pin and VCC pin. For the device to remain in
shutdown mode, apply a voltage below ENUVLO to the EN/UVLO pin. In shutdown mode, the quiescent current is
less than 0.8 µA (typical). If EN/UVLO pin sees a voltage higher than ENUVLO, but VIN is still below VCCUVLO, the
SW node is inactive. Once the VIN is above VCCUVLO, the chip begins to switch normally, provided the EN/UVLO
voltage is above 1.5 V.
There are three ways to enable the device operation. The simplest way is to connect the EN/UVLO pin to VCC
pin, allowing self-start-up of the device when VCC pin voltage is above VCCUVLO level. However, many
applications benefit from an input UVLO level different than that provided internal UVLO. So another way is to
employ an enable resistor divider network as shown in Figure below, which establishes a programmable UVLO
threshold. The thrid way is to connect an external logic output to drive this pin, allowing user-defined system
power sequencing.
EN/UVLO pin has a 5 µs (typical) glitch filter to help avoid false turn-on and turn-off due to noise coupling. It also
comes with an internal pull down design to ensure the device is in shutdown mode when the pin is left floating.
Programmable UVLO using EN/UVLO pin
VIN
RENT
EN/UVLO
RENB
GND
Resistor values can be calculated using Equation below, where the input turn on threshold VIN_UVLO is the
desired typical start-up input voltage, ENUVLO is 1.5 V typical, and RENT and RENB are in Ω.
R
ENT
V
= 1 +
× EN
(3)
IN_UVLO
UVLO
R
ENB
8.3.6.4 Thermal Shut Down (TSD)
Thermal shutdown prevents the device from reaching extreme junction temperatures by turning off the internal
switches when the IC junction temperature exceeds 180°C (typical). In TSD, the switching stops immediately to
prevent the internal MOSFETs from failing in either high ambient temperature operation conditions or due to self-
heating from high switching current. To recover from thermal shut down condition, the junction temperature must
be below the overtemperature protection falling threshold. When the junction temperature falls below 147°C
(typical), the power FET switching is enabled.
8.4 Device Functional Modes
The functional modes of the device are divided into start-up, operating, and off-mode.
8.4.1 Start-Up Mode
When VCC pin voltage ramps up to VCCUVLO , and EN/UVLO pin voltage is over ENUVLO the internal oscillator
starts operating. The output stage begins switching but the amplitude of the drain signals at SW1 and SW2 have
not reached its full maximum yet.
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8.4.1.1 Soft-Start
SN6507-Q1 device supports soft-start feature. Upon power up or when EN/UVLO pin transitions from Low to
High, the gate drive of the output powerFET is gradually increased over a period of time from 0 V to full driving
strength. Soft-start prevents high inrush current from VCC while charging large secondary side decoupling
capacitors, and also prevents overshoot in secondary voltage during power-up.
The sort-start time to ramp to the peak switch current is calculated by the capacitor and resistor on SS/ILIM pin
with the following formula.
C
SS
T
=
(4)
SS
0.6
275μA −
R
ILIM
During soft-start, the over-current protection is disabled. To ensure a smooth transition between soft-start and
the steady state, it's recommended to have a CSS value between 50 nF and 5 µF with an output capacitor, COUT
,
of less than 10 times the value of CSS
.
8.4.2 Operation Mode
The SN6507-Q1 driver is in operation mode when EN pin is above ENUVLO, VIN pin is above VCCUVLO, and soft-
start completes. In normal operation mode, the switching frequency is fixed, determined either by the CLK pin
resistor or external Clock signal.
8.4.3 Shutdown Mode
The device has a dedicated EN/UVLO pin to put the device in very low power mode to save power when not in
use. EN/UVLO pin has an internal pull down resistor which keeps device disabled when not driven. When
disabled or when VCC is < 2.8 V , both drain outputs, SW1 and SW2, are tri-stated.
8.4.4 SYNC Mode
The SN6507-Q1 has a CLK pin which can be used to synchronize the device with system clock and in turn with
other SN6507-Q1 devices so that the system can control the exact switching frequency of the device. In SYNC
mode, the CLK frequency is divided by two to drive the gates of powerFETs. 图9-2 shows the timing diagram for
the same.
The device cannot automatically change from SYNC mode to switching frequency control using the internal
oscillator or resistor-programmable switching frequency mode. If a valid external CLK signal is not present, the
output will stop switching, and a power cycle will be required to change the switching mode back to using the
internal oscillator or the adjustable switching frequency using RCLK
.
When the device is in SYNC mode, duty cycle control and SSM are not supported, therefore it's recommended
to leave DC pin floating in SYNC mode to reduce the solution size.
Note that it is recommended that the SN6507-Q1 VCC pin powers up before CLK pin. Before device power-up,
the initial state of external clock should be high-impedance.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN6507-Q1 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters
using the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
SW1
SW2
Q1
Q2
S
S
fOSC
MOSFET
Driver
BBM
Logic
Freq
Divider
CLK
GND
图9-1. Block Diagram With Break-Before-Make Action
CLK
S
S
G1
Q1 On
Q2 Off
Q1 Off
G2
Q2 On
SW1
SW2
tBBM
tBBM
tBBM
图9-2. Output timing with Break-Before-Make Action
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The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gate-
drive signals for the output transistors Q1 and Q2. As shown in 图9-2, before either one of the gates can assume
logic high, there must be a short time period during which both signals are low and both transistors are high-
impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends of
the primary.
9.2 Typical Application
Two application cases are discussed. One is for Fixed input with slew rate control. The other is for wide-ranging
input with duty cycle control.
VIN = 24V
LDO
1:N
RENT
10µF
VOUT = 15V
VIN
VOUT
EN/UVLO
DC
SW1
VCC
10µF
10µF
0.1µF
FB
SR
SS/ILIM
CLK
SW2
GND
RENB
RSR
RCLK
RILIM
CSS
GND
图9-3. Typical Application Schematic for Fixed Input with Slew Rate Control
VIN = 18V-30V
LDO
1:N
RENT
10µF
L
VOUT = 15V
VIN
VOUT
EN/UVLO
DC
SW1
VCC
10µF
10µF
0.1µF
FB
SR
SS/ILIM
CLK
SW2
GND
RENB
RCLK
RDC
RILIM
CSS
GND
图9-4. Typical Application Schematic for Wide-Ranging Input with Duty Cycle Control
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1 as design parameters.
表9-1. Design Parameters
PARAMETER
COMMENT
EXAMPLE VALUE
Fixed VIN
Input voltage for fixed input case
24 V ± 2%
18 V (min)
24 V (typ.)
30 V (max)
Wide-ranging VIN
Input voltage range for wide-input case
fSW
VOUT
ILOAD
ILIM
Switching frequency
Output voltage
1 MHz ± 10%
15 V
Load current
200 mA
500 mA
9 V
Peak Current Limit
Under Voltage Lockout
Soft-Start Time
UVLO
SS
2 ms
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9.2.2 Detailed Design Procedure
This section presents a detailed design procedures using the SN6507-Q1 transformer driver. The following
recommendations on components selection focus on the design of an efficient push-pull converter with high
current drive capability. Two cases are discussed: wide input range with duty cycle control, and a compact
design with a fixed input voltage.
The pin configuration of SN6507-Q1 are discussed by 5 simple steps, followed by the selection of external
components, including diodes, capacitors, inductor, LDO and transformers.
9.2.2.1 Pin Configuration
Here is an example of how to configure the SN6507-Q1 pins in 5 simple steps.
Step 1: Set the Switching Frequency
First, set the driver switching frequency with RCLK using 表8-1.
For example: RCLK = 9.6 kΩ or shorted to GND, sets typical fSW at about 1 MHz.
Step 2: Set the Input UVLO
The EN/UVLO (undervoltage lockout) pins are used to set minimum input voltage that the driver starts switching.
The resister divider value can be calculated by 方程式3.
For example, if the input threshold (VON) is expected to be at 9 V, the resistors are calculated as RENT/RENB = 5
Therefore,the resistors values are chosen as:
RENT = 5 kΩ, RENB = 1 kΩ
To make the device self-start at default UVLO thresold (2.8 V typical), users can skip Step 2 and directly short
the EN/UVLO pin to VCC.
Step 3: Set the Current Limit and Soft-Start Time
The current limit can be set by a resistor on SS/ILIM pin according to 表 8-3. Peak currents may be very high
during operation of the overcurrent protection system until the fault is cleared.
For example, to set the current limit is set at 500 mA (typical), the recommended RILIM is 50 kΩ.
Once RILIM is determined, substitue RILIM into 方程式4, the soft-time calculation is:
C
SS
T
=
SS
0.6
50k
275μA −
Taking 2 ms (typical) soft-start time as an example, the capacitor on SS/ILIM pin :CSS = 0.5 uF.
Note that both RILIM and CSS are required on SS/ILIM pin to ensure the robust operation of this device. Missing
the RC connection or leaving the pin floating should be avoided.
Step 4: Set the Duty Cycle
For fixed input cases, the duty cycle feature is not needed. This step can be skipped by leaving DC pin floating,
so that the device will operate at default maximum duty (48% typical). The maximum duty cycle is determined by
the switching period and the deadtime (70 ns typical) to avoid overlap of two power switches.
For wide-input cases, the duty cycle feature can be enabled by connecting a resistor RDC on DC pin, and an
inductor at the output side. The inductor selection is presented in 节9.2.2.4.
To achieve maximum input compensation, the DC is set close to 0.25 (25% duty cycle) at typical VCC (24 V). The
RDC is calculated as 50.9 kΩ by substituting DC = 0.25, VCC = 24 V, and RCLK = 9.6 into 方程式 1, where both
R
CLK and RDC are in kΩ.
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9.2.2.2 LDO Selection
SN6507-Q1 is an open-loop transformer driver without load regulation capability. The output voltage may vary
over a wide range load current. Therefore, if a high-accuracy, load independent supply is required, the
implementation of a low dropout regulator (LDO) on the output side is strongly advised.
The minimum requirements for a suitable low dropout regulator are:
• Its current drive capability should slightly exceed the specified load current of the application to prevent the
LDO from dropping out of regulation. Therefore, for a load current of 200 mA, choose a 200 mA to 300 mA
LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout
voltages that will reduce overall converter efficiency.
• The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain
efficiency. For a low-cost 300 mA LDO, a VDO of 600 mV at 300 mA is common. Be aware; however, that this
lower value is usually specified at room temperature and can increase by a factor of 2 over temperature,
which in turn will raise the required minimum input voltage.
• The required minimum input voltage preventing the regulator from dropping out of line regulation is given
with:
VI-min = VDO-max + VO-max
(5)
This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO
and VO specified in the LDO data sheet for rated output current (that is, 200 mA) and add them together. Also
specify that the output voltage of the push-pull rectifier at the specified load current is equal or higher than
VI-min. If it is not, the LDO will lose line-regulation and any variations at the input passes straight through to
the output. Hence, below VI-min the output voltage follows the input and the regulator behaves like a simple
conductor.
• The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this
condition there is no secondary current reflected back to the primary, thus making the voltage drop across
RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point, the
secondary reaches its maximum voltage of
VS-max = VIN-max × N
(6)
with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the
LDO from damage the maximum regulator input voltage must be higher than VS-max. 表 9-2 lists the maximum
secondary voltages for various turns ratios commonly applied in push-pull converters.
表9-2. Required Maximum LDO Input Voltages for Various Push-Pull Configurations
PUSH-PULL CONVERTER
LDO
VI-max [V]
25
CONFIGURATION
24 VIN to 15 VOUT
12 VIN to 15 VOUT
VIN-max [V]
TURNS-RATIO (N)
1.38:1
VS-max [V]
25
18
19
12.5
1:1.5
25
9.2.2.3 Diode Selection
A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output
as possible. However, when SN6507-Q1 is used in high-frequency switching applications, the diode must also
possess a low total capacitance, a short recovery time and a current rating greater than the load current.
Schottky diodes meet these requirements and are therefore strongly recommended in SN6507-Q1 push-pull
converter designs.
The necessary diode reverse voltage rating, VR, is determined by the transformer secondary side voltage plus
any voltage ringing. The voltage ringing, however, is difficult to predict, because it depends on multiple factors,
such as loop resistance, the leakage inductance of the transformer, and the diode junction capacitance. As a
rule of thumb, the diode voltage rating should be greater than 1.5 times the transformer turns ratio multiplied by
the maximum input voltage. Because the two secondary windings are connected across the rectifier bridge, a
factor of two is needed, producing the diode maximum DC blocking voltage rating:
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Diode V > 1 . 5 × 2 × N × V
(7)
R
IN MAX
For high-efficiency designs, diodes with low forward voltage, VF, and diode capacitance, CT, can be used, like
BAT165E6327HTSA1 or equivalent can be used for high-efficiency 15-V outputs. Diode parameters like these
parasitics and reverse recovery will impact system efficiency and can affect emissions. For low-emissions
designs, low-emissions diodes can be used, like PMEG200G20ELRX or equivalent can be used for low-
emissions outputs up to 100 V.
9.2.2.4 Capacitor and Inductor Selection
Capacitor Selection
The capacitors in the push-pull converter circuits are normally multi-layer ceramic chip (MLCC) capacitors. As
with many high speed CMOS ICs, the device requires a bypass capacitor of 100 nF. Ensure this capacitor is
placed within 2 mm of the SN6507-Q1 VCC pin.
The input bulk capacitor at the center-tap of the transformer primary side supports large currents into the primary
winding during the fast switching transients. For minimum ripple make this capacitor 1 μF to 10 μF, where 10
μF is preferred. Place this capacitor close to the transformer primary winding center-tap to minimize trace
inductance. If placed on the opposite side of the PCB from the transformer, an additional 100 nF capacitor can
be placed on the same layer and close to the transformer center tap. Use two vias in parallel for each connection
between these capacitors to the transformer center tap to ensure low-inductance paths.
The bulk capacitor at the rectifier output smooths the output voltage. Make this capacitor 500 nF to 10 μF. To
avoid hitting OCP at the transistion from soft-start to steady state, the output capacitor COUT is recommended to
be less than 10 times of CSS connected to the SS/ILIM pin. Otherwise, if there is a short soft-start time due to a
small CSS value, the output capacitor is only partially charged and sees high current spikes on the first switching
cycles after the device exits soft start mode.
Optional capacitors of values between 1 nF to 4.7 nF can be connected to the control pins of SN6507-Q1 for
filtering if operating in noisy environments.
If an LDO is used, an additional small capacitor at the LDO input is not necessarily required. However, good
analog design practice suggests using a small value of 47 nF to 100 nF improves the regulator’s transient
response and noise rejection.
If an LDO is used, an additional capacitor at the LDO output buffers the regulated output supply for the
subsequent isolator and transceiver circuitry. The choice of output capacitor depends on the LDO stability
requirements specified in the data sheet. However, in most cases, a low-ESR ceramic capacitor in the range of
4.7 μF to 10 μF will satisfy these requirements.
Inductor Selection
The inductor is required only for duty cycle feature. The minimum inductor value (LMIN) is is calculated by 方程式
2. Higher inductance produces better regulation and lower voltage ripple, but requires a correspondingly larger
size inductor. The optimum inductor value is determined by taking into account the tradeoff between the
regualtion performance and the size.
For example, when VOUT = 15 V, VIN TYP = 15 V, VIN MAX = 18 V, ILOAD MIN = 250 mA, fSW = 1 MHz, D = 0.25, the
minimum inductance is calculated to be 50 μH.
1 − 2 × 0 . 25 × 15V/18V
L
= 15V ×
= 8 . 75μH
(8)
MIN
4 × 0.25A × 1MHz
9.2.2.5 Transformer Selection
9.2.2.5.1 V-t Product Calculation
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied
by the device: the maximum time this voltage is applied to the primary for half the period of the lowest frequency
at the specified input voltage. For designs using duty cycle control, the maximum V-t applied by the device can
be calculated by the typical voltage applied for one quarter of the period of the lowest switching frequency. For
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systems using a clock frequency set by RCLK, fmin can be estimated as 15% below the typical or approximate
switching frequency value, fSW, for the corresponding RCLK from 节 Programmable Switching Frequency. For
systems where the CLK pin is connected to GND, the minimum specified FSW from 节 6 should be used.
Therefore, the transformer’s minimum V-t product is determined through 方程式 9 for fixed inputs and 方程式
10 for wide-ranging inputs using duty cycle control:
V
T
IN max
max
2
Vt
≥ V
×
=
(9)
min
min
IN max
IN typ
2 × f
min
V
T
IN typ
max
Vt
≥ V
×
=
(10)
4
4 × f
min
Example of Fixed Input:
For a fixed input system with fSW(min) of 780 kHz and a VIN = 24 V supply with ±10 % tolerance, 方程式 9 yields
the minimum V-t product of:
26 . 4V
2 × 780kHz
Vt
≥
= 16 . 9 Vμs
(11)
min
Example of Wide-Ranging Input:
Taking the assumption of fSW(min) as 780 kHz with a VIN(typ) 24 V supply, 方程式 10 yields the minimum V-t
product of:
24V
4 × 780kHz
Vt
≥
= 7 . 7 Vμs
(12)
min
While Vt-wise all of these transformers can be driven by the device, other important factors such as isolation
voltage, transformer wattage, and turns ratio must be considered before making the final decision.
9.2.2.5.2 Turns Ratio Estimate
From previous section, it has been determined that the transformer chosen must have a V-t product of 15 Vμs.
However, before searching the manufacturer web sites for a suitable transformer, the user still needs to know its
minimum turns ratio that allows the push-pull converter to operate flawlessly over the specified current and
temperature range. This minimum transformation ratio is expressed through the ratio of minimum secondary to
minimum primary voltage multiplied by a correction factor that takes the transformer’s typical efficiency of 97%
into account:
VP-min = VIN-min - VDS-max
(13)
VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still
provide sufficient input voltage for the regulator to remain in regulation. From the 节 9.2.2.2 section, this
minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:
VS-min = VF-max + VDO-max + VO-max
(14)
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V
F
V
DO
V
V
O
I
V
R
S
L
V
V
IN
P
V
DS
R
Q
DS
图9-5. Establishing the Required Minimum Turns Ratio Through Nmin = 1.03 × VS-min / VP-min
Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible
drain-source voltage of the device, VDS-max, from the minimum converter input voltage VIN-min
:
VP-min = VIN-min –VDS-max
(15)
VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the data
sheet:
VDS-max = RDS-max × IDmax
(16)
(17)
(18)
Then inserting 方程式16 into 方程式15 yields:
VP-min = VIN-min - RDS-max x IDmax
and inserting 方程式17 and 方程式14 into 方程式13 provides the minimum turns ration with:
V
+ V
DO − max
+ V
× I
F − max
O − max
D − max
N
= 1.03 ×
min
V
− R
IN − min
DS − max
Examples are given on the calculation method. One is for the fixed input case without duty cycle control. The
other is for the wide-ranging input, with or without duty cycle control.
Example of Fixed Input:
For a fixed 24 V VIN to 15 VOUT converter using the rectifier diode PMEG200G20ELRX and the LM317A LDO,
the data sheet values taken for a load current of 500mA and a maximum temperature of 85°C are VF-max = 0.5 V,
VDO-max = 0.7 V, and VO-max = 15.15 V.
Then assuming that the converter input voltage is taken from a 24V regulated supply with a maximum ±2%
accuracy makes VIN-min = 23.52 V. Finally the maximum values for drain-source resistance and drain current at
24 V are taken from the data sheet with RDS-max = 1 Ωand ID-max = 0.5 A.
Inserting the values above into the Equation above yields a minimum turns ratio of:
0.5 V + 0.7 V + 15.1 V
23.52 V − 1 Ω × 0.5 A
N
= 1.03 ×
= 0.72
(19)
min
Example of Wide-Ranging Input:
• Wide-Ranging Input without Duty-Cycle Control
For converter designs with wide-input range but no duty cycle control, the turns ratio needs to take the minimum
input voltage into consideration.
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Assuming the same diode and LDO are used, the calculation, so VF-max = 0.5 V, VDO-max = 0.7 V, and VO-max
15.15 V.
=
The input range from 18 V up to 30 V makes VIN-min = 18 V. The input range from 18 V up to 30 V with 24 V
typical makes VIN-min = 18 V. Substituting the same RDS-max = 1 Ω and ID-max = 0.5 A into the Equation above
yields to a minimum turns ratio of:
0.5 V + 0.7 V + 15.1 V
18 V − 1 Ω × 0.5 A
N
= 1.03 ×
= 0.96
(20)
min
• Wide-Ranging Input with Duty-Cycle Control
For converter designs with wide-input range, the duty cycle feature is useful to compensate input variaton. But
care must be taken to make sure that high turns ratios don’t lead to primary currents that exceed the specified
current limits of the device.
V
+ V
DO − max
+ V
× I
F − max
O − max
1
N
= 1.03 ×
×
(21)
min
V
− R
2D
IN − typ
DS − max
D − max
typ
Assuming the same diode and LDO are used, so VF-max = 0.5 V, VDO-max = 0.7 V, and VO-max = 15.15 V.
It's recommends the use to set the DC=25% at typical VIN-typ = 24 V. Substituting the same RDS-max = 1 Ω and
ID-max = 0.5 A into the Equation above yields to a minimum turns ratio of:
0.5 V + 0.7 V + 15.1 V
24 V − 1 Ω × 0.5 A
1
N
= 1.03 ×
×
= 1.38
(22)
min
2 × 0.25
9.2.2.6 Low-Emissions Designs
For isolated power supply designs requiring low levels of radiated and conducted emissions, the following
recommendations can help minimize emissions from SN6507-Q1 and its surrounding components:
• Ensure a push-pull isolation transformer with low parasitics, like leakage inductance and parasitic
capacitances, is used to minimize common-mode currents across the isolation barrier and antenna effects in
the system.
• Use low-emissions rectifier diodes with low recovery times, like PMEG200G20ELRX or equivalent.
• Configure SN6507-Q1 for its slowest slew-rate setting to minimize high-frequency content in the switching
paths.
• Include a snubber circuit on the secondary-side of the isolation transformer to filter high-frequency content in
the switching paths.
Using these configurations may each affect system-level efficiency. The SN6507DGQEVM can be used to
evaluate these design options.
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9.2.3 Application Curves
VIN = 12 V
图7-3
RL = 50 Ω
图9-6. SN6507-Q1 SWx Voltage and Current Waveforms
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9.2.4 System Examples
9.2.4.1 Higher Output Voltage Designs
The device can drive push-pull converters that provide doubling output voltages, or bipolar outputs with different
rectifier topologies . 图 9-7 to 图 9-9 show some of these topologies together with their respective open-circuit
output voltages.
n
n
V
VOUT = +n·VIN
V
=2n·V
IN
V
IN
OUT
IN
图9-8. Bridge Rectifier Without Center-Tapped
VOUT = -n·VIN
Secondary Performs Voltage Doubling
图9-7. Bridge Rectifier With Center-Tapped
Secondary Enables Bipolar Outputs
V
=4n·V
IN
OUT
n
V
IN
图9-9. Half-Wave Rectifier Without Centered Ground and Center-Tapped Secondary Performs Voltage
Doubling Twice, Hence Quadrupling VIN
9.2.4.2 Commercially-Available Transformers
表 9-3 shows recommended transformer designs for SN6507-Q1 that are commercially available. Although
SN6507-Q1 is compatible with many commercially-available and custom transformers, these part numbers or
equivalents are optimized for use with SN6507-Q1. Transformer equivalents for automotive applications of the
parts listed below may be available from their respective magnetics vendors under different part numbers.
表9-3. Recommended Center Tapped Transformers for SN6507-Q1
APPLICATIO
N
TURNS
RATIO
(1:N)
V-t
product
Min (Vμs)
ISOLATIO
N (VRMS)
DIMENSION (mm)
(L,W,H)
PART NUMBER 1
0.73
0.71
15
30
2.5 k
2.5 k
(8.5, 12.87, 5.16)
(10.3, 12.07, 5.97)
Wurth 750319696
Coilcraft TX1-ZB1459-
BE
24 V→15 V
0.73
0.75
25
25
2.5 k
3.75 k
2.5 k
(11.8, 13.2, 11.1)
(10.3, 13.2, 12.5)
(11, 13.5, 10.54)
Bourns SM91207L-E
Pulse PAG6356.086NLT
0.75
1.4
41.2
22
Semitel EP7-817
Coilcraft TX1-ZB1445-
CE
2.5 k
(10.3, 12.07, 5.97)
1.4
1.2
22
15
2.5 k
2.5 k
2.5 k
(8.5, 12.87, 5.16)
(11.8, 13.2, 11.1)
(11, 13.5, 10.54)
Wurth 750319692
Bourns SM91208L-E
Semitel EP7-815
12 V→15 V
1.4
25.8
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表9-3. Recommended Center Tapped Transformers for SN6507-Q1 (continued)
APPLICATIO
N
TURNS
RATIO
(1:N)
V-t
product
Min (Vμs)
ISOLATIO
N (VRMS)
DIMENSION (mm)
(L,W,H)
PART NUMBER 1
Coilcraft TX1-ZC1891-
AE
1.4
30
2.5 k
(10.3, 12.07, 5.97)
24 V→30 V
12 V→30 V
1.4
1.43
2.6
30
36.1
22
2.5 k
2.5 k
2.5 k
(8.5, 12.87, 5.16)
(11, 13.5, 10.54)
(8.5, 12.87, 5.16)
Wurth 750319948
Semitel EP7-818
Wurth 750319949
Coilcraft TX1-ZC1892-
AE
2.8
22
2.5 k
(10.3, 12.07, 5.97)
2.8
1.09
0.55
0.625
0.27
0.25
2.13
1.13
0.5
25.8
15
2.5 k
2.5 k
2.5 k
3.75 k
2.5 k
3.75 k
2.5 k
2.5 k
2.5 k
3.75 k
(11, 13.5, 10.54)
(8.5, 12.87, 5.16)
(8.5, 12.87, 5.16)
(10.3, 13.2, 12.5)
(8.5, 12.87, 5.16)
(10.3, 13.2, 12.5)
(8.5, 12.87, 5.16)
(8.5, 12.87, 5.16)
(8.5, 12.87, 5.16)
(10.3, 13.2, 12.5)
Semitel EP7-816
Wurth 750319697
24 V→24 V
24 V→12 V
15
Wurth 750319695
50
Pulse PAG6356.085NLT
Wurth 750319694
15
24 V→5 V
50
Pulse PAG6356.082NLT
Wurth 750319693
7.5
7.5
7.5
50
12 V→24 V
12 V→12 V
12 V→5 V
Wurth 750319691
Wurth 750319690
0.125
Pulse PAG6356.081NLT
24 V→3.3 V
1. Not all recommended part numbers are validated by Texas Instruments. Refer to the latest transformer
specifications to determine compatibility with SN6507-Q1.
9.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 3 V and 36 V nominal. If the input
supply is located more than a few inches from the device, a 0.1 μF by-pass capacitor should be connected as
close as possible to the device VCC pin and a 10 μF capacitor should be connected close to the transformer
center-tap pin.
9.4 Layout
9.4.1 Layout Guidelines
• The power supply input, VIN, must be buffered to ground with a low-ESR ceramic bypass-capacitor. The
recommended capacitor value can range from 1 μF to 10 μF, and is typically 10 μF. The capacitor must
have a voltage rating greater than the VIN voltage level and an X5R or X7R dielectric.
• The optimum placement of the VIN capacitor is closest to the VIN and GND pins at the board entrance to
minimize the loop area formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See
图9-10 for a PCB layout example.
• To help ensure reliable operation, a 0.1-μF low-ESR ceramic bypass-capacitor is recommended at the
device VCC pin. The capacitor should be placed as close to the supply pins as possible in the PCB layout and
on the same layer. The capacitor must have a voltage rating greater than the VIN voltage level.
• The connections between the device SW1 and SW2 pins and the transformer primary endings and the
connection of the device VCC pin and the transformer center-tap must be as short as possible for minimum
trace inductance.
• The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-
ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF, and is
typically 10 μF. The capacitor must have a voltage rating greater than the VIN voltage level and an X5R or
X7R dielectric.
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• The device GND pins must be tied to the PCB ground plane using two vias to help minimize inductance.
• The ground connections of the capacitors and other connections to the ground plane should use two vias for
minimum inductance.
• The rectifier diodes should be Schottky diodes with low forward voltage and low capacitance to maximize
efficiency.
• The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The typical
capacitor value can range from 500 nF to 10 μF and should be less than 10 times the value of CSS to ensure
a smooth transition between soft-start and the steady state.
9.4.2 Layout Example
图9-10. Layout Example of a 2-Layer Board
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to Isolate Signal and Power in Isolated CAN Systems TI TechNote
• Texas Instruments, How to Isolate Signal and Power for an RS-485 System TI TechNote
• Texas Instruments, How to Isolate Signal and Power for I2C TI TechNote
• Texas Instruments, How to Reduce Emissions in Push-Pull Isolated Power Supplies TI Application Note
• Texas Instruments, Small Form-Factor Reinforced Isolated IGBT Gate Drive Reference Design for 3-Phase
Inverter TI Design
• Texas Instruments, SN6507DGQEVM Low-Emissions 500 mA Push-Pull Transformer Driver for Isolated
Power Supplies Evaluation Module TI EVM User's Guide
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.3 Community Resources
10.4 Trademarks
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
34
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Product Folder Links: SN6507-Q1
SN6507-Q1
ZHCSND7 –SEPTEMBER 2022
www.ti.com.cn
PACKAGE OUTLINE
DGQ0010D-C01
PowerPADTM - 1.1 mm max height
S
C
A
L
E
3
.
7
0
0
PLASTIC SMALL OUTLINE
C
5.05
4.75
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.08
C A B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
EXPOSED
THERMAL PAD
NOTE 6
4
5
2.22
1.69
0.25
GAGE PLANE
8
1
0.15
0.05
0.7
0.4
0 - 8
1.83
1.45
DETAIL A
TYPICAL
4226759/A 04/2021
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.
6. The thermal pad design could vary depending on manufacturing site.
www.ti.com
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: SN6507-Q1
SN6507-Q1
ZHCSND7 –SEPTEMBER 2022
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DGQ0010D-C01
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(2.2)
NOTE 9
(1.83)
SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
SEE DETAILS
10X (1.45)
10X (0.3)
1
10
(1.3)
(2.22)
TYP
SOLDER MASK
OPENING
SYMM
(3.1)
NOTE 9
8X (0.5)
6
5
(R0.05) TYP
SYMM
METAL COVERED
BY SOLDER MASK
(
0.2) TYP
VIA
(1.3) TYP
(4.4)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226759/A 04/2021
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: SN6507-Q1
SN6507-Q1
ZHCSND7 –SEPTEMBER 2022
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DGQ0010D-C01
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(1.83)
BASED ON
0.125 THICK
STENCIL
10X (1.45)
10X (0.3)
1
10
(2.22)
SYMM
BASED ON
0.125 THICK
STENCIL
8X (0.5)
5
6
(R0.05) TYP
SEE TABLE FOR
SYMM
(4.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
METAL COVERED
BY SOLDER MASK
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.05 X 2.48
1.83 X 2.22 (SHOWN)
1.67 X 2.03
0.125
0.150
0.175
1.55 X 1.88
4226759/A 04/2021
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: SN6507-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN6507DGQRQ1
ACTIVE
HVSSOP
DGQ
10
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
6507
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN6507-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2022
Catalog : SN6507
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
DGQ 10
3 x 3, 0.5 mm pitch
PowerPADTM HVSSOP - 1.1 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224775/A
www.ti.com
PACKAGE OUTLINE
DGQ0010H
PowerPADTM - 1.1 mm max height
S
C
A
L
E
3
.
7
0
0
PLASTIC SMALL OUTLINE
C
5.05
4.75
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.08
C A B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
(0.61)
NOTE 6
(0.17) NOTE 6
(0.2) NOTE 6
(0.08)
NOTE 6
4
5
0.25
GAGE PLANE
2.22
1.92
0.15
0.05
0.7
0.4
8
0 - 8
1
DETAIL A
TYPICAL
1.75
1.45
EXPOSED
THERMAL PAD
4226735/B 05/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.
6. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DGQ0010H
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(2.2)
NOTE 10
(1.75)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED PAD
SEE DETAILS
10X (1.45)
10X (0.3)
1
10
(1.3)
TYP
(2.22)
SOLDER MASK
OPENING
SYMM
(3.1)
NOTE 10
8X (0.5)
6
5
(R0.05) TYP
SYMM
METAL COVERED
BY SOLDER MASK
(
0.2) TYP
VIA
(1.3) TYP
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226735/B 05/2022
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGQ0010H
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(1.75)
BASED ON
0.125 THICK
STENCIL
10X (1.45)
10X (0.3)
1
10
(2.22)
SYMM
BASED ON
0.125 THICK
STENCIL
8X (0.5)
5
6
(R0.05) TYP
SEE TABLE FOR
SYMM
(4.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
METAL COVERED
BY SOLDER MASK
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.100
0.125
0.150
0.175
1.96 X 2.48
1.75 X 2.22 (SHOWN)
1.6 X 2.03
1.48 X 1.88
4226735/B 05/2022
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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