SN65472DEP [TI]
SN65472-EP 双路外设驱动器 | D | 8 | -40 to 85;
| 型号： | SN65472DEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN65472-EP 双路外设驱动器 | D | 8 | -40 to 85 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总12页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65472-EP
www.ti.com.cn
ZHCSBL0 –SEPTEMBER 2013
双路外设驱动器
查询样品: SN65472-EP
1
特性
•
•
•
特别针对高达 300mA 的使用
支持工业应用
高压输出
•
•
•
•
•
•
•
受控基线
55V 时无输出闭锁
（在传到 300mA 电流后）
一个组装和测试场所
一个制造场所
•
•
•
•
中速切换
(1)
支持扩展（-40°C 至 125°C）温度范围
延长的产品生命周期
针对各种应用和逻辑功能选择的电路灵活性
TTL 兼容二极管钳位输入
标准电源电压
延长的产品变更通知
产品可追溯性
D 封装
（顶视图）
1A
1B
V
CC
1
2
3
4
8
7
6
5
2B
2A
2Y
1Y
GND
(1) 可定制工作温度范围
说明/订购信息
SN56472 双路外设驱动器可与系列 SN7452B 和系列 SN75462 进行功能互换，但是被设计用于要求更高击穿电压
的系统。此系统以稍慢于系列 75452B 系列产品的开关速度为代价提供高于这些系列产品所能够提供的击穿电
压（与 系列 SN75462 限值一样）。 典型应用包括高速逻辑缓冲器，电源驱动器，中继驱动器，灯驱动器，MOS
驱动器，线路驱动器和存储器驱动器。
SN65472 是一个双路外设 NAND 驱动器（假定为正逻辑电路），逻辑门的输出在内部被连接至 npn 输出晶体管的
底部。
这个器件的运行温度范围为 -40°C 至 125°C。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SLRS061
SN65472-EP
ZHCSBL0 –SEPTEMBER 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TJ
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
65472
VID NUMBER
V62/13618-01XE-T
V62/13618-01XE
Tape of 75
SN65472DEP
-40°C to 125°C
SOIC − D
Reel of 2500
SN65472DREP
65472
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
LOGIC SYMBOL
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
6
7
3
&
1A
1B
2A
2B
3
5
1
2
1Y
1Y
2Y
1A
1B
5
4
6
7
2Y
2A
2B
This symbol is in accordance with
ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
GND
Table 1. FUNCTION TABLE
(EACH DRIVER)
INPUTS
Y(1)
A
L
B
L
H (Off state)
H (Off state)
H (Off state)
L (On state)
L
H
L
H
H
H
(1) positive logic: Y = AB or A + B
SCHEMATIC (EACH DRIVER)
V
CC
1.6 kΩ
4 kΩ
130 Ω
1.6 kΩ
Y
A
B
500 Ω
1 kΩ
1 kΩ
GND
Resistor values shown are nominal.
2
Copyright © 2013, Texas Instruments Incorporated
SN65472-EP
www.ti.com.cn
ZHCSBL0 –SEPTEMBER 2013
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
7
UNIT
V
VCC
VI
Supply voltage range(2)
Input voltage
Inter-emitter voltage(3)
5.5
5.5
70
V
V
VO
IO
Off-state output voltage
V
Continuous collector or output current(4)
Peak collector or output current (tw ≤ 10 ms, duty cycle ≤ 50%)(4)
Absolute maximum junction temperature range
Storage temperature range
400
500
150
150
mA
mA
°C
°C
TJ
–40
–65
Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage values are with respect to the network GND, unless otherwise specified.
(3) This is the voltage between two emitters, A and B.
(4) Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time
interval must fall within the continuous dissipation rating.
THERMAL INFORMATION
SN65472-EP
THERMAL METRIC(1)
D
8 PINS
115.3
59.7
56.2
13.5
55.6
N/A
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
ψJB
θJCbot
(1) 有关传统和全新热度量的更多信息，请参阅 IC 封装热度量 应用报告 （文献号：ZHCA543）。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的规定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环
境热阻抗。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI 标准 G30-
88 中找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结至电路板的热阻。
(5) 结至顶部的特征参数，( ψJT)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
(6) 结至电路板的特征参数，(ψJB)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI
标准 G30-88 中找到了内容接近的说明。
间距
RECOMMENDED OPERATING CONDITIONS
MIN
4.75
2.1
NOM
MAX
UNIT
V
VCC
VIH
VIL
TA
Supply voltage
5
5.25
High-level input voltage
V
Low-level input voltage
0.8
85
V
Operating free-air temperature range
Operating virtual junction temperature
-40
-40
°C
°C
TJ
125
Copyright © 2013, Texas Instruments Incorporated
3
SN65472-EP
ZHCSBL0 –SEPTEMBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS
These specifications apply for -40°C ≤ TJ ≤ 125°C (unless otherwise noted)
PARAMETER
Input clamp voltage
TEST CONDITIONS
VCC = 4.75 V, II = – 12 mA
MIN
TYP(1)
MAX
UNIT
V
VIK
IOH
-1.2
-1.5
270
0.4
High-level output current
VCC = 4.75 V, VIH = 2 V, VOH = 70 V
VCC = 4.75 V, VIL= 0.8 V, IOL = 100 mA
VCC = 4.75 V, VIL= 0.8 V, IOL = 300 mA
µA
0.25
0.5
VOL
II
Low level output voltage
V
0.75
Input current at maximum input
voltage
VCC = 5.25 V, VI = 5.5 V
1
mA
IIH
High-level input current
Low-level input current
VCC = 5.25 V, VI = 2.4 V
VCC = 5.25 V, VI = 0.4 V
VCC = 5.25 V, VI = 5 V
VCC = 5.25 V, VI = 0
44
-1.6
17
µA
mA
mA
mA
IIL
-1
13
61
ICCH
ICCL
Supply current, outputs high
Supply current, outputs low
76
(1) All typical values are at VCC = 5 V, TA = 25°C.
SWITCHING CHARACTERISTICS
VCC = 5 V, TA = 25°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time,
low-to-high-level output
I
O ≈ 200 mA, CL = 15 pF, RL = 50 Ω,
tPLH
tPHL
tTLH
tTHL
VOH
45
65
ns
see Figure 2
O ≈ 200 mA, CL = 15 pF, RL = 50 Ω,
see Figure 2
O ≈ 200 mA, CL = 15 pF, RL = 50 Ω,
see Figure 2
IO ≈ 200 mA, CL = 15 pF, RL = 50 Ω,
Propagation delay time,
high-to-low-level output
I
30
13
10
50
25
20
ns
ns
Transition time,
low-to-high-level output
I
Transition time,
high-to-low-level output
ns
see Figure 2
High level output voltage after
switching
VS = 55 V, IO ≈ 300 mA,
see Figure 3
VS - 18
mV
4
Copyright © 2013, Texas Instruments Incorporated
SN65472-EP
www.ti.com.cn
ZHCSBL0 –SEPTEMBER 2013
1000000
100000
10000
Wirebond Voiding Fail Mode
1000
80
85
90
95
100 105 110 115 120 125 130 135 140 145 150
Junction Temperature (°C)
(1) See Datasheet for Absolute Maximum and minimum Recommended Operating Conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. SN65472-EP Wirebond Life Derating Chart
Copyright © 2013, Texas Instruments Incorporated
5
SN65472-EP
ZHCSBL0 –SEPTEMBER 2013
www.ti.com.cn
PARAMETER MEASUREMENT INFORMATION
Input
2.4 V
’472
10 V
R
= 50 Ω
L
0.5 µs
≤ 5 ns
≤ 10 ns
Output
3 V
0 V
Pulse
Generator
(see Note A)
90%
50%
90%
50%
Input
’472
Circuit
Under
Test
10%
10%
t
t
PHL
PLH
90%
V
OH
C
= 15 pF
(see Note B)
L
90%
GND SUB
50%
10%
50%
10%
Output
V
OL
t
t
TLH
THL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω.
O
B.
C includes probe and jig capacitance.
L
Figure 2. Switching Times
V
S
= 55 V
2 mH
Input
2.4 V
’472
5 V
40 µs
≤ 10 ns
≤ 5 ns
1N3064
180 Ω
Output
3 V
90%
50%
90%
50%
Input
’472
Pulse
Generator
(see Note A)
10%
10%
0 V
V
Circuit
Under
Test
OH
C
= 15 pF
(see Note B)
Output
L
GND SUB
V
OL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: PRR ≤ 12.5 kHz, Z ≈ 50 Ω.
O
B.
C includes probe and jig capacitance.
L
Figure 3. Latch-Up Test
6
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65472DEP
SN65472DREP
V62/13618-01XE
V62/13618-01XE-T
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
65472
65472
65472
65472
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
75
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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