SN65556FN [TI]
ELECTROLUMINESCENT COLUMIN DRIVERS; 电致发光COLUMIN DRIVERS
| 型号： | SN65556FN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ELECTROLUMINESCENT COLUMIN DRIVERS |
| 文件： | 总9页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLDS031A – APRIL 1985 – REVISED APRIL 1993
SN75555 . . . N PACKAGE
(TOP VIEW)
Each Device Drives 32 Electrodes
90-V Output Voltage Swing Capability
Using Ramped Supply
Q17
Q16
Q18
Q19
Q20
Q21
Q22
1
40
39
38
37
36
15-mA Output Source and Sink Current
Capability
2
Q15
3
High-Speed Serially-Shifted Data Input
Totem-Pole Outputs
Q14
4
Q13
5
Q12
6
35 Q23
Latches on All Driver Outputs
7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Q11
Q24
8
Q10
Q25
description
9
Q9
Q26
The SN65555, SN75555, SN65556, and
SN75556 are monolithic BIDFET† integrated
circuits designed to drive the column electrodes of
an electroluminescent display. The SN65556 and
SN75556 output sequence is reversed from the
SN65555 and SN75555 for ease in printed-circuit-
board layout.
10
11
12
13
14
15
16
17
18
19
20
Q8
Q27
Q7
Q28
Q6
Q29
Q5
Q30
Q4
Q31
Q3
Q32
Q2
OUTPUT ENABLE
DATA IN
Q1
The devices consist of a 32-bit shift register, 32
latches, and 32 output AND gates. Serial data is
entered into the shift register on the low-to-high
transition of CLOCK. When high, LATCHENABLE
transfers the shift register contents to the outputs
of the 32 latches. When OUTPUT ENABLE is
high, all Q outputs are enabled. Data must be
loaded into the latches and OUTPUT ENABLE
SERIAL OUT
CLOCK
GND
LATCH ENABLE
V
V
CC1
CC2
SN65555, SN75555 . . . FN PACKAGE
(TOP VIEW)
must be high before supply voltage V
ramped up.
is
CC2
6
5
4
3
2
1 44 43 42 41 40
39
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
7
Serial data output from the shift register can be
used to cascade shift registers. This output is not
affected by LATCH ENABLE or OUTPUT
ENABLE.
8
38
37
36
35
34
33
9
10
11
12
13
14
15
16
17
The SN65555 and SN65556 are characterized for
operation from –40 C to 85 C. The SN75555 and
SN75556 are characterized for operation from
0 C to 70 C.
32 Q30
31 Q31
30
Q32
NC
29
18 19 20 21 22 23 24 25 26 27 28
NC – No internal connection
† BIDFET – Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.
Copyright 1993, Texas Instruments Incorporated
4–1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SLDS031A – APRIL 1985 – REVISED APRIL 1993
SN65556, SN75556
N PACKAGE
SN65556, SN75556
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
Q16
Q17
Q15
Q14
Q13
Q12
Q11
1
40
39
38
37
36
2
6
5
4
3
2
1 44 43 42 41 40
39
Q18
3
Q10
Q9
Q8
Q7
Q6
Q5
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
7
Q19
4
8
38
37
36
35
34
Q20
5
9
Q21
6
35 Q10
10
11
12
13
14
15
16
17
7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Q22
Q9
8
Q8
Q23
9
Q24
Q7
33 Q4
32 Q3
10
11
12
13
14
15
16
17
18
19
20
Q25
Q6
Q26
Q5
31
30
29
Q2
Q1
NC
Q27
Q4
Q28
Q3
18 19 20 21 22 23 24 25 26 27 28
Q29
Q2
Q30
Q1
Q31
OUTPUT ENABLE
DATA IN
Q32
SERIAL OUT
CLOCK
GND
LATCH ENABLE
V
V
CC1
CC2
NC – No internal connection
†
logic symbols
SN65555, SN75555
CMOS/EL DISP
SN65556, SN75556
CMOS/EL DISP
21
21
V
CC2
V
CC2
[PWR Q1-32]
EN3
C2
[PWR Q1-32]
EN3
C2
25
23
25
23
OUTPUT ENABLE
LATCH ENABLE
OUTPUT ENABLE
LATCH ENABLE
SRG 32
C1/
SRG 32
C1/
19
24
19
24
CLOCK
CLOCK
17
16
26
27
Q1
Q2
DATA IN
2D
2D
2D
2D
1D
Q1
Q2
DATA IN
1D
3
3
3
3
1
40
40
1
Q15
Q16
2D
2D
Q17
Q18
2D
2D
3
3
3
3
27
26
18
16
17
18
2D
2D
Q31
Q32
SERIAL OUT
2D
2D
3
3
3
3
Q31
Q32
SERIAL OUT
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for N packages.
4–2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SLDS031A – APRIL 1985 – REVISED APRIL 1993
logic diagram (positive logic)
V
CC2
OUTPUT
ENABLE
Output
Buffers
LATCH
ENABLE
Shift
Register
Latches
C2
DATA IN
CLOCK
1D
C1
Q1
Q2
LC1
LC2
R1
R2
2D
C2
2D
1D
C1
28 Stages
(Q3 thru Q30)
Not Shown
1D
C1
C2
2D
Q31
LC31
LC32
R31
R32
C2
2D
1D
C1
Q32
SERIAL OUT
FUNCTION TABLE
CONTROL INPUTS
OUTPUTS
Q1 THRU Q32
SHIFT REGISTER
R1 THRU R32
LATCHES
LC1 THRU LC32
FUNCTION
LATCH
OUTPUT
CLOCK
SERIAL
ENABLE ENABLE
†
X
X
X
X
Load and shift
No change
Determined by
LATCH ENABLE
R32
R32
Load
Determined by OUTPUT ENABLE
Determined by OUTPUT ENABLE
‡
No
X
X
L
H
X
X
Stored data
New data
Latch
As determined above
R32
Output
Enable
X
X
X
X
L
H
Determined by
LATCH ENABLE
R32
R32
All L
As determined above
‡
LC1 thru LC21, respectively
H = high level, L = low level, X = irrelevant,
= low-to-high-level transition.
†
R32 and the serial output take on the state of R31, R31 takes on the state of R30,. . .R2 takes on the state of R1, and R1 takes on the state of
the data input.
‡
New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low.
4–3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SLDS031A – APRIL 1985 – REVISED APRIL 1993
typical operating sequence
CLOCK
DATA IN
Valid
Irrelevant
Valid
Invalid
SR Contents
LATCH ENABLE
Latch
Contents
Previously Stored Data
New Data Valid
OUTPUT
ENABLE
V
CC2
Valid
Q Outputs
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Q OUTPUTS
V
TYPICAL OF SERIAL OUTPUT
V
V
CC2
CC1
CC1
Output
Input
GND
Output
GND
GND
4–4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SLDS031A – APRIL 1985 – REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 V
CC1
CC2
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
CC1
+ 0.3 V
I
Ground current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : SN65555, SN65556 . . . . . . . . . . . . . . . . . . . . . . . – 40 C to 85 C
A
SN75555, SN75556 . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260 C
NOTES: 1. Voltage values are with respect to network GND.
2. These devices have been designed to be used in applications in which the high-voltage supply, V
changing the state of the outputs.
, is switched to GND before
CC2
DISSIPATION RATING TABLE
T
25 C
DERATING FACTOR
ABOVE T = 25 C
A
T
= 70 C
T = 85 C
A
A
A
PACKAGE
POWER RATING
POWER RATING POWER RATING
FN
N
1700 mW
13.6 mW/ C
10.0 mW/ C
1088 mW
800 mW
884 mW
650 mW
1250 mW
recommended operating conditions
MIN NOM
MAX
15
UNIT
V
Supply voltage, V
Supply voltage, V
10.8
0
12
CC1
CC2
80
V
V
CC1
V
CC1
V
CC1
V
CC1
= 10.8 V
= 15 V
8.1
11.1
15.3
2.7
High-level input voltage, V (see Figure 1)
IH
V
V
11.25
†
= 10.8 V
= 15 V
– 0.3
Low-level input voltage, V (see Figure 1)
IL
†
–0.3
3.75
–15
15
High-level output current, I
mA
mA
mA
MHz
ns
OH
Low-level output current, I
Output clamp current, I
OL
20
OK
clock
Pulse duration, CLOCK high or low, t
Clock frequency, f
0
80
6.25
(see Figure 2)
w(CLK)
w(LE)
Pulse duration, LATCH ENABLE, t
80
ns
DATA IN before CLOCK (see Figure 2)
OUTPUT ENABLE before V (see Figure 4)
20
Setup time, t
su
ns
500
80
CC2
DATA IN after CLOCK (see Figure 2)
OUTPUT ENABLE after V (see Figure 4)
Hold time, t
ns
V/ s
C
h
100
CC2
Rate of rise for V
dv/dt
80
85
85
CC2,
SN65555, SN65556
SN75555, SN75556
–40
Operating free-air temperature, T
A
0
†
The algebraic convention, in which the least positive (most negative) value is designated as minimum, is used in this data sheet for logic voltage
levels.
4–5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SLDS031A – APRIL 1985 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range, V
CC2
= 12 V,
CC1
V
= 80 V
PARAMETER
TEST CONDITIONS
= –15 mA
MIN
77
MAX
UNIT
Q outputs
I
O
V
High-level output voltage
Low-level output voltage
V
OH
OL
SERIAL OUT
Q outputs
I
= –100
A
10.5
O
I
= 15 mA
8
1
OL
V
V
SERIAL OUT
I
= 100 A
OL
V = 12 V
I
I
I
I
High-level input current
Low-level input current
1
A
A
IH
I
V = 0
I
– 1
2
IL
Supply current from V
Supply current from V
mA
mA
CC1
CC2
CC1
CC2
5
switching characteristics, V
CC1
= 12 V, T = 25 C
A
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Propagation delay time, high-to-low-level,
SERIAL OUT from CLOCK
t
140
ns
PHL
C
= 20 pF to GND,
V
= 0,
CC2
L
See Figure 3
Propagation delay time, low-to-high level,
SERIAL OUT from CLOCK
t
t
140
100
ns
ns
PLH
d
Delay time, V
to Q outputs
dv/dt = 80 V/ s,
See Figure 4
CC2
RECOMMENDED OPERATING CONDITIONS
INPUT VOLTAGE LOGIC-LEVEL LIMITS
vs
SUPPLY VOLTAGE V
CC1
12
10
8
T
A
= Full Range
Minimum V
IH
6
4
2
2
Maximum V
IL
10
11
12
13
14
15
V
– Supply Voltage – V
CC1
Figure 1
4–6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SLDS031A – APRIL 1985 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
t
w(CLK)
V
V
IH
CLOCK
50%
50%
50%
IL
t
w(CLK)
t
t
h
su
V
V
IH
DATA IN
Valid
IL
Figure 2. Input Timing Voltage Waveforms
V
V
IH
CLOCK
50%
IL
t
PLH
V
OH
V
OL
V
OH
50%
SERIAL OUT
t
PHL
SERIAL OUT
50%
V
OL
Figure 3. Voltage Waveforms for Propagation Delay Time, CLOCK to SERIAL OUT
V
V
IH
IL
OUTPUT
ENABLE
50%
50%
80 V
0 V
t
su
t
h
V
CC2
10%
10%
t
d
V
OH
OL
Valid
Q Output
10%
V
Figure 4. Voltage Waveforms for Delay Times, V
CC2
to Q Outputs
4–7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
4–8
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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