SN65C1167 [TI]

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS; 双路差动驱动器和接收
SN65C1167
型号: SN65C1167
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
双路差动驱动器和接收

驱动器
文件: 总14页 (文件大小:287K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢈ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅꢂ ꢈ  
ꢉꢊꢋ ꢌ ꢉꢍ ꢎꢎ ꢏꢐ ꢏꢁꢑ ꢍꢋ ꢌ ꢉꢐꢍ ꢒꢏ ꢐꢀ ꢋꢁꢉ ꢐꢏ ꢄꢏ ꢍ ꢒꢏ ꢐ ꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
SN65C1167 . . . DB OR NS PACKAGE  
SN75C1167 . . . DB, N, OR NS PACKAGE  
(TOP VIEW)  
D
Meet or Exceed Standards TIA/EIA-422-B  
and ITU Recommendation V.11  
D
BiCMOS Process Technology  
V
1B  
1A  
D
Low Supply-Current Requirements:  
9 mA Max  
1
2
3
4
5
6
7
8
16  
15  
14  
CC  
1D  
1Y  
1R  
D
D
D
D
Low Pulse Skew  
13 1Z  
12 DE  
RE  
2R  
Receiver Input Impedance . . . 17 kTyp  
Receiver Input Sensitivity . . . 200 mV  
11  
10  
9
2Z  
2Y  
2D  
2A  
Receiver Common-Mode Input Voltage  
Range of −7 V to 7 V  
2B  
GND  
D
Operate From Single 5-V Power Supply  
SN65C1168 . . . N, NS, OR PW PACKAGE  
SN75C1168 . . . DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Glitch-Free Power-Up/Power-Down  
Protection  
D
D
Receiver 3-State Outputs Active-Low  
Enable for SN65C1167 and SN75C1167 Only  
V
1B  
1A  
1
2
3
4
5
6
7
8
16  
15  
14  
CC  
Improved Replacements for the MC34050  
and MC34051  
1D  
1Y  
1R  
13 1Z  
1DE  
2R  
description/ordering information  
12 2DE  
11  
10  
9
2Z  
2Y  
2D  
2A  
The SN65C1167, SN75C1167, SN65C1168,  
and SN75C1168 dual drivers and receivers are  
integrated circuits designed for balanced  
2B  
GND  
transmission  
lines.  
The  
devices  
meet  
TIA/EIA-422-B and ITU recommendation V.11.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
PDIP (N)  
Tube  
SN75C1167N  
SN75C1167N  
75C1167  
SOP (NS)  
SSOP (DB)  
PDIP (N)  
Tape and reel  
Tape and reel  
Tube  
SN75C1167NSR  
SN75C1167DBR  
SN75C1168N  
CA1167  
SN75C1168N  
75C1168  
0°C to 70°C  
SOP (NS)  
SSOP (DB)  
Tape and reel  
Tape and reel  
Tube  
SN75C1168NSR  
SN75C1168DBR  
SN75C1168PW  
SN75C1168PWR  
SN65C1167NSR  
SN65C1167DBR  
SN65C1168N  
CA1168  
TSSOP (PW)  
CA1168  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP (NS)  
SSOP (DB)  
PDIP (N)  
65C1167  
CB1167  
SN65C1168N  
65C1168  
−40°C to 85°C  
SOP (NS)  
Tape and reel  
Tube  
SN65C1168NSR  
SN65C1168PW  
SN65C1168PWR  
TSSOP (PW)  
CB1168  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢓꢙ ꢘ ꢤꢟꢞ ꢜ ꢝ ꢞ ꢘꢖ ꢗꢘ ꢙ ꢚ ꢜ ꢘ ꢝ ꢡꢠ ꢞ ꢕꢗ ꢕꢞꢛ ꢜꢕ ꢘꢖꢝ ꢡꢠ ꢙ ꢜꢦ ꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢑꢠꢧ ꢛꢝ ꢍꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ  
ꢝ ꢜ ꢛ ꢖꢤ ꢛ ꢙꢤ ꢨ ꢛ ꢙꢙ ꢛ ꢖ ꢜꢩꢥ ꢓꢙ ꢘ ꢤꢟꢞ ꢜꢕꢘꢖ ꢡꢙ ꢘꢞ ꢠꢝ ꢝꢕ ꢖꢪ ꢤꢘꢠ ꢝ ꢖꢘꢜ ꢖꢠ ꢞꢠ ꢝꢝ ꢛꢙ ꢕꢣ ꢩ ꢕꢖꢞ ꢣꢟꢤ ꢠ  
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅꢅ ꢂꢆ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢈꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢈ  
ꢉ ꢊꢋꢌ ꢉ ꢍ ꢎ ꢎ ꢏꢐ ꢏꢁꢑ ꢍ ꢋꢌ ꢉꢐ ꢍ ꢒꢏ ꢐꢀ ꢋꢁ ꢉ ꢐꢏ ꢄꢏꢍꢒ ꢏꢐꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
description/ordering information (continued)  
The SN65C1167 and SN75C1167 combine dual 3-state differential line drivers and 3-state differential line  
receivers, both of which operate from a single 5-V power supply. The driver and receiver have active-high and  
active-low enables, respectively, which can be connected together externally to function as direction control.  
The SN65C1168 and SN75C1168 drivers have individual active-high enables.  
Function Tables  
EACH DRIVER  
OUTPUTS  
INPUT  
D
ENABLE  
DE  
Y
H
L
Z
L
H
L
H
H
L
H
Z
X
Z
SN75C1167, EACH RECEIVER  
DIFFERENTIAL INPUTS  
A − B  
ENABLE OUTPUT  
RE  
R
H
?
V
0.2 V  
L
ID  
−0.2 V < V < 0.2 V  
L
ID  
V
ID  
−0.2 V  
L
L
X
H
L
Z
H
Open  
H = high level, L = low level, ? = indeterminate,  
X = irrelevant, Z = high impedance (off)  
logic diagram (positive logic)  
SN65C1167/SN75C1167  
12  
SN65C1168, SN75C1168  
4
DE  
RE  
1DE  
1D  
14  
1Y  
1Z  
1A  
1B  
15  
4
13  
2
14  
3
1Y  
1Z  
15  
3
1
1R  
2DE  
2D  
1D  
13  
12  
9
10  
11  
6
2
1
2Y  
2Z  
2A  
2B  
1A  
1B  
1R  
2D  
2R  
10  
11  
5
2Y  
2Z  
9
2R  
7
6
7
2A  
2B  
5
2
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ꢉꢊꢋ ꢌ ꢉꢍ ꢎꢎ ꢏꢐ ꢏꢁꢑ ꢍꢋ ꢌ ꢉꢐꢍ ꢒꢏ ꢐꢀ ꢋꢁꢉ ꢐꢏ ꢄꢏ ꢍ ꢒꢏ ꢐ ꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
schematics of inputs  
EQUIVALENT OF DRIVER ENABLE INPUT  
EQUIVALENT OF A OR B INPUT  
V
CC  
V
CC  
17 kΩ  
NOM  
1.7 kΩ  
NOM  
Input  
Input  
288 kΩ  
NOM  
1.7 kΩ  
NOM  
V
(A)  
CC  
or  
GND (B)  
GND  
GND  
schematics of outputs  
TYPICAL OF EACH DRIVER OUTPUT  
TYPICAL OF EACH RECEIVER OUTPUT  
V
V
CC  
CC  
Output  
Output  
GND  
GND  
3
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ꢉ ꢊꢋꢌ ꢉ ꢍ ꢎ ꢎ ꢏꢐ ꢏꢁꢑ ꢍ ꢋꢌ ꢉꢐ ꢍ ꢒꢏ ꢐꢀ ꢋꢁ ꢉ ꢐꢏ ꢄꢏꢍꢒ ꢏꢐꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
I
CC  
Input voltage range, V (A or B, Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V to 14 V  
I
Differential input voltage range, V , Receiver (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −14 V to 14 V  
ID  
Output voltage range, V , Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 7 V  
O
Clamp current range, I or I , Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
IK  
OK  
Output current range, I , Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA  
O
Supply current, I  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA  
CC  
GND current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200 mA  
Output current range, I , Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA  
O
Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
Package thermal impedance, θ (see Notes 3 and 4): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W  
JA  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values except differential input voltage are with respect to the network GND.  
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.  
3. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable  
J
JA  
A
ambient temperature is P = (T (max) − T )/θ . Selecting the maximum of 150°C can affect reliability.  
D
J
A
JA  
4. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
V
Supply voltage  
4.5  
5
5.5  
V
CC  
Common-mode input voltage  
(see Note 5)  
Receiver  
7
7
V
IC  
V
ID  
V
IH  
V
IL  
Differential input voltage  
High-level input voltage  
Low-level input voltage  
Receiver  
Except A, B  
Except A, B  
Receiver  
Driver  
V
V
V
2
0.8  
−6  
−20  
6
I
I
High-level output current  
Low-level output current  
Operating free-air temperature  
mA  
mA  
°C  
OH  
OL  
Receiver  
Driver  
20  
70  
85  
SN75C1167, SN75C1168  
SN65C1167, SN65C1168  
0
T
A
−40  
NOTE 5: Refer to TIA/EIA-422-B for exact conditions.  
4
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ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢈ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅꢂ ꢈ  
ꢉꢊꢋ ꢌ ꢉꢍ ꢎꢎ ꢏꢐ ꢏꢁꢑ ꢍꢋ ꢌ ꢉꢐꢍ ꢒꢏ ꢐꢀ ꢋꢁꢉ ꢐꢏ ꢄꢏ ꢍ ꢒꢏ ꢐ ꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
DRIVER SECTION  
electrical characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted)  
PARAMETER  
Input clamp voltage  
TEST CONDITIONS  
MIN TYP  
MAX  
UNIT  
V
V
V
I = −18 mA  
−1.5  
V
V
V
V
V
IK  
I
High-level output voltage  
Low-level output voltage  
Differential output voltage  
Differential output voltage  
V
= 2 V,  
= 2 V,  
V
V
= 0.8 V,  
= 0.8 V,  
I
I
= −20 mA  
= 20 mA  
2.4  
3.4  
0.2  
OH  
OL  
IH  
IH  
IL  
OH  
V
0.4  
6
IL  
OL  
|V  
|V  
|
|
I
O
= 0 mA  
2
2
OD1  
3.1  
OD2  
Change in magnitude of differential  
output voltage  
|V  
|
0.4  
3
V
V
V
OD  
R
= 100 , See Figure 1 and Note 5  
L
V
OC  
Common-mode output voltage  
Change in magnitude of common-mode  
output voltage  
|V  
|
0.4  
OC  
V
V
= 6 V  
100  
−100  
20  
µA  
µA  
O
I
Output current with power off (see Note 3)  
High-impedance-state output current  
V
= 0 V  
O(OFF)  
CC  
= −0.25 V  
O
V
V
= 2.5 V  
= 5 V  
O
I
µA  
OZ  
−20  
1
O
I
I
I
High-level input current  
Low-level input current  
Short-circuit output current  
V = V  
I CC  
or V  
IH  
µA  
µA  
IH  
V = GND or V  
IL  
−1  
IL  
I
V
= V  
or GND,  
See Note 6  
or GND  
−30  
−150  
6
mA  
OS  
O CC  
V = V  
I
4
5
6
No load,  
Enabled  
CC  
I
Supply current (total package)  
Input capacitance  
mA  
pF  
CC  
V = 2.4 or 0.5 V, See Note 7  
I
9
C
i
All typical values are at V  
CC  
= 5 V and T = 25°C.  
A
NOTES: 5. Refer to TIA/EIA-422-B for exact conditions.  
6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.  
7. This parameter is measured per input, while the other inputs are at V or GND.  
CC  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX  
12  
UNIT  
ns  
t
t
t
Propagation delay time, high- to low-level output  
Propagation delay time, low- to high-level output  
Pulse skew  
7
7
PHL  
PLH  
sk(p)  
R
C
= R = 50 ,  
R
= 500 ,  
3
1
1
2
2
12  
ns  
= C = C = 40 pF,  
S1 is open,  
3
See Figure 2  
0.5  
5
4
ns  
R
C
= R = 50 ,  
R
= 500 ,  
3
t
t
t
t
t
t
Rise time  
10  
10  
19  
19  
16  
16  
ns  
ns  
ns  
ns  
ns  
ns  
1
1
2
2
r
= C = C = 40 pF,  
S1 is open,  
R = 500 ,  
3
3
Fall time  
5
See Figure 3  
f
R
C
= R = 50 ,  
Output enable time to high level  
Output enable time to low level  
Output disable time from low level  
Output disable time from high level  
10  
10  
7
1
1
2
2
PZH  
PZL  
PHZ  
PLZ  
= C = C = 40 pF,  
S1 is closed,  
R = 500 ,  
3
3
See Figure 4  
R
C
= R = 50 ,  
1
1
2
2
= C = C = 40 pF,  
S1 is closed,  
3
7
See Figure 4  
All typical values are at V  
CC  
= 5 V and T = 25°C.  
A
5
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ꢉ ꢊꢋꢌ ꢉ ꢍ ꢎ ꢎ ꢏꢐ ꢏꢁꢑ ꢍ ꢋꢌ ꢉꢐ ꢍ ꢒꢏ ꢐꢀ ꢋꢁ ꢉ ꢐꢏ ꢄꢏꢍꢒ ꢏꢐꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
RECEIVER SECTION  
electrical characteristics over recommended ranges of common-mode input voltage, supply  
voltage, and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX  
UNIT  
Positive-going input threshold voltage,  
differential input  
V
V
0.2  
V
IT+  
Negative-going input threshold voltage,  
differential input  
−0.2  
V
IT−  
V
V
V
V
Input hysteresis (V  
IT+  
− V  
)
60  
mV  
V
hys  
IT−  
Input clamp voltage, RE  
High-level output voltage  
Low-level output voltage  
SN75C1167 I = −18 mA  
−1.5  
IK  
I
V
= 200 mV,  
I
I
= −6 mA  
= 6 mA  
3.8  
4.2  
0.1  
V
OH  
OL  
ID  
ID  
OH  
V
= −200 mV,  
0.3  
5
V
OL  
High-impedance-state output  
current  
I
SN75C1167  
V
O
= V  
CC  
or GND  
0.5  
µA  
OZ  
V = 10 V  
1.5  
−2.5  
1
I
I
I
Line input current  
Other input at 0 V  
mA  
I
V = −10 V  
I
Enable input current, RE  
Input resistance  
SN75C1167 V = V  
or GND  
= −7 V to 7 V,  
IC  
µA  
kΩ  
I
I
CC  
r
V
Other input at 0 V  
4
17  
4
i
V = V  
or GND  
= 2.4 V or 0.5 V,  
6
9
I
CC  
I
Supply current (total package)  
No load, Enabled  
mA  
V
CC  
IH  
See Note 5  
5
All typical values are at V  
CC  
= 5 V and T = 25°C.  
A
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode  
input voltage and threshold voltage levels only.  
NOTE 5: Refer to TIA/EIA-422-B for exact conditions.  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted) (see Note 8)  
PARAMETER  
Propagation delay time, low- to high-level output  
Propagation delay time, high- to low-level output  
Transition time, low- to high-level output  
Transition time, high- to low-level output  
Output enable time to high level  
TEST CONDITIONS  
MIN TYP  
MAX  
27  
27  
9
UNIT  
ns  
t
t
t
t
t
t
t
t
9
9
17  
17  
4
PLH  
PHL  
TLH  
THL  
PZH  
PZL  
PHZ  
PLZ  
See Figure 5  
ns  
ns  
V
= 0 V,  
See Figure 5  
IC  
4
9
ns  
13  
13  
13  
13  
22  
22  
22  
22  
ns  
Output enable time to low level  
ns  
R
= 1 kW, See Figure 6  
L
Output disable time from high level  
Output disable time from low level  
ns  
ns  
All typical values are at V  
CC  
= 5 V and T = 25°C.  
A
NOTE 8: Measured per input while the other inputs are at V  
or GND  
CC  
6
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ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢈ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅꢂ ꢈ  
ꢉꢊꢋ ꢌ ꢉꢍ ꢎꢎ ꢏꢐ ꢏꢁꢑ ꢍꢋ ꢌ ꢉꢐꢍ ꢒꢏ ꢐꢀ ꢋꢁꢉ ꢐꢏ ꢄꢏ ꢍ ꢒꢏ ꢐ ꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
PARAMETER MEASUREMENT INFORMATION  
R
L
2
V
OD2  
R
L
V
OC  
2
Figure 1. Driver Test Circuit, V  
and V  
OC  
OD  
3 V  
0 V  
Input  
(see Note B)  
1.3 V  
1.3 V  
t
t
Y
Z
PLH  
PHL  
V
V
OH  
R1  
R2  
C2  
C3  
50%  
1.3 V  
50%  
1.3 V  
R3  
Y
Input  
1.5 V  
C1  
OL  
S1  
t
t
sk(p)  
sk(p)  
V
V
OH  
50%  
1.3 V  
50%  
1.3 V  
Z
See Note A  
OL  
t
t
PLH  
PHL  
TEST CIRCUIT  
NOTES: A. C1, C2, and C3 include probe and jig capacitance.  
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t = t 6 ns.  
VOLTAGE WAVEFORMS  
r
f
Figure 2. Driver Test Circuit and Voltage Waveforms  
3 V  
0 V  
Input  
(see Note B)  
R1  
C2  
C3  
R3  
V
OD  
Input  
1.5 V  
Differential  
Output  
C1  
S1  
90%  
10%  
90%  
10%  
R2  
t
t
f
r
See Note A  
VOLTAGE WAVEFORMS  
TEST CIRCUIT  
NOTES: A. C1, C2, and C3 include probe and jig capacitance.  
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t = t 6 ns.  
r
f
Figure 3. Driver Test Circuit and Voltage Waveforms  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅꢅ ꢂꢆ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢆꢇ ꢀ ꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢈꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢈ  
ꢉ ꢊꢋꢌ ꢉ ꢍ ꢎ ꢎ ꢏꢐ ꢏꢁꢑ ꢍ ꢋꢌ ꢉꢐ ꢍ ꢒꢏ ꢐꢀ ꢋꢁ ꢉ ꢐꢏ ꢄꢏꢍꢒ ꢏꢐꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
PARAMETER MEASUREMENT INFORMATION  
3 V  
0 V  
Input DE  
1.3 V  
1.5 V  
R1  
R3  
C2  
C3  
t
t
PLZ  
PZL  
0 V  
or  
1.5 V  
1.5 V  
C1  
Output  
S1  
V
OL  
+ 0.3 V  
− 0.3 V  
0.8 V  
3 V  
R2  
V
V
OL  
t
t
PHZ  
PZH  
Pulse  
Generator  
DE  
OH  
See Note A  
V
50 Ω  
2 V  
Output  
OL  
See Note B  
1.5 V  
TEST CIRCUIT  
NOTES: A. C1, C2, and C3 include probe and jig capacitance.  
VOLTAGE WAVEFORMS  
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t = t 6 ns.  
r
f
Figure 4. Driver Test Circuit and Voltage Waveforms  
V
CC  
S1  
t
t
THL  
TLH  
V
OH  
Output  
(see Note B)  
90%  
50%  
90%  
10%  
50%  
10%  
V
OL  
R
L
t
t
PHL  
PLH  
A Input  
B Input  
Device  
Under  
Test  
2.5 V  
0 V  
−2.5 V  
B Input  
A Input = 0 V  
C
= 50 pF  
L
(see Note A)  
TEST CIRCUIT  
C includes probe and jig capacitance.  
L
VOLTAGE WAVEFORMS  
NOTES: A.  
B. The pulse generator has the following characteristics: PRR 1 MHz, duty cycle = 50%, t = t 6 ns.  
r
f
Figure 5. Receiver Test Circuit and Voltage Waveforms  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅ ꢂ ꢆ ꢇ ꢀꢁꢂ ꢃ ꢄꢅꢅ ꢂ ꢈ ꢇ ꢀꢁ ꢆꢃ ꢄꢅꢅꢂ ꢈ  
ꢉꢊꢋ ꢌ ꢉꢍ ꢎꢎ ꢏꢐ ꢏꢁꢑ ꢍꢋ ꢌ ꢉꢐꢍ ꢒꢏ ꢐꢀ ꢋꢁꢉ ꢐꢏ ꢄꢏ ꢍ ꢒꢏ ꢐ ꢀ  
SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003  
PARAMETER MEASUREMENT INFORMATION  
3 V  
0 V  
RE Input  
1.3 V  
1.3 V  
V
CC  
S1  
0.5 V  
t
t
t
PLZ  
PZL  
V
CC  
Output  
Output  
50%  
V
OL  
RE Input  
R
L
t
PHZ  
PZH  
Device  
Under  
Test  
V
OH  
V
ID  
= −2.5 V  
or 2.5 V  
50%  
C
= 50 pF  
(see Note A)  
L
GND  
0.5 V  
Measurement: S1 to V  
t
, t  
PZL PLZ  
CC  
t
, t  
Measurement: S1 to GND  
PZH PHZ  
TEST CIRCUIT  
VOLTAGE WAVEFORMS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. The pulse generator has the following characteristics: PRR 1 MHz, duty cycle = 50%, t = t 6 ns.  
r
f
Figure 6. Receiver Test Circuit and Voltage Waveforms  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL  
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002  
N (R-PDIP-T**)  
PLASTIC DUAL-IN-LINE PACKAGE  
16 PINS SHOWN  
PINS **  
14  
16  
18  
20  
DIM  
0.775  
0.775  
0.920  
1.060  
A MAX  
A
(19,69) (19,69) (23,37) (26,92)  
16  
9
0.745  
0.745  
0.850  
0.940  
A MIN  
(18,92) (18,92) (21,59) (23,88)  
MS-100  
VARIATION  
0.260 (6,60)  
0.240 (6,10)  
AA  
BB  
AC  
AD  
C
1
8
0.070 (1,78)  
0.045 (1,14)  
D
0.045 (1,14)  
0.325 (8,26)  
0.300 (7,62)  
0.020 (0,51) MIN  
D
0.030 (0,76)  
0.015 (0,38)  
Gauge Plane  
0.200 (5,08) MAX  
Seating Plane  
0.010 (0,25) NOM  
0.125 (3,18) MIN  
0.100 (2,54)  
0.430 (10,92) MAX  
0.021 (0,53)  
0.015 (0,38)  
0.010 (0,25)  
M
14/18 PIN ONLY  
20 pin vendor option  
D
4040049/E 12/2002  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).  
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
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