SN65C1406_15 [TI]
TRIPLE LOW-POWER DRIVERS/RECEIVERS;
| 型号： | SN65C1406_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE LOW-POWER DRIVERS/RECEIVERS 驱动 |
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SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
SN65C1406 . . . D PACKAGE
SN75C1406 . . . D, DW, N, OR NS PACKAGE
(TOP VIEW)
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Very Low Power Consumption . . .
5 mW Typ
V
V
1
2
3
4
5
6
7
8
16
15
14
CC
DD
1RY
1DA
1RA
1DY
2RA
2DY
3RA
3DY
Wide Driver Supply Voltage Range . . .
±4.5 V to ±15 V
13 2RY
12 2DA
Driver Output Slew Rate Limited to
30 V/µs Max
11
10
9
3RY
3DA
GND
Receiver Input Hysteresis . . . 1000 mV Typ
Push-Pull Receiver Outputs
V
SS
On-Chip Receiver 1-µs Noise Filter
Functionally Interchangeable With Motorola
MC145406 and Texas Instruments
TL145406
Package Options Include Plastic
Small-Outline (D, DW, NS) Packages and
DIPs (N)
description
The SN65C1406 and SN75C1406 are low-power BiMOS devices containing three independent drivers and
receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment
(DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1406
and SN75C1406 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver,
respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs, and the
receivers have filters that reject input noise pulses shorter than 1 µs. Both these features eliminate the need
for external components.
The SN65C1406 and SN75C1406 are designed using low-power techniques in a BiMOS technology. In most
applications, the receivers contained in these devices interface to single inputs of peripheral devices such as
ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the
transition times of the input signals. If this is not the case, or for other uses, it is recommended that the
SN65C1406 and SN75C1406 receiver outputs be buffered by single Schmitt input gates or single gates of the
HCMOS, ALS, or 74F logic families.
The SN65C1406 is characterized for operation from –40°C to 85°C. The SN75C1406 is characterized for
operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
OUTLINE
(D)
SMALL
OUTLINE
(DW)
PLASTIC
DIP
PLASTIC
SMALL OUTLINE
(NS)
T
A
(N)
–40°C to 85°C
0°C to 70°C
SN65C1406D
—
—
—
SN75C1406D SN75C1406DW SN75C1406N
SN75C1406NS
The D, DW, and PW packages are available taped and reeled. Add the suffix R to device type
(e.g., SN75C1406DR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
logic diagram (positive logic)
Typical of Each Receiver
2, 4, 6
RA
15, 13, 11
14, 12, 10
RY
DA
Typical of Each Driver
3, 5, 7
DY
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
schematics of inputs and outputs
EQUIVALENT DRIVER INPUT
EQUIVALENT DRIVER OUTPUT
VDD
V
DD
Internal
1.4-V Reference
Input
DA
160 Ω
Output
DY
74 Ω
V
SS
GND
72 Ω
V
SS
EQUIVALENT RECEIVER INPUT
EQUIVALENT RECEIVER OUTPUT
V
CC
3.4 kΩ
Input
RA
Output
RY
1.5 kΩ
ESD
ESD
Protection
Protection
530 Ω
GND
GND
All resistor values shown are nominal.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage: V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
SS
CC
V
V
Input voltage range, V : Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to V
I
SS
DD
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V
Output voltage range, V : Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V – 6 V) to (V + 6 V)
O
SS
DD
CC
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
+ 0.3 V)
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150 °C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN NOM
MAX
15
UNIT
V
DD
V
SS
V
CC
Supply voltage
Supply voltage
Supply voltage
4.5
–4.5
4.5
12
–12
5
V
V
V
–15
6
Driver
V +2
SS
V
DD
V
I
Input voltage
V
Receiver
±25
V
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output curren
2
V
V
IH
0.8
–1
3.2
85
70
IL
I
I
mA
mA
OH
OL
SN65C1406
SN75C1406
–40
T
A
Operating free-air temperature
°C
0
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
DRIVER SECTION
electrical characteristics over operating free-air temperature range, V
CC
= 12 V, V
= –12 V,
DD
SS
V
= 5 V ± 10% (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
4
MAX
UNIT
TYP
R
R
= 3 kΩ,
V
DD
V
DD
V
DD
V
DD
= 5 V,
V
SS
V
SS
V
SS
V
SS
= –5 V
= –12 V
= –5 V
= –12 V
4.5
10.8
V
= 0.8 V,
L
L
IH
See Figure 1
V
OH
High-level output voltage
V
= 12 V,
= 5 V,
10
= 3 kΩ,
–4.4
–4
Low-level output voltage
(see Note 3)
V
= 2 V,
IH
See Figure 1
V
OL
V
= 12 V,
–10.7
–10
1
I
I
High-level input current
Low-level input current
High-level short-circuit
V = 5 V,
I
See Figure 2
See Figure 2
µA
µA
IH
V = 0,
I
–1
IL
I
V = 0.8 V,
I
V
= 0 or V
= 0 or V
,
SS
See Figure 1
See Figure 1
–7.5
–12 –19.5
mA
mA
OS(H)
O
O
‡
output current
Low-level short-circuit
I
V = 2 V,
I
V
,
DD
7.5
12
19.5
OS(L)
DD
‡
output current
V
V
V
V
V
= 5 V,
V
V
V
V
= –5 V
= –12 V
= –5 V
= –12 V
115
115
250
250
No load,
All inputs at 2 V or 0.8 V
DD
DD
DD
DD
SS
SS
SS
SS
I
I
Supply current from V
µA
DD
= 12 V,
= 5 V,
–115
–115
–250
–250
No load,
All inputs at 2 V or 0.8 V
Supply current from V
Output resistance
µA
SS
SS
= 12 V,
V
= V
= V
= 0,
= –2 V to 2 V,
O
DD
SS
CC
r
300
400
Ω
O
See Note 4
†
‡
All typical values are at T = 25°C.
Not more than one output should be shorted at a time.
A
NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
4. Test conditions are those specified by TIA/EIA-232-F.
switching characteristics at T = 25°C, V
= 12 V, V = –12 V, V
= 5 V ± 10%
CC
A
DD
SS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
= 3 kΩ to 7 kΩ, C = 15 pF,
L
L
§
§
t
t
t
t
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
1.2
2.5
2
3
µs
PLH
PHL
TLH
THL
TLH
THL
See Figure 3
R
= 3 kΩ to 7 kΩ, C = 15 pF,
L
L
3.5
3.2
3.2
2
µs
µs
See Figure 3
R
= 3 kΩ to 7 kΩ, C = 15 pF,
L
L
¶
¶
#
#
Transition time, low- to high-level output
Transition time, high- to low-level output
Transition time, low- to high-level output
Transition time, high- to low-level output
Output slew rate
0.53
0.53
See Figure 3
R
= 3 kΩ to 7 kΩ, C = 15 pF,
L
L
2
µs
See Figure 3
R
= 3 kΩ to 7 kΩ, C = 2500 pF,
L
L
1
µs
See Figure 3
R
= 3 kΩ to 7 kΩ, C = 2500 pF,
L
L
1
2
µs
See Figure 3
R
= 3 kΩ to 7 kΩ, C = 15 pF,
L
L
SR
4
10
30
V/µs
See Figure 3
§
¶
#
t
and t
include the additional time due to on-chip slew rate and are measured at the 50% points.
PHL
PLH
Measured between 10% and 90% points of output waveform
Measured between 3-V and –3-V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
RECEIVER SECTION
electrical characteristics over operating free-air temperature range, V
= 12 V, V = –12 V,
DD
SS
V
= 5 V ± 10% (unless otherwise noted)
CC
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Positive-going input
See Figure 5
V
1.7
2
2.55
V
IT+
IT–
hys
threshold voltage
Negative-going input
See Figure 5
V
0.65
600
1
1.25
V
threshold voltage
Input hysteresis voltage
V
1000
mV
(V )
–V
IT+ IT–
V = 0.75 V,
I
I
= –20 µA, See Figure 5 and Note 5
3.5
2.8
3.8
4.3
I
OH
V
CC
V
CC
V
CC
= 4.5 V
= 5 V
4.4
4.9
V
V
High-level output voltage
V
OH
V = 0.75 V,
I
See Figure 5
= –1 mA,
OH
= 5.5 V
5.4
Low-level output voltage
High-level input current
V = 3 V,
I
= 3.2 mA,
See Figure 5
0.17
4.6
0.4
8.3
1
V
OL
I
OL
V = 2.5 V
I
3.6
0.43
–3.6
I
IH
mA
V = 3 V
I
0.55
–5
V = –2.5 V
I
–8.3
–1
I
I
I
I
Low-level input current
mA
mA
mA
µA
IL
V = –3 V
I
–0.43 –0.55
High-level short-circuit
output current
V = 0.75 V,
I
V
V
= 0,
See Figure 4
See Figure 4
–8
–15
OS(H)
OS(L)
CC
O
Low-level short-circuit
output current
V = V
I CC
,
= V
,
CC
13
25
O
V
V
= 5 V,
V
V
= –5 V
320
320
450
450
No load,
All inputs at 0 or 5 V
DD
SS
Supply current from V
CC
= 12 V,
= –12 V
DD
SS
†
All typical values are at T = 25°C.
A
NOTE 5: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs remain in the high state.
switching characteristics at T = 25°C, V
= 12 V, V = –12 V, V
= 5 V ± 10% (unless otherwise
A
DD
SS
CC
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C
= 50 pF,
R
R
R
R
R
= 5 kΩ,
= 5 kΩ,
= 5 kΩ,
= 5 kΩ,
= 5 kΩ
L
L
L
L
L
L
t
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
3
4
µs
PLH
PHL
TLH
See Figure 6
C
= 50 pF,
L
3
300
100
4
µs
See Figure 6
C
= 50 pF,
L
‡
Transition time, low- to high-level output
Transition time, high- to low-level output
450
ns
See Figure 6
C
= 50 pF,
L
‡
t
t
300
4
ns
THL
See Figure 6
§
Duration of longest pulse rejected as noise
C
= 50 pF,
1
µs
w(N)
L
‡
§
Measured between 10% and 90% points of output waveform
Thereceiverignoresanypositive-ornegative-goingpulsethatislessthantheminimumvalueoft
w(N
)andacceptsanypositive-ornegative-going
pulse greater than the maximum of t
.
w(N)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
I
OS(L)
V
DD
V
V
V
or GND
or GND
DD
V
DD
CC
–I
OS(H)
V
CC
I
IH
SS
V
I
V
V
I
–I
IL
V
O
R
= 3 kΩ
L
I
V
SS
V
SS
Figure 1. Driver Test Circuit
Figure 2. Driver Test Circuit, I , I
V
, V , I
, I
IL IH
OH OL OS(L) OS(H)
V
DD
3 V
0 V
Input
V
CC
1.5
1.5
Input
Pulse
Generator
(See Note B)
t
t
PHL
PLH
90%
V
OH
90%
R
C
L
L
50%
10%
50%
10%
(see Note A)
Output
V
OL
V
SS
t
t
TLH
THL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A.
C includes probe and jig capacitance.
L
B. The pulse generator has the following characteristics: t = 25 µs, PRR = 20 kHz, Z = 50 Ω, t = t < 50 ns.
w
O
r
f
Figure 3. Driver Test Circuit and Voltage Waveforms
V
DD
V
DD
V
CC
–I
OS(H)
V
CC
V , V
IT
V
I
I
–I
OH
I
V
OH
OS(L)
V
OL
I
OL
V
CC
V
SS
V
SS
Figure 4. Receiver Test Circuit, I
, I
Figure 5. Receiver Test Circuit, V , V , V
OS(H) OS(L)
IT OL OH
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1406, SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
SLLS148E – MAY 1990 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
4 V
0 V
V
DD
Input
50%
50%
V
Input
CC
Pulse
Generator
(See Note B)
t
t
PHL
PLH
90%
V
OH
90%
C
R
L
L
50%
10%
50%
10%
(see Note A)
Output
V
OL
t
V
SS
t
TLH
THL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: C.
C includes probe and jig capacitance.
L
D. The pulse generator has the following characteristics: t = 25 µs, PRR = 20 kHz, Z = 50 Ω, t = t < 50 ns.
w
O
r
f
Figure 6. Receiver Test Circuit and Voltage Waveforms
APPLICATION INFORMATION
The TIA/EIA-232-F specification is for data interchange between a host computer and a peripheral at signaling rates
up to 20 kbit/s. Many TIA/EIA-232-F devices will operate at higher data rates with lower capacitive loads (short
cables). For reliable operation at greater than 20 kbit/s, the designer needs to have control of both ends of the cable.
By mixing different types of TIA/EIA-232-F devices and cable lengths, errors can occur at higher frequencies (above
20 kbit/s). When operating within the TIA/EIA-232-F requirements of less than 20 kbit/s and with compliant line
circuits, interoperability is assured. For applications operating above 20 kbit/s, the design engineer should consider
devices and system designs that meet the TIA/EIA-232-F requirements.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2006
PACKAGING INFORMATION
Orderable Device
SN65C1406D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65C1406DE4
SN65C1406DR
SN65C1406DRE4
SOIC
SOIC
SOIC
D
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65C1406N
SN75C1406D
OBSOLETE
ACTIVE
PDIP
SOIC
N
D
16
16
TBD
Call TI
Call TI
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75C1406DE4
SN75C1406DG4
SN75C1406DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75C1406DRE4
SN75C1406DRG4
SN75C1406DW
SN75C1406DWE4
SN75C1406DWR
SN75C1406DWRE4
SN75C1406N
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75C1406NE4
SN75C1406NSR
SN75C1406NSRE4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2006
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
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