SN65DSI84TPAPRQ1 [TI]
汽车类单通道 MIPI® DSI 转双链路 LVDS 桥接器 | PAP | 64 | -40 to 105;
| 型号： | SN65DSI84TPAPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类单通道 MIPI® DSI 转双链路 LVDS 桥接器 | PAP | 64 | -40 to 105 电信 电信集成电路 |
| 文件： | 总54页 (文件大小：1839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65DSI84-Q1
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
SN65DSI84-Q1 汽车用单通道 MIPI® DSI 转双链路 LVDS 桥接器
1 特性
3 说明
1
•
符合汽车类应用的 要求
SN65DSI84-Q1 DSI 转 LVDS 桥接器 具有 一个单通
道 MIPI D-PHY 接收器前端配置，此配置中在每个通
道上具有 4 条信道，每条信道的运行速率为 1Gbps，
最大输入带宽为 4Gbps。桥接器可解码 MIPI®DSI
18bpp RGB666 和 24bpp RGB888 包，并将格式化视
频数据流转换为 LVDS 输出（像素时钟范围为 25MHz
至 154MHz），从而提供双链路 LVDS 或单链路
LVDS（每个链路具有 4 个数据信道）。
•
具有符合 AEC-Q100 标准的下列特性：
–
器件温度等级 2：-40°C 至 105°C 的环境运行
温度范围
–
–
器件 HBM ESD 分类等级 3A
器件 CDM ESD 分类等级 C6
•
•
实现了 MIPI D-PHY 版本 1.00.00 物理层前端和显
示屏串行接口 (DSI) 版本 1.02.00
单通道 DSI 接收器每通道可配置 1、2、3 或 4 条
D-PHY 数据信道，每条信道的运行速率高达
1Gbps
SN65DSI84-Q1 器件非常适用于每秒帧数 (fps) 为 60
的 WUXGA (1920 × 1080)，每像素位数 (bpp) 高达
24 位。该器件实现了部分线路缓冲以适应 DSI 与
LVDS 接口间的数据流不匹配的情况。
•
•
支持 RGB666 和 RGB888 格式的 18bpp 与 24bpp
DSI 视频流
适合 60fps WUXGA 1920 × 1200 分辨率（18bpp
和 24bpp 颜色），以及 60fps 1366 × 768 分辨率
（18bpp 和 24bpp 颜色）
SN65DSI84-Q1 器件采用小外形 10mm × 10mm
HTQFP
（0.5mm 间距）封装，工作温度范围为 –40ºC 至
+105ºC。
•
•
•
针对单链路或双链路 LVDS 的输出配置
支持单通道 DSI 转单链路 LVDS 的操作模式
器件信息(1)
双链路或单链路模式下 LVDS 输出时钟范围为
25MHz 到 154MHz
器件编号
封装
封装尺寸（标称值）
•
LVDS 像素时钟可采用自由运行持续 D-PHY 时钟
或外部基准时钟 (REFCLK)
SN65DSI84-Q1
HTQFP (64)
10.00mm x 10.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
•
1.8V 主 VCC 电源
低功耗 特性 包括关断模式、低 LVDS 输出电压摆
幅、共模以及 MIPI 超低功耗状态 (ULPS) 支持
图 1. 典型应用
•
•
针对简化印刷电路板 (PCB) 走线的 LVDS 通道交
换 (SWAP)，LVDS 引脚顺序反向特性
TFT LCD Display
DA[3:0]P
A_Y0:3N
DA[3:0]N
Single-Channel
DSI to Dual
LVDS Bridge
A_Y0:3P
A_CLKN/P
B_Y0:3N
B_Y0:3P
采用 64 引脚 10mm × 10mm HTQFP (PAP) 封装
PowerPAD™IC 封装
Application
Processor
With DSI
Output
DACP/N
SN65SDSI84-Q1
SCL/SDA
2 应用
IRQ
EN
•
•
•
•
•
•
•
集成显示屏的信息娱乐系统主机
B_CLKN/P
具有远程显示屏的信息娱乐系统主机
后座信息娱乐系统
Copyright © 2016, Texas Instruments Incorporated
混合动力汽车仪表板
便携式导航设备 (PND)
导航
工业人机界面 (HMI) 和显示屏
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEW9
SN65DSI84-Q1
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
www.ti.com.cn
目录
8.6 Register Maps......................................................... 23
Application and Implementation ........................ 38
9.1 Application Information............................................ 38
9.2 Typical Application ................................................. 38
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 9
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 14
8.5 Programming........................................................... 22
9
10 Power Supply Recommendations ..................... 45
10.1 VCC Power Supply................................................. 45
10.2 VCORE Power Supply ......................................... 45
11 Layout................................................................... 45
11.1 Layout Guidelines ................................................. 45
11.2 Layout Example .................................................... 46
12 器件和文档支持 ..................................................... 47
12.1 文档支持 ............................................................... 47
12.2 接收文档更新通知 ................................................. 47
12.3 社区资源................................................................ 47
12.4 商标....................................................................... 47
12.5 静电放电警告......................................................... 47
12.6 术语表 ................................................................... 47
13 机械、封装和可订购信息....................................... 48
7
8
4 修订历史记录
Changes from Original (December 2016) to Revision A
Page
•
•
•
•
•
Deleted figure RESET and Initialization Timing Definition While VCC is High ...................................................................... 11
Changed the paragraph following Figure 8 ......................................................................................................................... 14
Changed Recommended Initialization Sequence To: Initialization Sequence ..................................................................... 15
Changed Table 2 .................................................................................................................................................................. 15
Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane to
LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. ............................................................... 38
2
Copyright © 2016–2018, Texas Instruments Incorporated
SN65DSI84-Q1
www.ti.com.cn
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
5 Pin Configuration and Functions
PAP Package
64-Pin HTQFP With PowerPAD™
Top View
RSVD2
EN
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
2
A_Y0N
A_Y0P
A_Y1N
A_Y1P
VCC
VCC
3
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC
4
5
6
7
A_Y2N
A_Y2P
VCC
8
Thermal
Pad
9
10
11
12
13
14
15
16
A_CLKN
A_CLKP
A_Y3N
A_Y3P
VCC
SCL
RSVD1
IRQ
SDA
Not to scale
Copyright © 2016–2018, Texas Instruments Incorporated
3
SN65DSI84-Q1
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Local I2C interface target address select. See Table 4. In normal operation this pin is an
input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power
rails where the SN65DSI84-Q1 VCC 1.8-V power rail is connected.
ADDR
64
I/O
A_Y0P
A_Y0N
A_Y1P
A_Y1N
A_Y2P
A_Y2N
A_Y3P
A_Y3N
A_CLKP
A_CLKN
B_Y0P
B_Y0N
B_Y1P
B_Y1N
B_Y2P
B_Y2N
B_Y3P
B_Y3N
B_CLKP
B_CLKN
DA0P
46
47
44
45
41
42
36
37
38
39
61
62
59
60
56
57
50
51
53
54
19
20
21
22
27
28
29
30
24
25
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
LVDS channel A, LVDS data output 0
LVDS channel A, LVDS data output 1
LVDS channel A, LVDS data output 2
LVDS channel A, LVDS data output 3. A_Y3P and A_Y3N must be left not connected
(NC) for 18-bpp panels.
LVDS channel A, LVDS clock output
LVDS channel B, LVDS data output 0
LVDS channel B, LVDS data output 1
LVDS channel B, LVDS data output 2
LVDS channel B, LVDS data output 3. B_Y3P and B_Y3N must be left NC for 18-bpp
panels.
LVDS channel B, LVDS clock output
MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps.
MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps
MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps.
MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps.
DA0N
I
DA1P
I
DA1N
I
DA2P
I
DA2N
I
DA3P
I
DA3N
I
DACP
I
MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps.
Leave unconnected
DACN
I
4, 5, 6, 7, 8, 9,
10, 11, 12, 13
RSVD
—
EN
2
23, 26, 52
33
I
Chip enable and reset. The device is reset (shutdown) when the EN pin is low.
GND
IRQ
G
O
Reference ground
Interrupt signal
This pin is an optional external reference clock for the LVDS pixel clock. If an external
reference clock is not used, this pin must be pulled to ground with an external resistor.
The source of the reference clock must be placed as close as possible with a series
resistor near the source to reduce EMI.
REFCLK
17
I
RSVD1
RSVD2
SCL
34
1
I/O
Reserved. This pin must be left unconnected for normal operation.
Reserved. This pin must be left unconnected for normal operation.
Local I2C interface clock.
I
I
15
16
SDA
I/O
Local I2C interface data
4
Copyright © 2016–2018, Texas Instruments Incorporated
SN65DSI84-Q1
www.ti.com.cn
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
3
—
—
—
—
—
—
—
—
—
—
—
—
14
18
32
35
40
43
48
49
55
58
63
VCC
1.8-V power supply
1.1-V output from the voltage regulator. This pin must have a 1-µF external capacitor to
ground.
VCORE
31
P
PowerPAD
—
Reference ground
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.5
–0.4
–40
–40
–65
MAX
2.175
2.175
1.4
UNIT
V
VCC
Supply voltage
Input voltage
CMOS input pins
V
DSI input pins (DAxP, DAxN, DBxP, and DBxN)
V
TA
Operating free-air temperature
Junction temperature
105
°C
°C
°C
TJ
115
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Procedures. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Copyright © 2016–2018, Texas Instruments Incorporated
5
SN65DSI84-Q1
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
www.ti.com.cn
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
TYP
MAX
1.95
0.05
1350
400
UNIT
V
VCC
VCC power supply
1.8
VPSN
V(DSI)
ƒ(I2C)
ƒHS(CLK)
tsu
Supply noise on any VCC pin
DSI input pin voltage
Local I2C input frequency
ƒ(noise) > 1 MHz
–50
V
mV
kHz
MHz
UI(1)
UI(1)
Ω
DSI high-speed (HS) clock input frequency
DSI HS data to clock setup time
DSI HS data to clock hold time
LVDS output differential impedance
Case temperature
40
0.15
0.15
90
500
th
ZOD(LVDS)
TC
132
92.2
°C
(1) The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps.
6.4 Thermal Information
SN65DSI84-Q1
THERMAL METRIC(1)
PAP (HTQFP)
64 PINS
36.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
18.2
20.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJB
20.5
RθJC(bot)
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
V
VIL
VIH
VOH
VOL
ILKG
IIH
Low-level control signal input voltage
High-level control signal input voltage
High-level output voltage
Low-level output voltage
0.3 × VCC
0.7 × VCC
1.25
V
IOH = –4 mA
V
IOL = 4 mA
0.4
±30
±30
±30
±10
±50
164
V
Input failsafe leakage current
High level input current
VCC = 0; VCC(PIN) = 1.8 V
Any input terminal
μA
μA
μA
μA
mA
mA
IIL
Low level input current
Any input terminal
IOZ
IOS
ICC
High-impedance output current
Short-circuit output current
Device active current
CMOS output terminals
Any output driving GND short
(2)
See
106
7.7
All data and clock lanes are in ultra-low
power state (ULPS)
IULPS
Device standby current
14
mA
IRST
REN
Shutdown current
EN = 0
0.04
200
130
µA
EN control input resistor
kΩ
(1) All typical values are at VCC = 1.8V and TA = 25°C
(2) SN65DSI84-Q1: SINGLE Channel DSI to DUAL Channel LVDS, 1400 x 900
(a) number of LVDS lanes = 2 × (3 data lanes + 1 CLK lane)
(b) number of DSI lanes = 2 data lanes + 1 CLK lane
(c) LVDS CLK OUT = 53.25 M
(d) DSI CLK = 500 M
(e) RGB888, LVDS18 bpp
Maximum values are at VCC = 1.95 V and TA = 105°C
6
Copyright © 2016–2018, Texas Instruments Incorporated
SN65DSI84-Q1
www.ti.com.cn
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
880
100
TYP(1)
MAX
UNIT
MIPI DSI INTERFACE
VIH-LP
VIL-LP
LP receiver input high threshold
LP receiver input low threshold
HS differential input voltage
See Figure 2
See Figure 2
mV
mV
mV
mV
550
270
50
|VID
|
|VIDT
|
HS differential input voltage threshold
LP receiver input low threshold; ultra-low
power state (ULPS)
VIL-ULPS
VCM-HS
300
330
100
460
mV
mV
mV
HS common mode voltage; steady-state
70
HS common mode peak-to-peak variation
including symbol delta and interference
ΔVCM-HS
VIH-HS
VIL-HS
HS single-ended input high voltage
HS single-ended input low voltage
See Figure 2
See Figure 2
mV
mV
–40
80
HS termination enable; single-ended input
voltage (both Dp AND Dn apply to
enable)
Termination is switched simultaneous for
Dn and Dp
VTERM-EN
450
125
mV
RDIFF-HS
HS mode differential input impedance
Ω
LVDS OUTPUT
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00
100 Ω near end termination
180
215
250
290
150
200
250
300
245
293
341
389
204
271
337
402
330
392
455
515
275
365
450
535
CSR 0x19.3:2=01 and, or CSR
0x19.1:0=01
100 Ω near end termination
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10
100 Ω near end termination
CSR 0x19.3:2=11 and, or CSR
0x19.1:0=11
100 Ω near end termination
Steady-state differential output voltage for
A_Yx P/N and B_Yx P/N
|VOD
|
mV
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00
200 Ω near end termination
CSR 0x19.3:2=01 and, or CSR
0x19.1:0=01
200 Ω near end termination
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10
200 Ω near end termination
CSR 0x19.3:2=11 and, or CSR
0x19.1:0=11
200 Ω near end termination
Copyright © 2016–2018, Texas Instruments Incorporated
7
SN65DSI84-Q1
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00
100 Ω near end termination
140
191
262
315
365
415
220
295
362
CSR 0x19.3:2=01 and, or CSR
0x19.1:0=01
100 Ω near end termination
168
195
226
117
156
195
234
229
266
303
159
211
263
314
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10
100 Ω near end termination
CSR 0x19.3:2=11 and, or CSR
0x19.1:0=11
100 Ω near end termination
Steady-state differential output voltage for
A_CLKP/N and B_CLKP/N
|VOD
|
mV
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00
200 Ω near end termination
CSR 0x19.3:2=01 and, or CSR
0x19.1:0=01
200 Ω near end termination
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10
200 Ω near end termination
CSR 0x19.3:2=11 and, or CSR
0x19.1:0=11
200 Ω near end termination
435
35
Change in steady-state differential output
voltage between opposite binary states
Δ|VOD
|
RL = 100 Ω
mV
V
CSR 0x19.6 = 1 and CSR 0x1B.6 = 1;
and, or CSR 0x19.4 = 1 and
CSR 0x1B.4 = 1; see Figure 3
0.75
1
0.9
1.13
Steady state common-mode output
voltage(3)
VOC(SS)
CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0;
see Figure 3
1.25
1.5
35
Peak-to-peak common-mode output
voltage
VOC(PP)
see Figure 3
mV
Pulldown resistance for disabled LVDS
outputs
RLVDS_DIS
1
kΩ
(3) Tested at VCC = 1.8V , TA = –40°C for MIN, TA = 25°C for TYP, TA = 105°C for MAX.
8
Copyright © 2016–2018, Texas Instruments Incorporated
SN65DSI84-Q1
www.ti.com.cn
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
DSI
tGS
LVDS
tc
DSI LP glitch suppression pulse width
300
40
ps
Output clock period
6.49
4/7 tc
–0.15
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw
High-level output clock (CLK) pulse duration
Delay time, CLK↑ to 1st serial bit position
Delay time, CLK↑ to 2nd serial bit position
Delay time, CLK↑ to 3rd serial bit position
Delay time, CLK↑ to 4th serial bit position
Delay time, CLK↑ to 5th serial bit position
Delay time, CLK↑ to 6th serial bit position
Delay time, CLK↑ to 7th serial bit position
Differential output rise-time
t0
0.15
1/7 tc + 0.15
2/7 tc + 0.15
3/7 tc + 0.15
4/7 tc + 0.15
5/7 tc + 0.15
6/7 tc + 0.15
t1
1/7 tc – 0.15
t2
2/7 tc – 0.15
3/7 tc – 0.15
4/7 tc – 0.15
5/7 tc – 0.15
6/7 tc – 0.15
tc = 6.49 ns;
Input clock jitter < 25 ps
(REFCLK)
t3
See Figure 4
t4
t5
t6
tr
See Figure 4
180
–10
500
10
ps
ps
tf
Differential output fall-time
LVDS CLK A to CLK B skew
EN, ULPS, RESET
ten
Enable time from EN or ULPS; see
tc(o) = 12.9 ns
tc(o) = 12.9 ns
1
ms
ms
ms
tdis
Disable time to standby
Reset Time
0.1
treset
REFCLK
10
REFCLK Freqeuncy. Supported frequencies:
25 MHz - 15 4MHz
FREFCLK
25
154
MHz
tr, tf
tpj
REFCLK rise and fall time
REFCLK Peak-to-Peak Phase Jitter
REFCLK Duty Cycle
0.1
1
50
ns
ps
Duty
40%
50%
1%
60%
REFCLK or DSI CLK (DACP/N, DBCP/N)
SSC enabled Input CLK center spread depth(2)
0.5%
30
2%
60
SSC_CLKIN
Modulation Frequency Range
kHz
(1) All typical values are at VCC = 1.8 V and TA = 25°C
(2) For EMI reduction purpose, SN65DSI84-Q1 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK
input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or
B_CLKP/N.
7 Parameter Measurement Information
1.3 V
LP-RX
Input HIGH
V
IH(LP)
V
IL(LP)
V
IH(HS)
V
ID
VCM(HS)max
LP-RX
Input LOW
HS-RX
Common Mode
Range
VCM(HS)min
GND
VIL(HS)
High Speed (HS) Mode
Receiver
Low Power (LP)
Mode Receiver
Figure 2. DSI Receiver Voltage Definitions
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Parameter Measurement Information (continued)
A_YnP
B_YnP
49.9 Ω 1%ꢀ(2ꢀPLCꢁ)
VOD
A_YnN
B_YnN
VOC
100%
80%
VOD(H)
0 V
VOD(L)
20%
0%
tf
tr
VOC(PP)
VOC(s)
VOC(s)
0 V
Figure 3. Test Load and Voltage Definitions for LVDS Outputs
CLK
t6
t5
t4
t3
t2
t1
t0
Yn
VOD(H)
0.00V
VOD(L)
t0-6
Figure 4. SN65DSI84-Q1 LVDS Timing Definitions
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Parameter Measurement Information (continued)
ULPS (LP00) State
DSI lane
t
ten
dis
A_CLKP/N
(LVDS_CHA_CLK)
(1) See the ULPS section of the data sheet for the ULPS entry and exit sequence.
(2) ULPS entry and exit protocol and timing requirements must be met according to the MIPI DPHY specification.
Figure 5. ULPS Timing Definition
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8 Detailed Description
8.1 Overview
The SN65DSI84-Q1 DSI to LVDS bridge features a single-channel MIPI D-PHY receiver front-end configuration
with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge
decodes MIPI DSI 18-bpp RGB666 and 240-bpp RG888 packets and converts the formatted video data stream
to a LVDS compatible LVDS output operating at pixel clocks operating from 25 MHx to 154 MHz, offering a Dual-
Link LVDS, Single-Link LVDS interface with four data lanes per link.
8.2 Functional Block Diagram
LVDS SERIALIZER
DSI PACKET
PROCESSORS
AVCC
AGND
VCC
A_Y0P
ERR
A_Y0N
A_Y1P
PACKET
ULPS
LPRX
HEADERS
ERR
A_Y1N
A_Y2P
A_Y2N
LANE
MERGE
GND
(ODD )
18
8
DA0P
DA0N
HSRX
LONG PACKETS
A_CLKP
A_CLKN
A_Y3P
(EVEN)
18
7-BIT SHIFT
REGISTER
DATA LANE 0
EOT
SOT
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
8
8
8
DATA LANE1
(Circuit same as DATA LANE 0)
Timers
A_Y3N
32
BE
DATA LANE 2
(Circuit same as DATA LANE 0)
DE
VS
HS
B_Y0P
B_Y0N
B_Y1P
SHORT PACKETS
DATA LANE 3
(Circuit same as DATA LANE 0)
DSI CHANNEL
MERGING
CHANNEL
B_Y1N
B_Y2P
B_Y2N
B_CLKP
B_CLKN
B_Y3P
B_Y3N
FORMATTER
PARTIAL
LINE BUFFER
ULPS
LPRX
LVDSPLL
PLL
DACP
DACN
Lock
CLOCK CIRCUITS
HSRX
PIXEL CLOCK
CLK LANE
SCL
CSR
LOCAL I 2
C
SDA
IRQ
HS Clock Sourced
M /N Pixel Clock
PLL
CSR READ
CSR WRITE
ADDR
Clock Dividers
REFCLK
EN
Reset
RSVD1
RSVD2
SN65DSI84
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8.3 Feature Description
8.3.1 Clock Configurations and Multipliers
The LVDS clock may be derived from the DSI channel A clock, or from an external reference clock source. When
the MIPI D-PHY channel A HS clock is used as the LVDS clock source, the D-PHY clock lane must operate in
HS free-running (continuous) mode; this feature eliminates the requirement for an external reference clock
reducing system costs
The reference clock source is selected by HS_CLK_SRC (CSR 0x0A.0) programmed through the local I2C
interface. If an external reference clock is selected, it is multiplied by the factor in REFCLK_MULTIPLIER (CSR
0x0B.1:0) to generate the LVDS output clock. When an external reference clock is selected, it must be between
25 MHz and 154 MHz. If the DSI channel A clock is selected, it is divided by the factor in DSI_CLK_DIVIDER
(CSR 0x0B.7:3) to generate the LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and
CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the LVDS output clock for and DSI
Channel A input clock respectively the internal PLL to operate correctly. After these settings are programmed,
PLL_EN (CSR 0x0D.0) must be set to enable the internal PLL.
8.3.2 ULPS
The SN65DSI84-Q1 supports the MIPI defined ultra-low power state (ULPS). While the device is in the ULPS,
the CSR registers are accessible via I2C interface. ULPS sequence should be issued to all active DSI CLK
and/or DSI data lanes of the enabled DSI Channels for the SN65DSI84-Q1 enter the ULPS. The Following
sequence should be followed to enter and exit the ULPS.
1. Host issues a ULPS entry sequence to all DSI CLK and data lanes enabled.
2. When host is ready to exit the ULPS mode, host issues a ULPS exit sequence to all DSI CLK and data lanes
that must be active in normal operation.
3. Wait for a minimum of 3 ms.
4. Set the SOFT_RESET bit (CSR 0x09.0).
5. Device resumes normal operation.(i.e video streaming resumes on the panel).
8.3.3 LVDS Pattern Generation
The SN65DSI84-Q1 supports a pattern generation feature on LVDS Channels. This feature can be used to test
the LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by
setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation
feature is enabled.
Three modes are available for LVDS test pattern generation. The mode of test pattern generation is determined
by register configuration as shown in Table 1.
Table 1. Video Registers
Addr. bit
0x20.7:0
0x21.3:0
0x24.7:0
0x25.3:0
0x2C.7:0
0x2D.1:0
0x30.7:0
0x31.1:0
0x34.7:0
0x36.7:0
0x38.7:0
0x3A.7:0
Register Name
CHA_ACTIVE_LINE_LENGTH_LOW
CHA_ACTIVE_LINE_LENGTH_HIGH
CHA_VERTICAL_DISPLAY_SIZE_LOW
CHA_VERTICAL_DISPLAY_SIZE_HIGH
CHA_HSYNC_PULSE_WIDTH_LOW
CHA_HSYNC_PULSE_WIDTH_HIGH
CHA_VSYNC_PULSE_WIDTH_LOW
CHA_VSYNC_PULSE_WIDTH_HIGH
CHA_HORIZONTAL_BACK_PORCH
CHA_VERTICAL_BACK_PORCH
CHA_HORIZONTAL_FRONT_PORCH
CHA_VERTICAL_FRONT_PORCH
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8.4 Device Functional Modes
8.4.1 Reset Implementation
When EN is de-asserted (low), the SN65DSI84-Q1 is in SHUTDOWN or RESET state. In this state, CMOS
inputs are ignored, the MIPI® D-PHY inputs are disabled and outputs are high impedance. The EN input must
transmit from a low to a high level after the VCC supply has reached the minimum operating voltage as shown in
Figure 6. This is achieved by a control signal to the EN input, or by an external capacitor connected between EN
and GND.
VCC
1.65V
EN
tVCC
Figure 6. Cold Start VCC Ramp up to EN
ten
When implementing the external capacitor, the size of the external capacitor depends on the power up ramp
of the VCC supply, where a slower ramp-up results in a larger value external capacitor. See the latest
reference schematic for the SN65DSI84-Q1 device and, or consider approximately 200 nF capacitor as a
reasonable first estimate for the size of the external capacitor.
Both EN implementations are shown in Figure 7 and Figure 8.
VCC
GPO
EN
EN
C
REN =200 kΩ
C
SN65DSI84
controller
SN65DSI84
Figure 7. External Capacitor Controlled EN
Figure 8. EN Input From Active Controller
When the SN65DSI84-Q1 is reset while VCC is high, the EN pin must be held low for at least 10 ms before being
asserted high as described in Table 2 to be sure that the device is properly reset. The DSI CLK lane MUST be in
HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted
per the timing described in Table 2.
8.4.2 Initialization Sequence
Use the following initialization sequence to setup the SN65DSI84-Q1. This sequence is required for proper
operation of the device. Steps 9 through 11 in the sequence are optional.
Also see to Figure 6.
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Device Functional Modes (continued)
Table 2. Initialization Sequence
INITIALIZATION
SEQUENCE
NUMBER
INITIALIZATION SEQUENCE DESCRIPTION
Init seq 1
Power on
After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven
to LP11 state
Init seq 2
Init seq 3
Wait 10 ms
Init seq 4
Wait 10 ms
Init seq 5
Set EN pin to Low
(1)
(1)
Tie EN pin to High
Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not
functional until the CSR registers are initialized)
Init seq 6
Wait 10 ms
Init seq 7
Wait 10 ms
Init seq 8
Set the PLL_EN bit (CSR 0x0D.0)
(1)
(1)
Set the SOFT_RESET bit (CSR 0x09.0)
Change DSI data lanes to HS state and start DSI video stream
(1)
Wait 5 ms
Init seq 9
Init seq 10
Wait 1 ms
Init seq 11
Read back all resisters and confirm they were correctly written
Write 0xFF to CSR 0xE5 to clear the error registers
(1)
Read CSR 0xE5. If CSR 0xE5!= 0x00, then go back to step #2 and re-initialize
(1) Minimum recommended delay. It is fine to exceed these.
8.4.3 LVDS Output Formats
The SN65DSI84-Q1 processes DSI packets and produces video data driven to the LVDS interface in an industry
standard format. Single-Link LVDS and Dual-Link LVDS are supported by the SN65DSI84-Q1; when the LVDS
output is implemented in a Dual-Link configuration, channel A carries the odd pixel data, and channel B carries
the even pixel data. During conditions such as the default condition, and some video synchronization periods,
where no video stream data is passing from the DSI input to the LVDS output, the SN65DSI84-Q1 transmits zero
value pixel data on the LVDS outputs while maintaining transmission of the vertical sync and horizontal sync
status.
Figure 9 illustrates a Single-Link LVDS 18bpp application.
Figure 10 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR
0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are transferred on
the Y3P/N LVDS lane.
Figure 11 illustrates a 24 bpp Single-Link application using Format 1. In data Format 1, the two LSB per color are
transferred on the Y3P/N LVDS lane.
Figure 12 illustrates a Single-Link LVDS application where 24 bpp data is received from DSI and converted to 18
bpp data for transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1
(CSR 0x18.1) to ‘1’ and CHA_24BPP_MODE (CSR 0x18.3) to ‘0’. In this configuration, the SN65DSI84-Q1 will
not transmit the 2 LSB per color because the Y3P/N LVDS lane is disabled.
NOTE
Note: Figure 9, Figure 10, Figure 11, and Figure 12 only illustrate a few example
applications for the SN65DSI84-Q1. Other applications are also supported.
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A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G0
B1
DE
R5
B0
VS
R4
G5
HS
R3
R2
G3
B4
R1
G2
B3
R0
G1
B2
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
G4
B5
B_YxP/N
DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low
Figure 9. LVDS Output Data; Single-Link 18 Bpp
A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G0
(o)
R5
(o)
R4
(o)
R3
(o)
R2
(o)
R1
(o)
R0
(o)
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
B1
(o)
B0
(o)
G5
(o)
G4
(o)
G3
(o)
G2
(o)
G1
(o)
DE
(o)
VS
(o)
HS
(o)
B5
(o)
B4
(o)
B3
(o)
B2
(o)
0
(o)
B7
(o)
B6
(o)
G7
(o)
G6
(o)
R7
(o)
R6
(o)
G0
(e)
R5
(e)
R4
(e)
R3
(e)
R2
(e)
R1
(e)
R0
(e)
B_Y0P/N
B_Y1P/N
B_Y2P/N
B_Y3P/N
B1
(e)
B0
(e)
G5
(e)
G4
(e)
G3
(e)
G2
(e)
G1
(e)
DE
(e)
VS
(e)
HS
(e)
B5
(e)
B4
(e)
B3
(e)
B2
(e)
0
(e)
B7
(e)
B6
(e)
G7
(e)
G6
(e)
R7
(e)
R6
(e)
DE = Data Enable; (o) = Odd Pixels; (e) = Even Pixels
Figure 10. LVDS Output Data (Format 2); Dual-Link 24 Bpp
A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G2
B3
DE
R7
B2
VS
R6
G7
HS
R5
R4
G5
B6
R3
G4
B5
R2
G3
B4
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
G6
B7
0
B1
B0
G1
G0
R1
R0
B_YxP/N
DE = Data Enable; Channel B Clock and Data are Output Low
Figure 11. LVDS Output Data (Format 1); Single-Link 24 Bpp
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A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G2
B3
DE
R7
B2
VS
R6
G7
HS
R5
G6
B7
R4
G5
B6
R3
G4
B5
R2
G3
B4
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
B_YxP/N
DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N a re Output Low; Channel B Clock, Channel B
Data, and A_Y3P/N are Output Low
Figure 12. LVDS Output Data (Format 1); 24-Bpp to Single-Link 18-Bpp Conversion
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8.4.4 DSI Lane Merging
The SN65DSI84-Q1 supports four DSI data lanes per input channel, and may be configured to support one, two,
or three DSI data lanes per channel. Unused DSI input pins on the SN65DSI84-Q1 should be left unconnected or
driven to LP11 state. The bytes received from the data lanes are merged in HS mode to form packets that carry
the video stream. DSI data lanes are bit and byte aligned.
Figure 13 illustrates the lane merging function for each channel; 4-Lane, 3-Lane, and 2-Lane modes are
illustrated
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 4
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 3
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-4
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
LANE 0
LANE 1
LANE 2
BYTE 10
BYTE 11
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 3
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 4
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-2
BYTE n-1
EOT
EOT
EOT
LANE 0
LANE 1
LANE 2
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
BYTE 10
BYTE 11
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 3
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-1
EOT
EOT
LANE 0
LANE 1
LANE 2
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
BYTE 10
BYTE 11
3 DSI Data Lane Configuration
EOT
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 2
HS BYTES TRANSMITTED (n) IS 3 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-1
EOT
EOT
LANE 0
LANE 1
SOT
SOT
BYTE 0
BYTE1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE n-2
BYTE n-1
EOT
EOT
BYTE 10
BYTE 11
EOT
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 2
EOT
LANE 0
LANE 1
SOT
SOT
BYTE 0
BYTE1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE n-1
EOT
EOT
4 DSI Data Lane Configuration (default)
2 DSI Data Lane Configuration
Figure 13. SN65DSI84-Q1 DSI Lane Merging Illustration
8.4.5 DSI Pixel Stream Packets
The SN65DSI84-Q1 processes 18bpp (RGB666) and 24 bpp (RGB888) DSI packets on each channel as shown
in Figure 14, Figure 15, andFigure 16.
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1 Byte
2 Bytes
1 Byte
WORD COUNT Bytes
2 Bytes
18 bpp Loosely Packed Pixel Stream
(Variable Size Payload)
WORD COUNT
ECC
CRC CHECKSUM
Packet Payload
Packet Footer
Packet Header
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0 1
2
7
2
7
2
7
2
7
2
7
2
7
2
7
2
7
2
7
R0
R5
G0
G5
B0
B5
R0
R5
G0
G5
B0
B5
R0
R5
G0
G5
B0
B5
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
First Pixel in Packet
Second Pixel in Packet
Third Pixel in Packet
Variable Size Payload (Three Pixels Per Nine Bytes of Payload)
Figure 14. 18 Bpp (Loosely Packed) DSI Packet Structure
1 Byte
2 Bytes
1 Byte
WORD COUNT Bytes
2 Bytes
18 bpp Packed Pixel Stream
(Variable Size Payload)
WORD COUNT
ECC
CRC CHECKSUM
Packet Payload
Packet Footer
Packet Header
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0
5
6
7
0
3
4
7
0 1
2
7
0
5
6
7
0
3
4
7
0 1
2
7
0
5
6
7
0
3
4
7
0 1
2
7
R0
R5 G0
G5 B0
B5 R0
R5 G0
G5 B0
B5 R0
R5 G0
G5 B0
B5 R0
R5 G0
G5 B0
B5
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
First Pixel in Packet
Second Pixel in Packet
Third Pixel in Packet
Fourth Pixel in Packet
Variable Size Payload (Four Pixels Per Nine Bytes of Payload)
Figure 15. 18-Bpp (Tightly Packed) DSI Packet Structure
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1 Byte
2 Bytes
1 Byte
WORD COUNT Bytes
2 Bytes
24 bpp Packed Pixel Stream
(Variable Size Payload)
WORD COUNT
ECC
CRC CHECKSUM
Packet Payload
Packet Footer
Packet Header
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
R0
R7 G0
G 7 B0
B7 R0
R7 G0
G 7 B0
B7 R0
R7 G0
G7 B0
B7
8-bits
RED
8-bits
GREEN
8-bits
BLUE
8-bits
RED
8-bits
GREEN
8-bits
BLUE
8-bits
RED
8-bits
GREEN
8-bits
BLUE
First Pixel in Packet
Second Pixel in Packet
Third Pixel in Packet
Variable Size Payload (Three Pixels Per Nine Bytes of Payload)
Figure 16. 24-Bpp DSI Packet Structure
8.4.6 DSI Video Transmission Specifications
The SN65DSI84-Q1 supports burst video mode and non-burst video mode with sync events or with sync pulses
packet transmission as described in the DSI specification. The burst mode supports time-compressed pixel
stream packets that leave added time per scan line for power savings LP mode. The SN65DSI84-Q1 requires a
transition to LP mode once per frame to enable PHY synchronization with the DSI host processor; however, for a
robust and low-power implementation, the transition to LP mode is recommended on every video line.
Figure 17 illustrates the DSI video transmission applied to SN65DSI84-Q1 applications. In all applications, the
LVDS output rate must be less than or equal to the DSI input rate. The first line of a video frame shall start with a
VSS packet, and all other lines start with VSE or HSS. The position of the synchronization packets in time is of
utmost importance because this has a direct impact on the visual performance of the display panel; that is, these
packets generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface after the delay
programmed into CHA_SYNC_DELAY_LOW/HIGH (CSR 0x28.7:0 and 0x29.3:0).
As required in the DSI specification, the SN65DSI84-Q1 requires that pixel stream packets contain an integer
number of pixels (i.e. end on a pixel boundary); TI recommends transmitting an entire scan line on one pixel
stream packet. When a scan line is broken in to multiple packets, inter-packet latency shall be considered such
that the video pipeline (ie. pixel queue or partial line buffer) does not run empty (i.e. under-run); during scan line
processing, if the pixel queue runs empty, the SN65DSI84-Q1 transmits zero data (18’b0 or 24’b0) on the LVDS
interface.
NOTE
When the HS clock is used as a source for the LVDS pixel clock, the LP mode transitions
apply only to the data lanes, and the DSI clock lane remains in the HS mode during the
entire video transmission.
The DSI84 does not support the DSI Virtual Channel capability or reverse direction
(peripheral to processor) transmissions.
20
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One Video Frame
t LINE
t LINE
t LINE
t LINE
t LINE
t LINE
t LINE
DSI
Channel A
NOP/
LP
NOP/
LP
NOP/
LP
NOP/
RGB
NOP/
LP
NOP/
LP
NOP/
LP
...
...
...
RGB
LP
Vertical sync / blanking
Active Lines
Vertical sync / blanking
* VSS and HSS packets are required for DSI Channel B, although LVDS video sync signals are derived from DSI Channel A VSS and HSS packets
Vertical Blanking Period LVDS Transfer Function
Active Video Line LVDS Transfer Function
t LINE
t LINE
tLINE
DSI
DSI
DSI
NOP/
LP
NOP/
LP
NOP/
LP
...
RGB
Channel A
Channel A
Channel(s)
tW (HS )
t W(HS)
HS (1)
HS(1)
HS (1)
t PD
tPD
VS (2)
DE (3)
DATA
VS (2)
DE(3)
DATA
VS (2)
DE (3)
DATA
0x000
0x000
0x000
PixelStream Data
0x000 (4)
LEGEND
VSS
(1) The assertion of HS is delayed (tPD) by a programmable number of pixel clocks from the
last bit of VSS/HSS packet received on DSI. The HS pulse width (tW(HS)) is also programmable.
The illustration shows HS active low.
DSI Sync Event Packet: V Sync Start
DSI Sync Event Packet: H Sync Start
(2) VS is signaled for a programmable number of lines (tLINE ) and is asserted when HS is
asserted for the first line of the frame . VS is de -asserted when HS is asserted after the
number of lines programmed has been reached. The illustration shows VS active low
HSS
RGB
A sequence of DSI Pixel Stream Packets
and Null Packets
(3) DE is asserted when active pixel data is transmitted on LVDS , and polarity is set
independent to HS/VS. The illustration shows DE active high
NOP/LP
DSI Null Packet , Blanking Packet , or a
transition to LP Mode
(4) After the last pixel in an active line is output to LVDS, the LVDS data is output zero
Figure 17. DSI Channel Transmission and Transfer Function
8.4.7 Operating Modes
The SN65DSI84-Q1 can be configured for several different operating modes via LVDS_LINK_CFG (CSR
0x18.4), LEFT_RIGHT_PIXELS (CSR 0x10.7), and DSI_CHANNEL_MODE (CSR 0x10.6:5). These modes are
summarized in Table 3. In each of the modes, video data can be 18 bpp or 24 bpp.
Table 3. SN65DSI84-Q1 Operating Modes
CSR 0x18.4
MODE
DESCRIPTION
LVDS_LINK_CFG
Single DSI Input to Single-Link LVDS
Single DSI Input to Dual-Link LVDS
1
Single DSI Input on Channel A to Single-Link LVDS output on Channel A.
Single DSI Input on Channel A to Dual-Link LVDS output with Odd pixels on
Channel A and Even pixels on Channel B.
0
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8.5 Programming
8.5.1 Local I2C Interface Overview
The SN65DSI84-Q1 local I2C interface is enabled when EN is input high, access to the CSR registers is
supported during ultra-low power state (ULPS). The SCL and SDA terminals are used for I2C clock and I2C data
respectively. The SN65DSI84-Q1 I2C interface conforms to the two-wire serial interface defined by the I2C Bus
Specification, Version 2.1 (January 2000), and supports fast mode transfers up to 400 kbps.
The device address byte is the first byte received following the START condition from the master device. The 7
bit device address for SN65DSI84-Q1 is factory preset to 010110X with the least significant bit being determined
by the ADDR control input. Table 4 clarifies the SN65DSI84-Q1 target address.
(1)(2)
Table 4. SN65DSI84-Q1 I2C Target Address Description
SN65DSI84-Q1 I2C TARGET ADDRESS
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (W/R)
0
1
0
1
1
0
ADDR
0/1
(1) When ADDR=1, Address Cycle is 0x5A (Write) and 0x5B (Read)
(2) When ADDR=0, Address Cycle is 0x58 (Write) and 0x59 (Read)
The following procedure is followed to write to the SN65DSI84-Q1 I2C registers.
1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI84-Q1 7-
bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The SN65DSI84-Q1 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within SN65DSI84-Q1) to be written, consisting of one
byte of data, MSB-first.
4. The SN65DSI84-Q1 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The SN65DSI84-Q1 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the SN65DSI84-Q1.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure is followed to read the SN65DSI84-Q1 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI84-Q1 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
2. The SN65DSI84-Q1 acknowledges the address cycle.
3. The SN65DSI84-Q1 transmit the contents of the memory registers MSB-first starting at register 00h. If a write
to the SN65DSI84-Q1 I2C register occurred prior to the read, then the SN65DSI84-Q1 will start at the sub-
address specified in the write.
4. The SN65DSI84-Q1 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the SN65DSI84-Q1 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure is followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI84-Q1 7-
bit address and a zero-value “W/R” bit to indicate a write cycle
2. The SN65DSI84-Q1 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within SN65DSI84-Q1) to be written, consisting of one
byte of data, MSB-first.
4. The SN65DSI84-Q1 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
22
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8.6 Register Maps
8.6.1 Control and Status Registers Overview
Many of the SN65DSI84-Q1 functions are controlled by the Control and Status Registers (CSR). All CSR
registers are accessible through the local I2C interface.
See the following tables for the SN65DSI84-Q1 CSR descriptions. Reserved or undefined bit fields should not be
modified. Otherwise, the device may operate incorrectly.
8.6.1.1 CSR Bit Field Definitions – ID Registers
8.6.1.1.1 Registers 0x00 – 0x08
Figure 18. Registers 0x00 – 0x08
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Registers 0x00 – 0x08 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Reserved
R
Reserved
Addresses 0x08 - 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53,
0x49, 0x38, 0x35}
8.6.1.2 CSR Bit Field Definitions – Reset and Clock Registers
8.6.1.2.1 Register 0x09
Figure 19. Register 0x09
7
6
5
4
Reserved
R
3
2
1
0
SOFT_RESET
W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Register 0x09 Field Descriptions
Bit
7-1
0
Field
Type
R
Reset
Description
Reserved
SOFT_RESET
Reserved
W
0
This bit automatically clears when set to ‘1’ and returns zeros
when read. This bit must be set after the CSR’s are updated.
This bit must also be set after making any changes to the DIS
clock rate or after changing between DSI burst and non-burst
modes.
0 – No action (default)
1 – Reset device to default condition excluding the CSR bits.
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8.6.1.2.2 Register 0x0A
Figure 20. Register 0x0A
7
6
5
Reserved
R
4
3
2
LVDS_CLK_RANGE
R/W
1
0
PLL_EN_STAT
R
HS_CLK_SRC
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Register 0x0A Field Descriptions
Bit
Field
Type
Reset
Description
7
PLL_EN_STAT
R
0
0 – PLL not enabled (default)
1 – PLL enabled
Note: After PLL_EN_STAT = 1, wait at least 3ms for PLL to lock.
6-4
3-1
Reserved
R
LVDS_CLK_RANGE
R/W
101
This field selects the frequency range of the LVDS output clock.
000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz
001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz
010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz
100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz
101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default)
110 – Reserved
111 – Reserved
0
HS_CLK_SRC
R/W
0
0 – LVDS pixel clock derived from input REFCLK (default)
1 – LVDS pixel clock derived from MIPI D-PHY channel A HS
continuous clock
8.6.1.2.3 Register 0x0B
Figure 21. Register 0x0B
7
6
5
DSI_CLK_DIVIDER
R/W
4
3
2
Reserved
R
1
0
REFCLK_MULTIPLIER
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Register 0x0B Field Descriptions
Bit
Field
Type
Reset
Description
7-3
DSI_CLK_DIVIDER
R/W
00000
When CSR 0x0A.0 = ‘1’, this field controls the divider used to
generate the LVDS output clock from the MIPI D-PHY Channel
A HS continuous clock. When CSR 0x0A.0 = ‘0’, this field must
be programmed to 00000.
00000 – LVDS clock = source clock (default)
00001 – Divide by 2
00010 – Divide by 3
00011 – Divide by 4
•
•
•
10111 – Divide by 24
11000 – Divide by 25
11001 through 11111 – Reserved
2
Reserved
R
1-0
REFCLK_MULTIPLIER
R/W
00
When CSR 0x0A.0 = ‘0’, this field controls the multiplier used to
generate the LVDS output clock from the input REFCLK. When
CSR 0x0A.0 = ‘1’, this field must be programmed to 00.
00 – LVDS clock = source clock (default)
01 – Multiply by 2
10 – Multiply by 3
11 – Multiply by 4
24
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8.6.1.2.4 Register 0x0D
Figure 22. Register 0x0D
7
6
5
4
Reserved
R
3
2
1
0
PLL_EN
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Register 0x0D Field Descriptions
Bit
7-1
0
Field
Type
R
Reset
Description
Reserved
PLL_EN
Reserved
R/W
0
When this bit is set, the PLL is enabled with the settings
programmed into CSR 0x0A and CSR 0x0B. The PLL should be
disabled before changing any of the settings in CSR 0x0A and
CSR 0x0B. The input clock source must be active and stable
before the PLL is enabled.
0 – PLL disabled (default)
1 – PLL enabled
8.6.1.3 CSR Bit Field Definitions – DSI Registers
8.6.1.3.1 Register 0x10
Figure 23. Register 0x10
7
6
5
4
3
2
1
0
Reserved
CHA_DSI_LANES
Reserved
R
SOT_ERR_TO
L_DIS
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. Register 0x10 Field Descriptions
Bit
7-5
4-3
Field
Type
R
Reset
Description
Reserved
Reserved
CHA_DSI_LANES
R/W
11
This field controls the number of lanes that are enabled for DSI
Channel A.
00 – Four lanes are enabled
01 – Three lanes are enabled
10 – Two lanes are enabled
11 – One lane is enabled (default)
Note: Unused DSI input pins on the SN65DSI84-Q1 should be
left unconnected.
2-1
0
Reserved
R
Reserved
SOT_ERR_TOL_DIS
R/W
0
0 – Single bit errors are tolerated for the start of transaction SoT
leader sequence (default)
1 – No SoT bit errors are tolerated
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8.6.1.3.2 Register 0x11
Figure 24. Register 0x11
7
6
5
4
3
2
1
0
CHA_DSI_DATA_EQ
R/W
Reserved
R
CHA_DSI_CLK_EQ
R/W
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. Register 0x11 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
CHA_DSI_DATA_EQ
R/W
00
This field controls the equalization for the DSI Channel A Data
Lanes
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization
5-4
3-2
Reserved
R
Reserved
CHA_DSI_CLK_EQ
R/W
00
This field controls the equalization for the DSI Channel A Clock
00 – No equalization (default)
01 – 1 dB equalization
10 – Reserved
11 – 2 dB equalization
1-0
Reserved
R
Reserved
8.6.1.3.3 Register 0x12
Figure 25. Register 0x12
7
6
5
4
3
2
1
0
CHA_DSI_CLK_RANGE
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. Register 0x12 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_DSI_CLK_RANGE
R/W
0
This field specifies the DSI Clock frequency range in 5 MHz
increments for the DSI Channel A Clock
0x00 through 0x07 – Reserved
0x08 – 40 ≤ frequency < 45 MHz
0x09 – 45 ≤ frequency < 50 MHz
...
0x63 – 495 ≤ frequency < 500 MHz
0x64 – 500 MHz
0x65 through 0xFF – Reserved
26
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8.6.1.4 CSR Bit Field Definitions – LVDS Registers
8.6.1.4.1 Register 0x18
Figure 26. Register 0x18
7
6
5
4
3
2
1
0
DE_NEG_POL HS_NEG_POL VS_NEG_POL LVDS_LINK_C CHA_24BPP_
CHB_24BPP_ CHA_24BPP_F CHB_24BPP_F
ARITY
ARITY
ARITY
FG
MODE
MODE
ORMAT1
ORMAT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Register 0x18 Field Descriptions
Bit
Field
Type
Reset
Description
7
DE_NEG_POLARITY
R/W
0
0 – DE is positive polarity driven ‘1’ during active pixel
transmission on LVDS (default)
1 – DE is negative polarity driven ‘0’ during active pixel
transmission on LVDS
6
5
4
HS_NEG_POLARITY
VS_NEG_POLARITY
LVDS_LINK_CFG
R/W
R/W
R/W
1
1
1
0 – HS is positive polarity driven ‘1’ during corresponding sync
conditions
1 – HS is negative polarity driven ‘0’ during corresponding sync
(default)
0 – VS is positive polarity driven ‘1’ during corresponding sync
conditions
1 – VS is negative polarity driven ‘0’ during corresponding sync
(default)
0 – LVDS Channel A and Channel B outputs enabled
When CSR 0x10.6:5 = ’00’ or ‘01’, the LVDS is in Dual-Link
configuration
When CSR 0x10.6:5 = ‘10’, the LVDS is in two Single-Link
configuration
1 – LVDS Single-Link configuration; Channel A output enabled
and Channel B output disabled (default)
3
2
CHA_24BPP_MODE
CHB_24BPP_MODE
R/W
R/W
0
0
0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled
(default)
1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled
CHB_24BPP_MODE
0 – Force 18bpp; LVDS channel B lane 4 (A_Y3P/N) is disabled
(default)
1 – Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled
1
CHA_24BPP_FORMAT1
R/W
0
This field selects the 24bpp data format
0 – LVDS channel A lane A_Y3P/N transmits the 2 most
significant bits (MSB) per color; Format 2 (default)
1 – LVDS channel B lane A_Y3P/N transmits the 2 least
significant bits (LSB) per color; Format 1
Note1: This field must be ‘0’ when 18bpp data is received from
DSI.
Note2: If this field is set to ‘1’ and CHA_24BPP_MODE is ‘0’, the
SN65DSI84-Q1 will convert 24bpp data to 18bpp data for
transmission to an 18bpp panel. In this configuration, the
SN65DSI84-Q1 will not transmit the 2 LSB per color on LVDS
channel A, because LVDS channel A lane A_Y3P/N is disabled.
0
CHB_24BPP_FORMAT
R/W
0
This field selects the 24bpp data format
0 – LVDS channel B lane B_Y3P/N transmits the 2 most
significant bits (MSB) per color; Format 2 (default)
1 – LVDS channel B lane B_Y3P/N transmits the 2 least
significant bits (LSB) per color; Format 1
Note1: This field must be ‘0’ when 18bpp data is received from
DSI.
Note2: If this field is set to ‘1’ and CHB_24BPP_MODE is ‘0’, the
SN65DSI84-Q1 will convert 24bpp data to 18bpp data for
transmission to an 18bpp panel. In this configuration, the
SN65DSI84-Q1 will not transmit the 2 LSB per color on LVDS
channel B, because LVDS channel B lane B_Y3P/Nis disabled.
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8.6.1.4.2 Register 0x19
Figure 27. Register 0x19
7
6
5
4
3
2
1
0
Reserved
CHA_LVDS_V
OCM
Reserved
CHB_LVDS_V
OCM
CHA_LVDS_VOD_SWING
CHB_LVDS_VOD_SWING
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Register 0x19 Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Reserved
Reserved
6
CHA_LVDS_VOCM
R/W
0
This field controls the common mode output voltage for LVDS
Channel A
0 – 1.2V (default)
1 – 0.9V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set
to ‘01b’)
5
4
Reserved
R
Reserved
CHB_LVDS_VOCM
R/W
0
This field controls the common mode output voltage for LVDS
Channel B
0 – 1.2V (default)
1 – 0.9V (CSR 0x1B.1:0 CHB_LVDS_CM_ADJUST must be set
to ‘01b’)
3-2
1-0
CHA_LVDS_VOD_SWING
CHB_LVDS_VOD_SWING
R/W
R/W
01
01
This field controls the differential output voltage for LVDS
Channel A. See the Electrical Characteristics table for |VOD| for
each setting:
00, 01 (default), 10, 11.
This field controls the differential output voltage for LVDS
Channel B. See the Electrical Characteristics table for |VOD| for
each setting:
00, 01 (default), 10, 11.
8.6.1.4.3 Register 0x1A
Figure 28. Register 0x1A
7
6
5
4
3
2
1
0
Reserved
EVEN_ODD_S CHA_REVERS CHB_REVERS
Reserved
R
CHA_LVDS_TE CHB_LVDS_TE
WAP
E_LVDS
E_LVDS
RM
RM
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Register 0x1A Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Reserved
Reserved
6
EVEN_ODD_SWAP
R/W
0
0 – Odd pixels routed to LVDS Channel A and Even pixels
routed to LVDS Channel B (default)
1 – Odd pixels routed to LVDS Channel B and Even pixels
routed to LVDS Channel A
Note: When the SN65DSI84-Q1 is in two stream mode (CSR
0x10.6:5 = ‘10’), setting this bit to ‘1’ will cause the video stream
from DSI Channel A to be routed to LVDS Channel B and the
video stream from DSI Channel B to be routed to LVDS Channel
A.
28
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Table 15. Register 0x1A Field Descriptions (continued)
Bit
Field
CHA_REVERSE_LVDS
Type
Reset
Description
5
R/W
0
This bit controls the order of the LVDS pins for Channel A.
0 – Normal LVDS Channel A pin order. LVDS Channel A pin
order is the same as listed in the Terminal Assignments Section.
(default)
1 – Reversed LVDS Channel A pin order. LVDS Channel A pin
order is remapped as follows:
•
•
•
•
•
•
•
•
•
•
A_Y0P → A_Y3P
A_Y0N → A_Y3N
A_Y1P → A_CLKP
A_Y1N → A_CLKN
A_Y2P → A_Y2P
A_Y2N → A_Y2N
A_CLKP → A_Y1P
A_CLKN → A_Y1N
A_Y3P → A_Y0P
A_Y3N → A_Y0N
4
CHB_REVERSE_LVDS
R/W
0
This bit controls the order of the LVDS pins for Channel B.
0 – Normal LVDS Channel B pin order. LVDS Channel B pin
order is the same as listed in the Terminal Assignments Section.
(default)
1 – Reversed LVDS Channel B pin order. LVDS Channel B pin
order is remapped as follows:
•
•
•
•
•
•
•
•
•
•
B_Y0P → B_Y3P
B_Y0N → B_Y3N
B_Y1P → B_CLKP
B_Y1N → B_CLKN
B_Y2P → B_Y2P
B_Y2N → B_Y2N
B_CLKP → B_Y1P
B_CLKN → B_Y1N
B_Y3P → B_Y0P
B_Y3N → B_Y0N
3-2
1
Reserved
R
Reserved
CHA_LVDS_TERM
R/W
1
1
This bit controls the near end differential termination for LVDS
Channel A. This bit also affects the output voltage for LVDS
Channel A.
0 – 100Ω differential termination
1 – 200Ω differential termination (default)
0
CHB_LVDS_TERM
R/W
This bit controls the near end differential termination for LVDS
Channel B. This bit also affects the output voltage for LVDS
Channel B.
0 – 100Ω differential termination
1 – 200Ω differential termination (default)
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8.6.1.4.4 Register 0x1B
Figure 29. Register 0x1B
7
6
5
4
3
2
1
0
Reserved
R
CHA_LVDS_CM_ADJUST
R/W
Reserved
R
CHB_LVDS_CM_ADJUST
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Register 0x1B Field Descriptions
Bit
7-6
5-4
Field
Type
R
Reset
Description
Reserved
Reserved
CHA_LVDS_CM_ADJUST
R/W
00
This field can be used to adjust the common mode output
voltage for LVDS Channel A.
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%
3-2
1-0
Reserved
R
Reserved
CHB_LVDS_CM_ADJUST
R/W
00
This field can be used to adjust the common mode output
voltage for LVDS Channel B.
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%
Note for all video registers:
1. TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only. Others
are for normal operation unless the test pattern generation feature is enabled.
8.6.1.5 CSR Bit Field Definitions – Video Registers
8.6.1.5.1 Register 0x20
Figure 30. Register 0x20
7
6
5
4
3
2
1
0
CHA_ACTIVE_LINE_LENGTH_LOW
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Register 0x20 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_ACTIVE_LINE_LENGTH_LO R/W
W
0
This field controls the length in pixels of the active horizontal line
line that are received on DSI Channel A and output to LVDS
Channel A in single LVDS Channel mode(CSR 0x18.4=1),
Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).
The value in this field is the lower 8 bits of the 12-bit value for
the horizontal line length.
30
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8.6.1.5.2 Register 0x21
Figure 31. Register 0x21
7
6
5
4
3
2
1
0
Reserved
R
CHA_ACTIVE_LINE_LENGTH_HIGH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Register 0x21 Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
Reserved
R
Reserved
CHA_ACTIVE_LINE_LENGTH_HIG R/W
H
0
This field controls the length in pixels of the active horizontal line
that are received on DSI Channel A and output to LVDS
Channel A in single LVDS Channel mode(CSR 0x18.4=1),
Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).
The value in this field is the upper 4 bits of the 12-bit value for
the horizontal line length.
8.6.1.5.3 Register 0x24
Figure 32. Register 0x24
7
6
5
4
3
2
1
0
CHA_VERTICAL_DISPLAY_SIZE_LOW
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Register 0x24 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_VERTICAL_DISPLAY_SIZE_L R/W
OW
0
TEST PATTERN GENERATION PURPOSE ONLY. This field
controls the vertical display size in lines for LVDS Channel A in
single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in
dual LVDS Channel mode(CSR 0x18.4=0. The value in this field
is the lower 8 bits of the 12-bit value for the vertical display size.
8.6.1.5.4 Register 0x25
Figure 33. Register 0x25
7
6
5
4
3
2
1
0
Reserved
R
CHA_VERTICAL_DISPLAY_SIZE_HIGH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Register 0x25 Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
Reserved
R
Reserved
CHA_VERTICAL_DISPLAY_SIZE_ R/W
HIGH
0
TEST PATTERN GENERATION PURPOSE ONLY. This field
controls the vertical display size in lines for LVDS Channel A in
single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in
dual LVDS Channel mode(CSR 0x18.4=0). The value in this
field is the upper 4 bits of the 12-bit value for the vertical display
size
8.6.1.5.5 Register 0x28
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Figure 34. Register 0x28
7
6
5
4
3
2
1
0
CHA_SYNC_DELAY_LOW
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. Register 0x28 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_SYNC_DELAY_LOW
R/W
0
This field controls the delay in pixel clocks from when an HSync
or VSync is received on the DSI to when it is transmitted on the
LVDS interface for Channel A in single LVDS Channel
mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel
mode(CSR 0x18.4=0). The delay specified by this field is in
addition to the pipeline and synchronization delays in the
SN65DSI84-Q1. The additional delay is approximately 10 pixel
clocks. The Sync delay must be programmed to at least 32 pixel
clocks to ensure proper operation. The value in this field is the
lower 8 bits of the 12-bit value for the Sync delay.
8.6.1.5.6 Register 0x29
Figure 35. Register 0x29
7
6
5
4
3
2
1
0
Reserved
R
CHA_SYNC_DELAY_HIGH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Register 0x29 Field Descriptions
Bit
7-4
3-0
Field
Type
R
Reset
Description
Reserved
Reserved
CHA_SYNC_DELAY_HIGH
R/W
0
This field controls the delay in pixel clocks from when an HSync
or VSync is received on the DSI to when it is transmitted on the
LVDS interface for Channel A in single LVDS Channel
mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel
mode(CSR 0x18.4=0). The delay specified by this field is in
addition to the pipeline and synchronization delays in the
SN65DSI84-Q1. The additional delay is approximately 10 pixel
clocks. The Sync delay must be programmed to at least 32 pixel
clocks to ensure proper operation. The value in this field is the
upper 4 bits of the 12-bit value for the Sync delay.
8.6.1.5.7 Register 0x2C
Figure 36. Register 0x2C
7
6
5
4
3
2
1
0
CHA_HSYNC_PULSE_WIDTH_LOW
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Register 0x2C Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_HSYNC_PULSE_WIDTH_LO R/W
W
0
This field controls the width in pixel clocks of the HSync Pulse
Width for LVDS Channel A in single LVDS Channel mode(CSR
0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR
0x18.4=0). The value in this field is the lower 8 bits of the 10-bit
value for the HSync Pulse Width.
32
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8.6.1.5.8 Register 0x2D
Figure 37. Register 0x2D
7
6
5
4
3
2
1
0
Reserved
R
CHA_HSYNC_PULSE_WIDTH_
HIGH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Register 0x2D Field Descriptions
Bit
7-2
1-0
Field
Type
Reset
Description
Reserved
R
Reserved
CHA_HSYNC_PULSE_WIDTH_HIG R/W
H
0
This field controls the width in pixel clocks of the HSync Pulse
Width for LVDS Channel A in single LVDS Channel mode(CSR
0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR
0x18.4=0). The value in this field is the upper 2 bits of the 10-bit
value for the HSync Pulse Width.
8.6.1.5.9 Register 0x30
Figure 38. Register 0x30
7
6
5
4
3
2
1
0
CHA_VSYNC_PULSE_WIDTH_LOW
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. Register 0x30 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_VSYNC_PULSE_WIDTH_LO R/W
W
0
This field controls the length in lines of the VSync Pulse Width
for LVDS Channel A in single LVDS Channel mode(CSR
0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR
0x18.4=0). The value in this field is the lower 8 bits of the 10-bit
value for the VSync Pulse Width.
8.6.1.5.10 Register 0x31
Figure 39. Register 0x31
7
6
5
4
3
2
1
0
Reserved
R
CHA_VSYNC_PULSE_WIDTH_
HIGH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. Register 0x31 Field Descriptions
Bit
7-2
1-0
Field
Type
Reset
Description
Reserved
R
Reserved
CHA_VSYNC_PULSE_WIDTH_HIG R/W
H
0
This field controls the length in lines of the VSync Pulse Width
for LVDS Channel A in single LVDS Channel mode(CSR
0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR
0x18.4=0). The value in this field is the upper 2 bits of the 10-bit
value for the VSync Pulse Width.
8.6.1.5.11 Register 0x34
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Figure 40. Register 0x34
7
6
5
4
3
2
1
0
CHA_HORIZONTAL_BACK_PORCH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. Register 0x34 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_HORIZONTAL_BACK_PORC R/W
H
0
This field controls the time in pixel clocks between the end of the
HSync Pulse and the start of the active video data for LVDS
Channel A in single LVDS Channel mode(CSR 0x18.4=1),
Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).
8.6.1.5.12 Register 0x36
Figure 41. Register 0x36
7
6
5
4
3
2
1
0
CHA_VERTICAL_BACK_PORCH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. Register 0x36 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_VERTICAL_BACK_PORCH
R/W
0
TEST PATTERN GENERATION PURPOSE ONLY. This field
controls the number of lines between the end of the VSync
Pulse and the start of the active video data for LVDS Channel A
in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0).
8.6.1.5.13 Register 0x38
Figure 42. Register 0x38
7
6
5
4
3
2
1
0
CHA_HORIZONTAL_FRONT_PORCH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. Register 0x38 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_HORIZONTAL_FRONT_POR R/W
CH
0
TEST PATTERN GENERATION PURPOSE ONLY. This field
controls the time in pixel clocks between the end of the active
video data and the start of the HSync Pulse for LVDS Channel A
in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0).
34
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8.6.1.5.14 Register 0x3A
Figure 43. Register 0x3A
7
6
5
4
3
2
1
0
CHA_VERTICAL_FRONT_PORCH
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. Register 0x3A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHA_VERTICAL_FRONT_PORCH R/W
0
TEST PATTERN GENERATION PURPOSE ONLY. This field
controls the number of lines between the end of the active video
data and the start of the VSync Pulse for LVDS Channel A in
single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in
dual LVDS Channel mode(CSR 0x18.4=0).
8.6.1.5.15 Register 0x3C
Figure 44. Register 0x3C
7
6
5
4
3
2
1
0
Reserved
CHA_TEST_PA
TTERN
Reserved
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. Register 0x3C Field Descriptions
Bit
7-5
4
Field
Type
R
Reset
Description
Reserved
Reserved
CHA_TEST_PATTERN
R/W
0
TEST PATTERN GENERATION PURPOSE ONLY. When this
bit is set, the SN65DSI84-Q1 will generate a video test pattern
based on the values programmed into the Video Registers for
LDS Channel A in single LVDS Channel mode(CSR 0x18.4=1),
Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).
3-0
Reserved
R
Reserved
8.6.1.6 CSR Bit Field Definitions – IRQ Registers
8.6.1.6.1 Register 0xE0
Figure 45. Register 0xE0
7
6
5
4
3
2
1
0
Reserved
R
IRQ_EN
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. Register 0xE0 Field Descriptions
Bit
7-1
0
Field
Type
R
Reset
Description
Reserved
IRQ_EN
Reserved
R/W
0
When enabled by this field, the IRQ output is driven high to
communicate IRQ events.
0 – IRQ output is high-impedance (default)
1 – IRQ output is driven high when a bit is set in registers 0xE5
that also has the corresponding IRQ_EN bit set to enable the
interrupt condition
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8.6.1.6.2 Register 0xE1
Figure 46. Register 0xE1
7
6
5
4
3
2
1
0
CHA_SYNCH_ CHA_CRC_ER CHA_UNC_EC CHA_COR_EC CHA_LLP_ERR CHA_SOT_BIT
Reserved
PLL_UNLOCK_
EN
ERR_EN
R_EN
C_ERR_EN
C_ERR_EN
_EN
_ERR_EN
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. Register 0xE1 Field Descriptions
Bit
Field
Type
Reset
Description
7
CHA_SYNCH_ERR_EN
R/W
0
0 – CHA_SYNCH_ERR is masked
1 – CHA_SYNCH_ERR is enabled to generate IRQ events
6
5
4
3
2
CHA_CRC_ERR_EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0 – CHA_CRC_ERR is masked
1 – CHA_CRC_ERR is enabled to generate IRQ events
CHA_UNC_ECC_ERR_EN
CHA_COR_ECC_ERR_EN
CHA_LLP_ERR_EN
0 – CHA_UNC_ECC_ERR is masked
1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events
0 – CHA_COR_ECC_ERR is masked
1 – CHA_COR_ECC_ERR is enabled to generate IRQ events
0 – CHA_LLP_ERR is masked
1 – CHA_ LLP_ERR is enabled to generate IRQ events
CHA_SOT_BIT_ERR_EN
0 – CHA_SOT_BIT_ERR is masked
1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events
1
0
Reserved
R
Reserved
PLL_UNLOCK_EN
R/W
0
0 – PLL_UNLOCK is masked
1 – PLL_UNLOCK is enabled to generate IRQ events
36
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8.6.1.6.3 Register 0xE5
Figure 47. Register 0xE5
7
6
5
4
3
2
1
0
CHA_SYNCH_ CHA_CRC_ER CHA_UNC_EC CHA_COR_EC CHA_LLP_ERR CHA_SOT_BIT
Reserved
PLL_UNLOCK
ERR
R
C_ERR
C_ERR
_ERR
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34. Register 0xE5 Field Descriptions
Bit
Field
Type
Reset
Description
7
CHA_SYNCH_ERR
R/W
0
When the DSI channel A packet processor detects an HS or VS
synchronization error, that is, an unexpected sync packet; this
bit is set; this bit is cleared by writing a ‘1’ value.
6
5
CHA_CRC_ERR
R/W
R/W
0
0
When the DSI channel A packet processor detects a data
stream CRC error, this bit is set; this bit is cleared by writing a
‘1’ value.
CHA_UNC_ECC_ERR
When the DSI channel A packet processor detects an
uncorrectable ECC error, this bit is set; this bit is cleared by
writing a ‘1’ value.
4
3
CHA_COR_ECC_ERR
CHA_LLP_ERR
R/W
R/W
0
0
When the DSI channel A packet processor detects a correctable
ECC error, this bit is set; this bit is cleared by writing a ‘1’ value.
When the DSI channel A packet processor detects a low level
protocol error, this bit is set; this bit is cleared by writing a ‘1’
value.
Low level protocol errors include SoT and EoT sync errors,
Escape Mode entry command errors, LP transmission sync
errors, and false control errors. Lane merge errors are reported
by this status condition.
2
CHA_SOT_BIT_ERR
R/W
0
1
When the DSI channel A packet processor detects an SoT
leader sequence bit error, this bit is set; this bit is cleared by
writing a ‘1’ value.
1
0
Reserved
R
Reserved
PLL_UNLOCK
R/W
This bit is set whenever the PLL Lock status transitions from
LOCK to UNLOCK.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN65DSI84-Q1 device is primarily targeted for portable applications such as tablets and smart phones that
utilize the MIPI DSI video format. The SN65DSI84-Q1 device can be used between a GPU with DSI output and a
video panel with LVDS inputs
9.1.1 Video Stop and Restart Sequence
When the system requires to stop outputting video to the display, it is recommended to use the following
sequence for the SN65DSI84-Q1:
1. Clear the PLL_EN bit to 0 (CSR 0x0D.0)
2. Stop video streaming on DSI inputs
3. Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS.
When the system is ready to restart the video streaming.
1. Start video streaming on DSI inputs.
2. Set the PLL_EN bit to 1(CSR 0x0D.0).
3. Wait for a minimum of 3 ms.
4. Set the SOFT_RESET bit(0x09.0).
9.1.2 Reverse LVDS Pin Order Option
For ease of PCB routing, the SN65DSI84-Q1 supports swapping/reversing the channel or pin order via
configuration register programming. The order of the LVDS pin for LVDS Channel A or Channel B can be
reversed by setting the address 0x1A bit 5 CHA_REVERSE_LVDS or bit 4 CHB_REVERSE_LVDS. The LVDS
Channel A and Channel B can be swapped by setting the 0x1A.6 EVEN_ODD_SWAP bit. See the corresponding
register bit definition for details.
9.1.3 IRQ Usage
The SN65DSI84-Q1 provides an IRQ pin that can be used to indicate when certain errors occur on DSI. The IRQ
output is enabled through the IRQ_EN bit (CSR 0xE0.0). The IRQ pin will be asserted when an error occurs on
DSI, the corresponding error enable bit is set, and the IRQ_EN bit is set. An error is cleared by writing a ‘1’ to the
corresponding error status bit.
NOTE
If the SOFT_RESET bit is set while the DSI video stream is active, some of the error
status bits may be set.
If the DSI video stream is stopped, some of the error status bits may be set. These error
status bits should be cleared before restarting the video stream.
If the DSI video stream starts before the device is configured, some of the error status bits
may be set. TI recommends starting streaming after the device is correctly configured as
recommended in the initialization sequence in the Initialization Sequence section.
9.2 Typical Application
Figure 48 illustrates a typical application using the SN65DSI84-Q1 for a single channel DSI receiver to interface
a single-channel DSI application processor to an LVDS Dual-Link 18 bit-per-pixel panel supporting 1920 x 1200
WUXGA resolutions at 60 frames per second.
38
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Typical Application (continued)
SN65DSI84-Q1 A_Y0N
A_Y0P
100Ω
DA0P
DA0N
A_Y1N
A_Y1P
Application
Processor
100Ω
100Ω
100Ω
to odd pixel
row and column
drivers
DA1P
DA1N
A_Y2N
A_Y2P
DA2P
DA2N
A_CLKN
A_CLKP
DA3P
DA3N
A_Y3N
A_Y3P
DACP
DACN
B_Y0N
B_Y0P
SCL
SDA
100Ω
100Ω
100Ω
100Ω
IRQ
EN
B_Y1N
B_Y1P
to even pixel
row and column
drivers
ADDR
REFCLK
GND
B_Y2N
B_Y2P
B_CLKN
B_CLKP
1.8V
B_Y3N
B_Y3P
VCC
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 48. Typical 1920 x 1200 WUXGA 18-bpp Panel Application
9.2.1 Design Requirements
For the 1920 x 1200 WUXGA 18-bpp Panel typical application design parameters, see Table 35.
Table 35. Design Parameters
DESIGN PARAMETER
VCC
EXAMPLE VALUE
1.8V (±5%)
DSIA_CLK
N/A
CLOCK
REFCKL Frequency
DSIA Clock Frequency
PANEL INFORMATION
LVDS Output Clock Frequency
Resolution
490 MHz
81 MHz
1920 x 1200
Horizontal Active (pixels)
Horizontal Blanking (pixels)
Vertical Active (lines)
960
144
1200
Vertical Blanking (lines)
Horizontal Sync Offset (pixels)
Horizontal Sync Pulse Width (pixels)
Vertical Sync Offset (lines)
Vertical Sync Pulse Width (lines)
Horizontal Sync Pulse Polarity
Vertical Sync Pulse Polarity
Color Bit Depth (6bpc or 8bpc)
Number of LVDS Lanes
20
50
50
1
5
Negative
Negative
6-bit
2 X [3 Data Lanes + 1 Clock Lane]
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www.ti.com.cn
Typical Application (continued)
Table 35. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
DSI INFORMATION
Number of DSI Lanes
1 X [4 Data Lanes + 1 Clock Lane]
DSI Input Clock Frequency
Dual DSI Configuration(Odd/Even or Left/Right)
490MHz
N/A
9.2.2 Detailed Design Procedure
The video resolution parameters required by the panel must be programmed into the SN65DSI84-Q1. For this
example, the parameters programmed would be the following:
Horizontal active = 1920 or 0x780
CHA_ACTIVE_LINE_LENGTH_LOW = 0X80
CHA_ACTIVE_LINE_LENGTH_HIGH = 0x07
Horizontal pulse Width = 50 or 0x32
CHA_HSYNC_PULSE_WIDTH_LOW = 0x32
CHA_HSYNC_PULSE_WIDTH_HIGH= 0x00
Horizontal back porch = Horizontal blanking – (Horizontal sync offset + Horizontal sync pulse width)
Horizontal back porch = 144– (50 + 50)
Horizontal back porch = 44 or 0x2C
CHA_HORIZONTAL_BACK_PORCH = 0x2C
Vertical pulse width = 5
CHA_VSYNC_PULSE_WIDTH_LOW = 0x05
CHA_VSYNC_PULSE_WIDTH_HIGH= 0x00
The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and
configuring the following TEST PATTERN GENERATION PURPOSE ONLY registers.
Vertical active = 1200 or 0x4B0
CHA_VERTICAL_DISPLAY_SIZE_LOW = 0xB0
CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x04
Vertical back porch = Vertical blanking – (Vertical sync offset +Vertical sync pulse width)
Vertical back porch = 20 – (1 + 5)
Vertical back porch = 14 or 0x0E
CHA_VERTICAL_BACK_PORCH = 0x0E
Horizontal front porch = Horizontal sync offset
Horizontal front porch = 50 or 0x32
CHA_HORIZONTAL_FRONT_PORCH = 0x32
Vertical front porch = Vertical sync offset
Vertical front porch =1
CHA_VERTICAL_FRONT_PORCH = 0x01
40
Copyright © 2016–2018, Texas Instruments Incorporated
SN65DSI84-Q1
www.ti.com.cn
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
In this example, the clock source for the SN65DSI84-Q1 is the DSI clock. When the MIPI D-PHY clock is used as
the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the LVDS
output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be
set to the frequency range of the LVDS output clock and DSI Channel A input clock respectively for the internal
PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) should be set to enable
the internal PLL.
LVDS_CLK_RANGE = 010b-62.5 MHz ≤ LVDS_CLK < 87.5 MHz
HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock
DSI_CLK_DIVIDER = 0010b – Divide by 6
CHA_DSI_LANES = 00 – Four lanes are enabled
CHA_DSI_CLK_RANGE = 0x62 – 490 MHz ≤ frequency < 495 MHz
9.2.2.1 Example Script
This example configures the SN65DSI84-Q1 for the following configuration:
<aardvark>
<configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/>
<i2c_bitrate khz="100"/>
=====SOFTRESET=======
<i2c_write addr="0x2D" count="1" radix="16"glt;09 01</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0D=======
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
<i2c_write addr="0x2D" count="1" radix="16"glt;0D 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0A=======
======HS_CLK_SRC bit0===
======LVDS_CLK_Range bit 3:1======
<i2c_write addr="0x2D" count="1" radix="16"glt;0A 05</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0B=======
======DSI_CLK_DIVIDER bit7:3=====
======RefCLK multiplier(bit1:0)====== ======00 - LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4======
<i2c_write addr="0x2D" count="1" radix="16"glt;0B 28</i2c_writeglt;
<sleep ms="10"/>
======ADDR 10=======
======DSI Ch Confg Left_Right Pixels(bit7 - 0 for A ODD, B EVEN, 1 for the other config)======
======DSI Ch Mode(bit6:5) 00 - Dual, 01 - single, 10 - two single =======
======CHA_DSI_Lanes(bit4:3), CHB_DSI_Lanes(bit2:1), 00 - 4, 01 - 3, 10 - 2, 11 - 1
======SOT_ERR_TOL_DIS(bit0)=======
<i2c_write addr="0x2D" count="1" radix="16"glt;10 26</i2c_writeglt;
<sleep ms="10"/>
======ADDR 12=======
<i2c_write addr="0x2D" count="1" radix="16"glt;12 62</i2c_writeglt;
<sleep ms="10"/>
======ADDR 18=======
======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA 24bpp, bit2: CHB 24bpp,
bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1======
<i2c_write addr="0x2D" count="1" radix="16"glt;18 63</i2c_writeglt;
<sleep ms="10"/>
======ADDR 19=======
<i2c_write addr="0x2D" count="1" radix="16"glt;19 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 1A=======
<i2c_write addr="0x2D" count="1" radix="16"glt;1A 03</i2c_writeglt;
<sleep ms="10"/>
======ADDR 20=======
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SN65DSI84-Q1
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www.ti.com.cn
======CHA_LINE_LENGTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;20 80</i2c_writeglt;
<sleep ms="10"/>
======ADDR 21=======
======CHA_LINE_LENGTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;21 07</i2c_writeglt;
<sleep ms="10"/>
======ADDR 22=======
======CHB_LINE_LENGTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;22 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 23=======
======CHB_LINE_LENGTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;23 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 24=======
======CHA_VERTICAL_DISPLAY_SIZE_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;24 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 25=======
======CHA_VERTICAL_DISPLAY_SIZE_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;25 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 26=======
======CHB_VERTICAL_DISPLAY_SIZE_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;26 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 27=======
======CHB_VERTICAL_DISPLAY_SIZE_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;27 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 28=======
======CHA_SYNC_DELAY_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;28 20</i2c_writeglt;
<sleep ms="10"/>
======ADDR 29=======
======CHA_SYNC_DELAY_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;29 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2A=======
======CHB_SYNC_DELAY_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;2A 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2B=======
======CHB_SYNC_DELAY_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;2B 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2C=======
======CHA_HSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;2C 32</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2D=======
======CHA_HSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;2D 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2E=======
======CHB_HSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;2E 00</i2c_writeglt;
<sleep ms="10"/>
42
Copyright © 2016–2018, Texas Instruments Incorporated
SN65DSI84-Q1
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ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
======ADDR 2F=======
======CHB_HSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;2F 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 30=======
======CHA_VSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;30 05</i2c_writeglt;
<sleep ms="10"/>
======ADDR 31=======
======CHA_VSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;31 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 32=======
======CHB_VSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;32 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 33=======
======CHB_VSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;33 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 34=======
======CHA_HOR_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;34 2C</i2c_writeglt;
<sleep ms="10"/>
======ADDR 35=======
======CHB_HOR_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;35 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 36=======
======CHA_VER_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;36 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 37=======
======CHB_VER_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;37 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 38=======
======CHA_HOR_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;38 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 39=======
======CHB_HOR_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;39 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 3A=======
======CHA_VER_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;3A 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 3B=======
======CHB_VER_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;3B 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 3C=======
======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)========
<i2c_write addr="0x2D" count="1" radix="16"glt;3C 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0D=======
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
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<i2c_write addr="0x2D" count="1" radix="16"glt;0D 01</i2c_writeglt;
<sleep ms="10"/>
=====SOFTRESET=======
<i2c_write addr="0x2D" count="1" radix="16"glt;09 00</i2c_writeglt;
<sleep ms="10"/>
======write======
<i2c_write addr="0x2D" count="196" radix="16"glt;00</i2c_writeglt;
<sleep ms="10"/>
======Read======
<i2c_read addr="0x2D" count="256" radix="16"glt;00</i2c_readglt;
<sleep ms="10"/>
</aardvark>
9.2.3 Application Curve
SN65DSI84-Q1: SINGLE Channel DSI to DUAL Channel LVDS, 1440 x 900
111.0
Unit 1
110.0
Unit 2
109.0
Unit 3
108.0
107.0
106.0
105.0
104.0
103.0
102.0
0.0
20.0
40.0
60.0
80.0
œ40.0
œ20.0
Temperature (°C)
C001
Figure 49. Supply Current vs Temperature
44
Copyright © 2016–2018, Texas Instruments Incorporated
SN65DSI84-Q1
www.ti.com.cn
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
10 Power Supply Recommendations
10.1 VCC Power Supply
Each VCC power supply pin must have a 100-nF capacitor to ground connected as close as possible to the
SN65DSI84-Q1 device. It is recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also
recommended to have the pins connected to a solid power plane.
10.2 VCORE Power Supply
This pin must have a 100-nF capacitor to ground connected as close as possible to the SN65DSI84-Q1 device. It
is recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also recommended to have the pins
connected to a solid power plane.
11 Layout
11.1 Layout Guidelines
11.1.1 Package Specific
For the ZQE package, to minimize the power supply noise floor, provide good decoupling near the SN65DSI84-
Q1 device power pins. The use of four ceramic capacitors (2 × 0.1 μF and 2 × 0.01 μF) provides good
performance. At the least, TI recommends to install one 0.1-μF and one 0.01-μF capacitor near the SN65DSI84-
Q1 device. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and
device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI84-Q1 device on the
bottom of the PCB is often a good choice.
11.1.2 Differential Pairs
•
Differential pairs must be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended
impedance (±15%).
•
•
•
•
•
Keep away from other high speed signals
Keep lengths to within 5 mils of each other.
Length matching must be near the location of mismatch.
Each pair must be separated at least by 3 times the signal trace width.
The use of bends in differential traces must be kept to a minimum. When bends are used, the number of left
and right bends must be as equal as possible and the angle of the bend must be ≥ 135 degrees. This
arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that
bends have on EMI.
•
•
•
•
•
Route all differential pairs on the same of layer.
The number of vias must be kept to a minimum. It is recommended to keep the via count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will therefore negatively impact signal
performance. If test points are used, they must be placed in series and symmetrically. They must not be
placed in a manner that causes a stub on the differential pair.
11.1.3 Ground
TI recommends that only one board ground plane be used in the design. This provides the best image plane for
signal traces running above the plane. The thermal pad of the SN65DSI84-Q1 must be connected to this plane
with vias.
Copyright © 2016–2018, Texas Instruments Incorporated
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SN65DSI84-Q1
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11.2 Layout Example
NC pins must not be connected
to any signal, power or ground.
Place Vcc decoupling caps as
close to Vcc as possible
VCC 1.8V
B_Y3P
VCC 1.8V
1uF
DA3N
B_Y3N
DA3P
GND
B_CLKP
B_CLKN
VCC 1.8V
B_Y2P
DA2N
DA2P
GND
DACN
DACP
GND
GND
B_Y2N
VCC 1.8V
B_Y1P
DA1N
DA1P
DA0N
DA0P
VCC 1.8V
B_Y1N
B_Y0P
B_Y0N
VCC 1.8V
4.7lQ
10lQ
GND
VCC 1.8V
1
SDA
4.7lQ
4.7lQ
VCC 1.8V
VCC 1.8V
Differential pairs must be routed
with controlled 100-O differential
impedance
SCL
Figure 50. SN65DSI8x Layout Example
46
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SN65DSI84-Q1
www.ti.com.cn
ZHCSFS1A –DECEMBER 2016–REVISED JUNE 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
《SN65DSI8x 视频配置指南和配置工具用户手册》（文献编号：SLLA332）
《SN65DSI83、SN65DSI84 和 SN65DSI85 硬件实现指南》（文献编号：SLLA340）
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
MIPI is a registered trademark of Arasan Chip Systems, Inc..
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
48
版权 © 2016–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65DSI84TPAPRQ1
ACTIVE
HTQFP
PAP
64
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
DSI84TQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
PAP 64
10 x 10, 0.5 mm pitch
HTQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226442/A
www.ti.com
PACKAGE OUTLINE
TM
PAP0064Q
PowerPAD TQFP - 1.2 mm max height
SCALE 1.300
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
16
33
17
32
A
0.27
64X
60X 0.5
0.17
0.08
C A B
4X 7.5
C
SEATING PLANE
1.2 MAX
(0.127)
TYP
SEE DETAIL A
17
32
0.25
GAGE PLANE
(1)
4X 0.4 MAX
NOTE 4
33
16
4X 0.31 MAX
NOTE 4
0.15
0.05
0.08 C
0 -7
0.75
0.45
3.30
2.62
DETAIL A
65
A
17
4X (0.18)
NOTE 4
TYPICAL
4X (0.18)
NOTE 4
1
48
49
64
4223672/A 04/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
PAP0064Q
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
8)
NOTE 8
(
3.3)
SYMM
SOLDER MASK
49
64
DEFINED PAD
64X (1.5)
(R0.05)
TYP
1
48
64X (0.3)
65
(11.4)
SYMM
(1.3 TYP)
60X (0.5)
33
16
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
17
32
SEE DETAILS
(1.3 TYP)
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223672/A 04/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
PAP0064Q
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
3.3)
BASED ON
0.125 THICK STENCIL
SYMM
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
64
49
64X (1.5)
1
48
64X (0.3)
(R0.05) TYP
SYMM
65
(11.4)
60X (0.5)
33
16
METAL COVERED
BY SOLDER MASK
17
32
(11.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.69 X 3.69
3.3 X 3.3 (SHOWN)
3.01 X 3.01
0.125
0.15
0.175
2.79 X 2.79
4223672/A 04/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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