SN65HVD05DR [TI]
HIGH OUTPUT RS-485 TRANSCEIVERS; 高输出RS -485收发器
| 型号： | SN65HVD05DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH OUTPUT RS-485 TRANSCEIVERS |
| 文件： | 总24页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D–MAY 2002–REVISED JULY 2006
HIGH OUTPUT RS-485 TRANSCEIVERS
FEATURES
DESCRIPTION
•
•
•
Minimum Differential Output Voltage of 2.5 V
Into a 54-Ω Load
The SN65HVD05, SN75HVD05, SN65HVD06,
SN75HVD06, SN65HVD07, and SN75HVD07
combine
a 3-state differential line driver and
Open-Circuit, Short-Circuit, and Idle-Bus
Failsafe Receiver
1/8th Unit-Load Option Available (Up to 256
differential line receiver. They are designed for
balanced data transmission and interoperate with
ANSI
TIA/EIA-485-A
and
ISO
8482E
Nodes on the Bus)
standard-compliant devices. The driver is designed
to provide a differential output voltage greater than
that required by these standards for increased noise
margin. The drivers and receivers have active-high
and active-low enables respectively, which can be
externally connected together to function as direction
control.
•
•
•
Bus-Pin ESD Protection Exceeds 16 kV HBM
Driver Output Slew Rate Control Options
Electrically Compatible With ANSI
TIA/EIA-485-A Standard
•
•
Low-Current Standby Mode . . . 1 µA Typical
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
The driver differential outputs and receiver
differential inputs connect internally to form
a
differential input/ output (I/O) bus port that is
designed to offer minimum loading to the bus
whenever the driver is disabled or not powered.
These devices feature wide positive and negative
common-mode voltage ranges, making them suitable
for party-line applications.
•
Pin Compatible With Industry Standard
SN75176
APPLICATIONS
•
Data Transmission Over Long or Lossy Lines
or Electrically Noisy Environments
•
•
•
•
•
•
Profibus Line Interface
D OR P PACKAGE
(TOP VIEW)
Industrial Process Control Networks
Point-of-Sale (POS) Networks
Electric Utility Metering
Building Automation
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
CC
Digital Motor Control
GND
LOGIC DIAGRAM
(POSITIVE LOGIC)
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
5
1
T
= 25°C
A
R
4.5
4
DE at V
CC
D at V
CC
V
2
60 Ω Load
Line
= 5 V
RE
CC
3.5
30 Ω Load
Line
3
3
4
2.5
DE
D
6
7
A
B
2
1.5
1
0.5
0
0
20
40
60
80
100
120
I
- Differential Output Current - mA
OD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com
SLLS533D–MAY 2002–REVISED JULY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
MARKED AS
DRIVER
OUTPUT SLOPE
CONTROL
PLASTIC
DUAL-IN-LINE
PACKAGE
(PDIP)
SMALL
OUTLINE
IC (SOIC)
PACKAGE
SIGNALING
RATE
UNIT
LOAD
TA
PART NUMBER(2)
40 Mbps
10 Mbps
1 Mbps
1/2
1/8
1/8
1/2
1/8
1/8
No
Yes
Yes
No
SN65HVD05D SN65HVD05P
65HVD05
65HVD06
65HVD07
75HVD05
75HVD06
75HVD07
VP05
VP06
VP07
VN05
VN06
VN07
40°C to 85°C SN65HVD06D SN65HVD06P
SN65HVD07D SN65HVD07P
40 Mbps
10 Mbps
1 Mbps
SN75HVD05D SN75HVD05P
Yes
Yes
0°C to 70°C
SN75HVD06D SN75HVD06P
SN75HVD07D SN75HVD07P
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR).
PACKAGE DISSIPATION RATINGS
(See Figure 12 and Figure 13)
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D(2)
D(3)
P
710 mW
5.7 mW/°C
10.3 mW/°C
8.0 mW/°C
455 mW
821 mW
640 mW
369 mW
667 mW
520 mW
1282 mW
1000 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)(2)
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
Supply voltage range, VCC
-0.3 V to 6 V
-9 V to 14 V
Voltage range at A or B
Input voltage range at D, DE, R or RE
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 11)
Receiver output current, IO
-0.5 V to VCC + 0.5 V
-50 V to 50 V
–11 mA to 11mA
16 kV
A, B, and GND
Human body model(3)
Electrostatic discharge
All pins
All pins
4 kV
Charged-device model(4)
1 kV
Continuous total power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under" recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
2
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D–MAY 2002–REVISED JULY 2006
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supply voltage, VCC
4.5
-7(1)
2
5.5
12
V
V
V
V
V
Voltage at any bus terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
Low-level input voltage, VIL
D, DE, RE
D, DE, RE
0.8
12
Differential input voltage, VID (see Figure 7)
-12
-100
-8
Driver
High-level output current, IOH
Low-level output current, IOL
mA
mA
Receiver
Driver
100
8
Receiver
SN65HVD05
SN65HVD06
SN65HVD07
SN75HVD05
SN75HVD06
SN75HVD07
-40
0
85
70
°C
°C
Operating free-air temperature, TA
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
II = -18 mA
No Load
-1.5
V
VCC
|VOD
|
Differential output voltage
RL = 54 Ω, See Figure 4
2.5
2.2
V
Vtest = -7 V to 12 V, See Figure 2
Change in magnitude of differential output
voltage
∆|VOD
|
See Figure 4 and Figure 2
-0.2
2.2
0.2
3.3
0.1
V
V
V
VOC(SS)
Steady-state common-mode output voltage
See Figure 3
Change in steady-state common-mode
output voltage
∆VOC(SS)
-0.1
HVD05
600
500
900
Peak-to-peak common-mode
output voltage
VOC(PP)
HVD06 See Figure 3
mV
HVD07
IOZ
II
High-impedance output current
Input current
See receiver input currents
D
-100
0
0
100
250
µA
DE
IOS
Short-circuit output current
-7 V ≤ VO ≤ 12 V
-250
16
mA
pF
C(diff)
Differential output capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
RE at VCC
D & DE at VCC
No load
,
Receiver disabled
and driver enabled
,
9
1
9
15
5
mA
µA
RE at VCC
,
Receiver disabled
ICC
Supply current
D at VCC DE at 0 V, and driver disabled
No load
(standby)
RE at 0 V,
D & DE at VCC
No load
Receiver enabled
and driver enabled
,
15
mA
(1) All typical values are at 25°C and with a 5-V supply.
3
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SN75HVD05, SN65HVD07
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SLLS533D–MAY 2002–REVISED JULY 2006
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
HVD05
6.5
27
11
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tPHL - tPLH|)
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
40
400
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
250
6.5
27
40
250
400
6
2.7
18
3.6
28
RL = 54 Ω, CL = 50 pF,
See Figure 4
55
150
2.7
18
300
3.6
28
450
6
tf
55
150
300
450
2
tsk(p)
tsk(pp)
tPZH1
tPHZ
tPZL1
tPLZ
2.5
10
3.5
14
(2)
Part-to-part skew
100
25
Propagation delay time,
high-impedance-to-high-level output
45
250
25
RE at 0 V, RL = 110 Ω,
See Figure 5
Propagation delay time,
high-level-to-high-impedance output
60
250
15
Propagation delay time,
high-impedance-to-low-level output
45
200
14
RE at 0 V, RL = 110 Ω,
See Figure 6
Propagation delay time,
low-level-to-high-impedance output
90
550
RL = 110Ω , RE at 3 V,
See Figure 5
tPZH2
tPZL2
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
6
6
µs
µs
RL = 110 Ω, RE at 3 V,
See Figure 6
(1) All typical values are at 25°C and with a 5-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D–MAY 2002–REVISED JULY 2006
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
Positive-going input
threshold voltage
VIT+
VIT-
Vhys
VIK
IO = -8 mA
IO = 8 mA
0.01
V
Negative-going input
threshold voltage
-0.2
Hysteresis voltage
35
mV
V
(VIT+ - VIT-
)
Enable-input clamp
voltage
II = -18 mA
-1.5
4
VOH
VOL
High-level output voltage
Low-level output voltage
VID = 200 mV,
VID = -200 mV,
IOH = -8 mA,
IOL = 8 mA,
See Figure 7
See Figure 7
V
V
0.4
1
High-impedance-state
output current
IOZ
VO = 0 or VCC
RE at VCC
-1
µA
VA or VB = 12 V
VA or VB = 12 V,
VA or VB = -7 V
VA or VB = -7 V,
VA or VB = 12 V
VA or VB = 12 V,
VA or VB = -7 V
VA or VB = -7 V,
0.23
0.3
0.5
0.5
VCC = 0 V
VCC = 0 V
VCC = 0 V
VCC = 0 V
HVD05 Other inputat 0 V
mA
-0.4
-0.4
0.13
0.15
0.06
0.08
0.05
0.03
II
Bus input current
0.1
0.13
HVD06
Other inputat 0 V
HVD07
mA
-0.1
-0.05
High-level input current,
RE
IIH
VIH = 2 V
-60
-60
26.4
27.4
16
5
µA
µA
pF
Low-level input current,
RE
IIL
VIL = 0.8 V
Differential input
capacitance
C(diff)
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
RE at 0 V, D & DE at
0 V, No load
Receiver enabled and driver disabled
10
5
mA
µA
RE at VCC, DE at 0 V, Receiver disabled and driver disabled
D at VCC, No load
RE at 0 V,
1
ICC
Supply current
(standby)
D & DE at VCC
,
Receiver enabled and driver enabled
9
15
mA
No load
(1) All typical values are at 25°C and with a 5-V supply.
5
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SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
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SLLS533D–MAY 2002–REVISED JULY 2006
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output 1/2 UL HVD05
Propagation delay time, high-to-low-level output 1/2 UL HVD05
14.6
14.6
55
25
25
70
70
70
70
2
ns
ns
HVD06
Propagation delay time, low-to-high-level output 1/8 UL
HVD07
tPLH
ns
ns
55
VID = -1.5 V to 1.5 V,
See Figure 8
HVD06 CL = 15 pF,
55
tPHL
Propagation delay time, high-to-low-level output 1/8 UL
HVD07
HVD05
HVD06
HVD07
HVD05
HVD06
HVD07
55
tsk(p)
Pulse skew (|tPHL - tPLH|)
4.5
4.5
6.5
14
14
3
ns
(2)
tsk(pp)
Part-to-part skew
ns
ns
tr
Output signal rise time
2
2
CL = 15 pF,
See Figure 8
tf
Output signal fall time
3
tPZH1
tPZL1
tPHZ
tPLZ
tPZH2
tPZL2
Output enable time to high level
Output enable time to low level
10
10
15
15
6
CL = 15 pF,
DE at 3 V,
See Figure 9
ns
µs
Output disable time from high level
Output disable time from low level
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
CL = 15 pF, DE at 0,
See Figure 10
6
(1) All typical values are at 25°C and with a 5-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
V
CC
I
DE
OA
OB
I
I
A
B
V
OD
54 Ω ±1%
0 or 3 V
I
V
I
V
OB
V
OA
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
V
CC
DE
A
B
D
V
OD
60 Ω ±1%
0 or 3 V
+ -7 V < V
(test)
_
< 12 V
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
6
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SLLS533D–MAY 2002–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V
A
B
A
V
CC
27 Ω ± 1%
27 Ω ± 1%
V
B
DE
A
B
D
V
OC(PP)
∆V
OC(SS)
Input
V
OC
V
C
L
= 50 pF ±20%
OC
C
L
Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t <6ns, t <6ns, Z = 50 Ω
r
f
O
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3 V
V
CC
1.5 V
1.5 V
V
I
DE
C
C
= 50 pF ±20%
L
0 V
A
B
V
OD
D
t
t
PHL
Includes Fixture
and Instrumentation
Capacitance
PLH
L
≈ 2 V
Input
Generator
R
± 1%
= 54 Ω
90%
90%
L
V
I
50 Ω
0 V
10%
0 V
10%
V
OD
≈ –2 V
t
r
t
f
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
3 V
0 V
A
S1
D
V
O
V
1.5 V
1.5 V
I
3 V
B
DE
0.5 V
R
L
= 110 Ω
C
L
= 50 pF ±20%
t
PZH(1 & 2)
Input
Generator
± 1%
V
OH
V
I
C
Includes Fixture
50 Ω
L
and Instrumentation
Capacitance
V
O
2.3 V
≈ 0 V
t
PHZ
Generator: PRR = 100 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
V
CC
R
± 1%
= 110 Ω
L
≈ 3 V
A
B
V
t
1.5 V
1.5 V
S1
I
D
V
O
3 V
0 V
t
PZL(1 & 2)
PLZ
DE
V
CC
C
= 50 pF ±20%
Input
Generator
L
V
I
50 Ω
0.5 V
C
L
Includes Fixture
and Instrumentation
Capacitance
V
O
2.3 V
V
OL
Generator: PRR = 100 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
7
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SLLS533D–MAY 2002–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
I
A
A
B
I
O
R
V
A
V
I
ID
V
B
V
IC
V
O
B
V
A
+ V
2
B
Figure 7. Receiver Voltage and Current Definitions
A
3 V
V
O
R
Input
Generator
1.5 V
1.5 V
V
I
V
I
50 Ω
B
1.5 V
0 V
C
C
= 15 pF ±20%
0 V
V
L
t
t
PHL
PLH
RE
Includes Fixture
and Instrumentation
Capacitance
L
OH
90% 90%
V
O
1.5 V
10%
1.5 V
10%
V
OL
Generator: PRR = 100 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
t
r
t
f
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8
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SLLS533D–MAY 2002–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A
B
D
0 V or 3 V
Generator: PRR = 100 kHz,
50% Duty Cycle,
DE
RE
3 V
t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Input
Generator
V
I
50 Ω
A
V
CC
V
O
R
S1
B
1 kΩ ± 1%
C
C
= 15 pF ±20%
L
Includes Fixture and
Instrumentation Capacitance
L
3 V
V
I
1.5 V
1.5 V
0 V
V
t
t
PHZ
PZH(1)
OH
D at 3 V
S1 to B
V
OH
–0.5 V
1.5 V
V
O
≈ 0 V
t
t
PLZ
PZL(1)
V
CC
D at 0 V
S1 to A
1.5 V
V
O
V
OL
+0.5 V
V
OL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
9
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SLLS533D–MAY 2002–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Generator: PRR = 100 kHz,
50% Duty Cycle,
DE
RE
t <6 ns, t <6 ns, Z = 50 Ω
0 V
r
f
o
Input
Generator
V
I
50 Ω
A
B
A
0 V or 1.5 V
1.5 V or 0 V
V
CC
V
O
R
S1
B
1 kΩ ± 1%
C
C
= 15 pF ±20%
L
Includes Fixture and
Instrumentation Capacitance
L
3 V
1.5 V
V
I
0 V
V
t
PZH(2)
OH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
V
O
GND
t
PZL(2)
V
CC
A at 0 V
B at 1.5 V
S1 to A
1.5 V
V
O
V
OL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
RE
A
R
B
100 Ω
± 1%
Pulse Generator,
D
15 µs Duration,
1% Duty Cycle
+
_
t , t ≤ 100 ns
r
f
DE
3 V or 0 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 11. Test Circuit, Transient Over Voltage Test
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SLLS533D–MAY 2002–REVISED JULY 2006
FUNCTION TABLES
DRIVER
INPUT
D
ENABLE
DE
OUTPUTS
A
B
H
L
X
Open
X
H
H
L
H
Open
H
L
Z
H
Z
L
H
Z
L
Z
RECEIVER(1)
DIFFERENTIAL INPUTS
VID = VA - VB
ENABLE
RE
OUTPUT
R
V
ID≤ -0.2 V
L
L
L
?
-0.2 V < VID < -0.01 V
-0.01 V≤ VID
L
H
L
H
Z
H
H
Z
X
Open Circuit
Short Circuit
X
L
Open
(1) H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
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SLLS533D–MAY 2002–REVISED JULY 2006
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
V
CC
V
CC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
16 V
100 kΩ
16 V
R1
R1
R3
R2
R3
Input
Input
100 kΩ
16 V
R2
16 V
A and B Outputs
R Output
V
CC
V
CC
16 V
5 Ω
Output
9 V
Output
16 V
R1/R2
9 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
SN65HVD05
SN65HVD06
SN65HVD07
36 kΩ
36 kΩ
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SN75HVD05, SN65HVD07
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SLLS533D–MAY 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS
HVD05
HVD06
MAXIMUM RECOMMENDED STILL-AIR
OPERATING TEMPERATURE
vs
MAXIMUM RECOMMENDED STILL-AIR
OPERATING TEMPERATURE
vs
SIGNALING RATE
(D-PACKAGE)
SIGNALING RATE
(D-PACKAGE)
85
25
85
25
High K Board
High K Board
Low K Board
Low K Board
1
10
1
10
40
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 12.
Figure 13.
HVD05
RMS SUPPLY CURRENT
vs
HVD06
RMS SUPPLY CURRENT
vs
SIGNALILNG RATE
SIGNALING RATE
120
120
T = 25°C
R = 54 Ω
L
C = 50 pF
L
A
T = 25°C
R = 54 Ω
L
C = 50 pF
L
A
RE at V
DE at V
CC
CC
RE at V
DE at V
110
100
90
CC
CC
V
CC
= 5 V
V
CC
= 5 V
100
80
80
70
60
50
60
40
40
30
0
2.5
5
7.5
10
0
5
10
15
20
25
30
35
40
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 14.
Figure 15.
13
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SN75HVD05, SN65HVD07
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SLLS533D–MAY 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
HVD07
RMS SUPPLY CURRENT
BUS INPUT CURRENT
vs
vs
SIGNALING RATE
BUS INPUT VOLTAGE
110
100
90
250
200
T
= 25°C
R = 54 Ω
L
A
T
= 25°C
A
RE at V
DE at V
C
L
= 50 pF
CC
CC
DE at 0 V
= 5 V
V
CC
= 5 V
V
CC
150
100
HVD05
80
50
0
70
HVD06
HVD07
-50
-100
60
50
40
-150
-200
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 1011 12
100
400
700
1000
Signaling Rate - kbps
V - Bus Input Voltage - V
I
Figure 16.
Figure 17.
DRIVER HIGH-LEVEL OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
160
140
0
T
= 25°C
A
T
= 25°C
A
DE at V
CC
DE at V
D at V
V
-20
CC
D at 0 V
= 5 V
CC
V
CC
= 5 V
CC
120
-40
-60
100
80
-80
60
-100
-120
-140
-160
40
20
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
O
- High-Level Output Voltage - V
V
O
- Low-Level Output Voltage - V
Figure 18.
Figure 19.
14
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SN75HVD05, SN65HVD07
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SLLS533D–MAY 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
DRIVER OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
4
70
60
T
= 25°C
DE at V
D at V
CC
A
CC
DE at V
D at V
R
3.8
3.6
3.4
3.2
3
CC
V
CC
= 5 V
CC
= 54 Ω
R
L
= 54 Ω
L
50
40
30
20
2.8
2.6
2.4
2.2
10
0
2
-40
0
0.6 1.2 1.8 2.4
3
3.6 4.2 4.8 5.4
-15
10
35
60
85
V
CC
- Supply Voltage - V
T
A
- Free-Air Temperature - °C
Figure 20.
Figure 21.
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
ENABLE TIME
vs
COMMON-MODE VOLTAGE (SEE Figure 24)
5
4.5
4
600
500
400
T
= 25°C
A
DE at V
D at V
V
CC
CC
HVD07
HVD5
= 5 V
CC
60 Ω Load
Line
3.5
30 Ω Load
Line
3
2.5
300
200
HVD06
2
1.5
1
100
0
0.5
0
0
20
OD
40
60
80
100
120
-7
-2
3
8
13
I
- Differential Output Current - mA
V
− Common-Mode Voltage − V
(TEST)
Figure 22.
Figure 23.
15
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SLLS533D–MAY 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
375 W ± 1%
Y
-7 V < V(TEST) < 12 V
D
60 W
± 1%
VOD
0 or 3 V
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0 V
tpZL(diff)
-1.5 V
VOD (low)
Figure 24. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
16
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SLLS533D–MAY 2002–REVISED JULY 2006
APPLICATION INFORMATION
R
T
R
T
Device
HVD05
HVD06
HVD07
Number of Devices on Bus
64
256
256
NOTE: The line should be terminated at both ends with its characteristic impedance (R = Z ).
T
O
Stub lengths off the main line should be kept as short as possible.
Figure 25. Typical Application Circuit
17
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device
SN65HVD05D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD05DG4
SN65HVD05DR
SN65HVD05DRG4
SN65HVD05P
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
D
D
D
P
P
D
D
D
D
P
P
D
D
D
D
P
P
D
D
D
D
P
P
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD05PE4
SN65HVD06D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD06DG4
SN65HVD06DR
SN65HVD06DRG4
SN65HVD06P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD06PE4
SN65HVD07D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD07DG4
SN65HVD07DR
SN65HVD07DRG4
SN65HVD07P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD07PE4
SN75HVD05D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75HVD05DG4
SN75HVD05DR
SN75HVD05DRG4
SN75HVD05P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD05PE4
SN75HVD06D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
Orderable Device
SN75HVD06DG4
SN75HVD06DR
SN75HVD06DRG4
SN75HVD06P
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
P
P
D
D
D
D
P
P
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD06PE4
SN75HVD07D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75HVD07DG4
SN75HVD07DR
SN75HVD07DRG4
SN75HVD07P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD07PE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
(mm)
SN65HVD05DR
SN65HVD06DR
SN65HVD07DR
SN75HVD05DR
SN75HVD06DR
SN75HVD07DR
D
D
D
D
D
D
8
8
8
8
8
8
SITE 27
SITE 27
SITE 27
SITE 27
SITE 27
SITE 27
0
0
0
0
0
0
6.4
6.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
2.1
2.1
8
8
8
8
8
8
12
12
12
12
12
12
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65HVD05DR
SN65HVD06DR
SN65HVD07DR
SN75HVD05DR
SN75HVD06DR
SN75HVD07DR
D
D
D
D
D
D
8
8
8
8
8
8
SITE 27
SITE 27
SITE 27
SITE 27
SITE 27
SITE 27
342.9
342.9
342.9
342.9
342.9
342.9
336.6
336.6
336.6
336.6
336.6
336.6
0.0
0.0
0.0
0.0
0.0
0.0
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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