SN65HVD08 [TI]
WIDE SUPPLY RANGE RS-485 TRANSCEIVER; 宽电源范围RS- 485收发器
| 型号： | SN65HVD08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | WIDE SUPPLY RANGE RS-485 TRANSCEIVER |
| 文件： | 总17页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75HVD08, SN65HVD08
www.ti.com
SLLS550C–NOVEMBER 2002–REVISED JULY 2006
WIDE SUPPLY RANGE RS-485 TRANSCEIVER
The driver differential outputs and receiver
differential inputs connect internally to form
FEATURES
a
•
Operates With a 3-V to 5.5-V Supply
differential input/output (I/O) bus port that is designed
to offer minimum loading to the bus whenever the
driver is disabled or not powered. The drivers and
receivers have active-high and active-low enables
respectively, which can be externally connected
together to function as a direction control.
•
Consumes Less Than 90 mW Quiescent
Power
•
Open-Circuit, Short Circuit, and Idle-Bus
Failsafe Receiver
•
•
•
1/8th Unit-Load (up to 256 nodes on the bus)
D or P PACKAGE
(TOP VIEW)
Bus-Pin ESD Protection Exceeds 16 kV HBM
Driver Output Voltage Slew-Rate Limited for
Optimum Signal Quality at 10 Mbps
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
CC
•
Electrically Compatible With ANSI
TIA/EIA-485 Standard
GND
APPLICATIONS
•
Data Transmission With Remote Stations
Powered From the Host
LOGIC DIAGRAM (Positive Logic)
•
•
•
•
Isolated Multipoint Data Buses
Industrial Process Control Networks
Point-of-Sale Networks
A
B
D
DE
RE
Electric Utility Metering
DESCRIPTION
R
The SN65HVD08 combines a 3-state differential line
driver and differential line receiver designed for
balanced data transmission and interoperation with
ANSI
TIA/EIA-485-A
and
ISO-8482E
standard-compliant devices.
The wide supply voltage range and low quiescent
current requirements allow the SN65HVD08s to
operate from a 5-V power bus in the cable with as
much as a 2-V line voltage drop. Busing power in the
cable can alleviate the need for isolated power to be
generated at each connection of a ground-isolated
bus.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN75HVD08, SN65HVD08
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
Remote
(One of n Shown)
Host
5 V Power
Isolation
Barrier
Direct
Connection
to Host
SN65HVD08
5 V Return
Power Bus and Return Resistance
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
SPECIFIED TEMPERATURE
PART NUMBER
PACKAGE
PACKAGE MARKING
RANGE
SN65HVD08D
SN65HVD08P
SN75HVD08D
SN75HVD08P
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
SOIC
PDIP
SOIC
PDIP
VP08
65HVD08
VN08
75HVD08
PACKAGE DISSIPATION RATINGS
PACKAGE
SOIC (D)
PDIP (P)
TA≤ 25°C POWER RATING
710 mW
DERATING FACTOR ABOVE TA = 25°C
TA = 85°C POWER RATING
369 mW
5.7 mW/°C
8 mW/°C
1000 mW
520 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)(2)
UNIT
-0.3 V to 6 V
-9 V to 14 V
Supply voltage, VCC
Voltage range at A or B
Input voltage range at D, DE, R or RE
Voltage input range, transient pulse, A and B, through 100 Ω
Receiver ouput current, IO
-0.5 V to VCC + 0.5 V
-25 V to 25 V
–11 mA to 11 mA
16 kV
A, B, and GND
All pins
(3)
Human Body Model
Electrostatic discharge
4 kV
Charged-Device Model(4)
All pins
1 kV
Continuous total power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, VCC
Input voltage at any bus terminal (separately or common mode), VI(1)
3
–7
5.5
12
V
V
High-level input voltage, VIH
2.25
0
VCC
0.8
12
Driver, driver enable, and receiver enable inputs
V
Low-level input voltage, VIL
Differential input voltage, VID
–12
–60
–8
Driver
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
mA
mA
°C
Receiver
Driver
60
8
Receiver
SN75HVD08
SN65HVD08
0
70
85
–40
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
|VOD
∆|VOD
VOC(PP)
VIT+
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL= 60 Ω, 375 Ω on each output to
-7 V to 12 V, See Figure 1
|
Driver differential output voltage magnitude
1.5
VCC
V
Change in magnitude of driver differential
output voltage
|
RL= 54 Ω
–0.2
0.2
V
Peak-to-peak driver common-mode output
voltage
Center of two 27-Ω load
resistors, See Figure 2
0.5
V
Positive-going receiver differential input
voltage threshold
–10
mV
mV
mV
Negative-going receiver differential input
voltage threshold
VIT-
–200
Receiver differential input voltage threshold
hysteresis(VIT+ - VIT-
Vhys
35
)
VOH
VOL
Receiver high-level output voltage
Receiver low-level output voltage
IOH = -8 mA
IOL = 8 mA
2.4
V
V
0.4
Driver input, driver enable, and receiver
enable high-level input current
IIH
–100
100
µA
Driver input, driver enable, and receiver
enable low-level input current
IIL
–100
–265
100
µA
IOS
Driver short-circuit output current
7 V < VO < 12 V
VI = 12 V
265
130
mA
VI = -7 V
–100
–100
II
Bus input current (disabled driver)
µA
VI = 12 V, VCC = 0 V
VI = -7 V. VCC = 0 V
130
Receiver enabled, driver
disabled, no load
10
16
mA
Driver enabled, receiver
disabled, no load
ICC
Supply current
Both disabled
5
µA
Both enabled, no load
16
mA
3
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
18
TYP
MAX UNIT
tPHL
tPLH
tr
Driver high-to-low propagation delay time
40
40
Driver low-to-high propagation delay time
Driver 10%-to-90% differential output rise time
Driver 90%-to-10% differential output fall time
Driver differential output pulse skew, |tPHL - tPLH
18
RL = 54 Ω, CL = 50 pF,See Figure 3
10
55
55
2.5
55
6
ns
tf
10
tSK(P)
|
Receiver enabled, See Figures 4 and 5
Receiver disabled, See Figures 4 and 5
Receiver enabled, See Figures 4 and 5
ns
µs
ns
ten
Driver enable time
Driver disable time
tdis
90
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPHL
tPLH
tr
Receiver high-to-low propagation delay time
Receiver low-to-high propagation delay time
Receiver 10%-to-90% differential output rise time
Receiver 90%-to-10% differential output fall time
Receiver differential output pulse skew, |tPHL - tPLH
70
70
CL = 15 pF, See Figure 6
5
5
ns
tf
tSK(P)
|
4.5
15
6
Driver enabled, See Figure 7
Driver disabled, See Figure 8
Driver enabled, See Figure 7
ns
µs
ns
ten
Receiver enable time
Receiver disable time
tdis
20
PARAMETER MEASUREMENT INFORMATION
375 Ω ±1%
V
CC
DE
A
B
D
V
OD
60 Ω ±1%
0 or 3 V
+
–7 V < V
< 12 V
(test)
_
375 Ω ±1%
Figure 1. Driver VOD With Common-Mode Loading Test Circuit
V
A
A
V
CC
27 Ω ± 1%
V
B
DE
B
A
D
V
OC(PP)
∆V
OC(SS)
Input
27 Ω ± 1%
V
OC
B
V
OC
C
L
= 50 pF ±20%
C
L
Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t <6ns, t <6ns, Z = 50 Ω
r
f
O
Figure 2. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
3 V
V
CC
1.5 V
1.5 V
V
I
DE
C
C
= 50 pF ±20%
L
A
B
V
OD
D
t
t
PHL
Includes Fixture
and Instrumentation
Capacitance
PLH
L
≈ 2 V
Input
Generator
R
± 1%
= 54 Ω
90%
90%
L
V
I
50 Ω
0 V
10%
0 V
10%
V
OD
≈ –2 V
t
r
t
f
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 3. Driver Switching Test Circuit and Voltage Waveforms
3 V
0 V
A
S1
D
V
O
V
1.5 V
1.5 V
I
3 V
B
C
DE
0.5 V
R
L
= 110 Ω
= 50 pF ±20%
t
L
PZH
Input
Generator
± 1%
V
OH
V
I
C
Includes Fixture
50 Ω
L
and Instrumentation
Capacitance
V
O
2.3 V
≈ 0 V
t
PHZ
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 4. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
3 V
R
± 1%
= 110 Ω
L
≈ 3 V
A
V
I
1.5 V
1.5 V
S1
D
V
O
3 V
0 V
B
C
t
t
PLZ
PZL
DE
50 Ω
≈ 3 V
= 50 pF ±20%
Input
Generator
L
V
I
0.5 V
C
Includes Fixture
L
V
O
2.3 V
and Instrumentation
Capacitance
V
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 5. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A
B
V
O
R
Input
Generator
V
I
50 Ω
1.5 V
0 V
C
C
= 15 pF ±20%
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
1.5 V
V
I
0 V
t
t
PHL
PLH
V
V
OH
90% 90%
V
O
1.5 V
10%
1.5 V
10%
OL
t
r
t
f
Figure 6. Receiver Switching Test Circuit and Voltage Waveforms
3 V
DE
V
CC
A
B
A
1 kΩ ± 1%
= 15 pF ±20%
R
V
O
D
S1
B
0 V or 3 V
C
C
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
V
I
1.5 V
PZH
1.5 V
PHZ
0 V
V
t
t
OH
D at 3 V
S1 to B
V
OH
–0.5 V
1.5 V
V
O
≈ 0 V
t
t
PLZ
PZL
≈ V
CC
D at 0 V
S1 to A
1.5 V
V
O
V
OL
+0.5 V
V
OL
Figure 7. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
A
B
A
1 kΩ ± 1%
= 15 pF ±20%
0 V or 1.5 V
1.5 V or 0 V
R
V
O
S1
B
C
C
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
PZH
V
I
0 V
V
t
OH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
V
O
GND
t
PZL
≈ V
CC
A at 0 V
B at 1.5 V
S1 to A
1.5 V
V
O
V
OL
Figure 8. Receiver Enable Time From Standby (Driver Disabled)
DEVICE INFORMATION
Function Tables
DRIVER
INPUT ENABLE
OUTPUTS
D
DE
A
B
H
L
X
H
H
L
H
L
Z
H
L
H
Z
L
Open
H
RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
ENABLE(1)
OUTPUT(1)
R
RE
V
ID≤ -0.2 V
L
L
L
H
L
L
L
?
H
Z
H
H
-0.2 V < VID < -0.01 V
-0.01 V ≤ VID
X
Open Circuit
Short Circuit
(1) H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
V
CC
V
CC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
16 V
100 kΩ
16 V
36 kΩ
36 kΩ
180 kΩ
36 kΩ
180 kΩ
36 kΩ
Input
Input
100 kΩ
16 V
16 V
A and B Outputs
R Output
V
CC
V
CC
16 V
5 Ω
Output
9 V
Output
16 V
8
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
DRIVER OUTPUT CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.5
3
70
60
D and DE at V
CC
T
= 25°C
A
T
A
= –40°C
R
L
= 54 Ω
DE at V
D at V
R
CC
CC
= 54 Ω
T
A
= 25°C
L
50
40
T
= 85°C
A
2.5
2
30
20
1.5
10
0
1
2.5
3
3.5
4
4.5
5
5.5
6
0
0.6 1.2 1.8 2.4
3
3.6 4.2 4.8 5.4
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 9.
Figure 10.
RMS SUPPLY CURRENT
vs
LOGIC INPUT THRESHOLD VOLTAGE
vs
SIGNALING RATE
SUPPLY VOLTAGE
2.5
2
120
T
= 25°C
R = 54 Ω
T
= 25°C
A
L
A
RE at V
DE at V
C
L
= 50 pF
D, DE or RE input
CC
CC
V
CC
= 5 V
Positive Going
100
80
1.5
1
Negative Going
60
40
0.5
0
0
2.5
5
7.5
10
2.5
3.5
4.5
5.5
6.5
V
CC
– Supply Voltage – V
Signaling Rate – Mbps
Figure 11.
Figure 12.
9
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
TYPICAL CHARACTERISTICS (continued)
ENABLE TIME
vs
COMMON-MODE VOLTAGE (SEE Figure 14)
500
450
400
350
300
250
200
150
3.3 V
5 V
100
50
0
-7
-2
3
8
13
V
− Common-Mode Voltage − V
(TEST)
Figure 13.
375 W ± 1%
Y
-7 V < V(TEST) < 12 V
D
60 W
± 1%
VOD
0 or 3 V
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0 V
tpZL(diff)
-1.5 V
VOD (low)
Figure 14. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
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SLLS550C–NOVEMBER 2002–REVISED JULY 2006
APPLICATION INFORMATION
As electrical loads are physically distanced from their
power source, the effects of supply and return line
impedance and the resultant voltage drop must be
accounted. If the supply regulation at the load cannot
be maintained to the circuit requirements, it forces
the use of remote sensing, additional regulation at
the load, bigger or shorter cables, or a combination
of these. The SN65HVD08 eases this problem by
relaxing the supply requirements to allow for more
variation in the supply voltage over typical RS-485
transceivers.
not be ignored and decoupling capacitance at the
load is required. The amount depends upon the
magnitude and frequency of the load current change
but, if only powering the SN65HVD08, a 0.1 µF
ceramic capacitor is usually sufficient.
OPTO-ISOLATED DATA BUSES
Long RS-485 circuits can create large ground loops
and pick up common-mode noise voltages in excess
of the range tolerated by standard RS-485 circuits. A
common remedy is to provide galvanic isolation of
the data circuit from earth or local grounds.
SUPPLY SOURCE IMPEDANCE
Transformers, capacitors, or phototransistors most
often provide isolation of the bus and the local node.
Transformers and capacitors require changing
signals to transfer the information over the isolation
barrier and phototransistors (opto-isolators) can pass
steady-state signals. Each of these methods incurs
additional costs and complexity, the former in clock
encoding and decoding of the data stream and the
latter in requiring an isolated power supply.
In the steady state, the voltage drop from the source
to the load is simply the wire resistance times the
load current as modeled in Figure 15.
I
L
R
S
+
+
–
R
L
V
L
= V – 2R I
S L
S
V
S
Quite often, the cost of isolated power is repeated at
each node connected to the bus as shown in
Figure 16. The possibly lower-cost solution is to
generate this supply once within the system and then
distribute it along with the data line(s) as shown in
Figure 17.
R
S
–
Figure 15. Steady-State Circuit Model
For example, if you were to provide 5-V ±5% supply
power to a remote circuit with a maximum load
requirement of 0.1 A (one SN65HVD08), the voltage
at the load would fall below the 4.5-V minimum of
most 5-V circuits with as little as 5.8 m of 28-GA
conductors. Table 1 summarizes wire resistance and
the length for 4.5 V and 3 V at the load with 0.1 A of
load current. The maximum lengths would scale
linearly for higher or lower load currents.
DC-to-DC
Converter
Local Power
Source
Opto
Isolators
Rest of
Board
Table 1. Maximum Cable Lengths for Minimum
Load Voltages at 0.1 A Load
WIRE
SIZE
RESISTANCE 4.5 V LENGTH
AT 0.1 A
3-v LENGTH
AT 0.1 A
DC-to-DC
Converter
Local Power
Source
28 Gage
24 Gage
22 Gage
20 Gage
18 Gage
0.213 Ω/m
0.079 Ω/m
0.054 Ω/m
0.034 Ω/m
0.021 Ω/m
5.8 m
15.8 m
23.1 m
36.8 m
59.5 m
41.1 m
110.7 m
162.0 m
257.3 m
416.7 m
Rest of
Board
Opto
Isolators
Figure 16. Isolated Power at Each Node
Under dynamic load requirements, the distributed
inductance and capacitance of the power lines may
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The features of the SN65HVD08 are particularly
good for the application of Figure 17. Due to added
supply source impedance, the low quiescent current
requirements and wide supply voltage tolerance
allow for the poorer load regulation.
Local Power
Source
Opto
Isolators
Rest of
Board
AN OPTO ALTERNATIVE
The ISO150 is a two-channel, galvanically isolated
data coupler capable of data rates of 80 Mbps. Each
channel can be individually programmed to transmit
data in either direction.
SN65HVD08
Data is transmitted across the isolation barrier by
coupling complementary pulses through high-voltage
0.4-pF capacitors. Receiver circuitry restores the
pulses to standard logic levels. Differential signal
Local Power
Source
Opto
Isolators
Rest of
Board
transmission
rejects
isolation-mode
voltage
transients up to 1.6 kV/ms.
ISO150 avoids the problems commonly associated
with opto-couplers. Optically-isolated couplers
require high current pulses and allowance must be
made for LED aging. The ISO150's Bi-CMOS
circuitry operates at 25 mW per channel with supply
voltage range matching that of the SN65HVD08 of 3
V to 5.5 V.
Figure 17. Distribution of Isolated Power
Figure 18 shows a typical circuit.
–5 V
+5 V
SN65HVD08
A
B
D
Data
(I/O)
Bus
D
2A
G
A
ISO150
V
D
2B
R/T
R/T
2B
SB
DE
2A
Channel 1
RE
R
Side A
Side B
Channel 2
D
1A
R/T
V
G
A
R/T
D
1B
1A
SA
1B
DE/RE
+5 V
“1”
+5 V
Figure 18. Isolated RS-485 Interface
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
SN65HVD08D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD08DG4
SN65HVD08DR
SN65HVD08DRG4
SN65HVD08P
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
P
P
D
D
D
D
P
P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD08PE4
SN75HVD08D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75HVD08DG4
SN75HVD08DR
SN75HVD08DRG4
SN75HVD08P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD08PE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to
discontinue any product or service without notice. Customers should obtain the latest relevant information
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subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible
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Copyright © 2007, Texas Instruments Incorporated
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