SN65HVD1176_08 [TI]
PROFIBUS RS-485 TRANSCEIVERS; PROFIBUS RS - 485收发器
| 型号： | SN65HVD1176_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PROFIBUS RS-485 TRANSCEIVERS |
| 文件： | 总19页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D–JULY 2003–REVISED DECEMBER 2007
PROFIBUS RS-485 TRANSCEIVERS
1
FEATURES
APPLICATIONS
•
•
•
Process Automation
•
Optimized for PROFIBUS Networks
–
–
–
Chemical Production
Brewing and Distillation
Paper Mills
–
–
Signaling Rates Up to 40 Mbps
Differential Output Exceeds 2.1 V
(54 Ω Load)
Factory Automation
–
Low Bus Capacitance of 10 pF (Max)
–
–
–
Automobile Production
Rolling, Pressing, Stamping Machines
Networked Sensors
•
•
•
•
•
Meets the Requirements of TIA/EIA-485-A
ESD Protection Exceeds ±10 kV HBM
Failsafe Receiver for Bus Open, Short, Idle
Up to 160 Transceivers on a Bus
General RS-485 Networks
–
–
–
Motor/Motion Control
HVAC and Building Automation Networks
Networked Security Stations
Low Skew During Output Transitions and
Driver Enabling / Disabling
•
•
•
•
Common-Mode Rejection Up to 50 MHz
Short-Circuit Current Limit
Hot Swap Capable
Thermal Shutdown Protection
DESCRIPTION
These devices are half-duplex differential transceivers, with characteristics optimized for use in PROFIBUS (EN
50170) applications. The driver output differential voltage exceeds the Profibus requirements of 2.1 V with a 54 Ω
load. A signaling rate of up to 40 Mbps allows technology growth to high data transfer speeds. The low bus
capacitance provides low signal distortion.
The SN65HVD1176 and SN75HVD1176 meet or exceed the requirements of ANSI standard TIA/EIA-485-A
(RS-485) for differential data transmission across twisted-pair networks. The driver outputs and receiver inputs
are tied together to form a half-duplex bus port, with one-fifth unit load, allowing up to 160 nodes on a single bus.
The receiver output stays at logic high when the bus lines are shorted, left open, or when no driver is active. The
driver outputs are in high impedance when the supply voltage is below 2.5 V to prevent bus disturbance during
power cycling or during live insertion to the bus. An internal current limit protects the transceiver bus pins in
short-circuit fault conditions by limiting the output current to a constant value. Thermal shutdown circuitry protects
the device against damage due to excessive power dissipation caused by faulty loading and drive conditions.
The SN75HVD1176 is characterized for operation at temperatures from 0°C to 70°C. The SN65HVD1176 is
characterized for operation at temperatures from -40°C to 85°C.
LOGIC DIAGRAM (POSITIVE LOGIC)
D PACKAGE
(TOP VIEW)
A
B
D
R
RE
DE
D
VCC
B
1
2
3
4
8
7
6
5
DE
A
GND
RE
R
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D–JULY 2003–REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
TA
PACKAGED DEVICES(1)
PACKAGE MARKING(2)
VN1176
0C to 70C
-40°C to 85°C
SN75HVD1176D
SN65HVD1176D
VP1176
(1) The D package is available taped and reeled. Add an R suffix to the device type (for example, SN65HVD1176DR).
(2) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
SN65HVD1176
UNIT
SN75HVD1176
VCC
Supply voltage(2)
–0.5 to 7
–9 to 14
–40 to 40
–0.5 to 7
–10 to 10
4
V
V
Voltage at any bus I/O terminal
Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 15)
Voltage input at any D, DE or RE terminal
Receiver output current
V
V
IO
mA
kV
All pins
Human Body Model,
Electrostatic discharge
(HBM)(3)
Bus terminals and
GND
10
kV
TJ
Junction temperature
150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal..
(3) Tested in accordance with JEDEC standard 22. test method A114-A..
RECOMMENDED OPERATING CONDITIONS
MIN
4.75
–7
2
TYP MAX
UNIT
V
VCC
Supply voltage
5
5.25
12
Voltage at either bus I/O terminal
High-level input voltage
Low-level input voltage
Differential input voltage
A, B
V
VIH
VIL
VIL
VCC
0.8
12
V
D, DE, RE
0
V
A with respect to B
Driver
-12
-70
-8
V
70
mA
mA
Ω
IO
Output current
Receiver
8
SN65HVD1176
SN75HVD1176
-40
0
130
130
(1)
TJ
Junction temperature
Ω
RL
Differential load resistance
Signaling rate
54
Ω
1/tU1
40
Mbps
(1) See the Thermal Characteristics table for more information on maintenance of this requirement.
2
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SLLS563D–JULY 2003–REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
DRIVER
VO
Open-circuit output voltage
A or B,
No load
0
VCC
V
V
RL = 54 Ω
See Figure 1
2.1
2.9
2.7
Steady-state differential output voltage
magnitude
With common-mode loading,
(VTEST from -7 V to 12 V)
See Figure 2
|VOD(SS)
|
2.1
V
Change in steady-state differential output
voltage between logic states
Δ|VOD(SS)
VOC(SS)
ΔVOC(SS)
VOC(PP)
|
See Figure 1 and Figure 6
–0.2
2
0
2.5
0
0.2
3
V
Steady-state common-mode output voltage
V
V
Change in steady-state common-mode output
voltage
See Figure 5
–0.2
0.2
Peak-to-peak common-mode output voltage
0.5
V
Differential output voltage over and under
shoot
VOD(RING)
RL = 54 Ω, CL = 50 pF, See Figure 6
10%
50
VOD(PP)
µA
II
Input current
D, DE
-50
IO(OFF)
IOZ
Output current with power off
High impedance state output current
Peak short-circuit output current
VCC ≤ 2.5 V
See receiver line input
DE at 0 V
IOS(P)
VOS = –7 V to 12 V
-250
60
250
mA
mA
VOS > 4 V,
Output driving low
DE at VCC, See
Figure 8
90
135
-60
IOS(SS)
Steady-state short-circuit output current
Differential output capacitance
VOS < 1 V,
Output driving high
-135
-90
mA
pF
COD
See receiver CID
RECEIVER
Positive-going differential input voltage
threshold
VIT(+)
SeeFigure 9
VO = 2.4 V, IO = –8 mA
VO = 0.4 V, IO = 8 mA
–80
–20
mV
mV
Negative-going differential input voltage
threshold
VIT(–)
-200
-120
VHYS
VOH
VOL
Hysteresis voltage (VIT+ – VIT-
High-level output voltage
Low-level output voltage
)
40
4.6
0.2
mV
V
VID = 200 mV, IOH = –8 mA, See Figure 9
VID = –200 mV, IOL = 8 mA, See Figure 9
4
0.4
V
IA, IB
VCC = 4.75 V to 5.25 V
VI = - 7 V to 12 V,
Bus pin input current
–160
200
µA
IA(OFF)
IB(OFF)
Other input = 0 V
VCC = 0 V
II
Receiver enable input current
RE
–50
–1
50
1
µA
µA
kΩ
IOZ
RI
High-impedance - state output current
Input resistance
RE = VCC
60
Test input signal is a 1.5 MHz sine wave with
amplitude 1 Vpp, capacitance measured across A
and B
CID
Differential input capacitance
Common mode rejection
7
4
10
pF
V
CMR
See Figure 11
(1) All typical values are at VCC = 5 V and 25°C.
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SLLS563D–JULY 2003–REVISED DECEMBER 2007
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP( MAX UNIT
1)
DRIVER
tPLH
Propagation delay time low-level-to-high-level output
Propagation delay time high-level-to-low-level output
4
4
7
7
10
10
2
ns
ns
ns
ns
ns
ns
tPHL
RL = 54 Ω, CL = 50 pF,
See Figure 3
tsk(p)
Pulse skew | tPLH – tPHL
|
0
tr
Differential output rise time
Differential output fall time
Output transition skew
2
2
3
7.5
7.5
1
tf
3
tt(MLH), tt(MHL)
See Figure 4
0.2
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active
output
10
10
20
20
1.5
2.5
4
ns
ns
ns
ns
µs
ns
µs
µs
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-to- high-impedance
output
RE at 0 V
|tp(AZL) – tp(BZH)
|tp(AZH) – tp(BZL)
|
|
Enable skew time
Disable skew time
0.55
RL = 110 Ω,
CL = 50 pF
See Figure 7
|tp(ALZ) – tp(BHZ)
|tp(AHZ) – tp(BLZ)
|
|
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active
output (from sleep mode)
1
30
RE at 5 V
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-output-to
high-impedance (to sleep mode)
50
Time from application of short-circuit to current
foldback
t(CFB)
t(TSD)
See Figure 8
0.5
Time from application of short-circuit to thermal
shutdown
TA = 25°C, See Figure 8
100
RECEIVER
tPLH
tPHL
tsk(p)
tr
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
20
20
1
25
25
2
ns
ns
ns
ns
ns
Pulse skew | tPLH – tPHL
|
See Figure 10
Receiver output voltage rise time
Receiver output voltage fall time
2
4
tf
2
4
Propagation delay time, high-impedance-to-high-level
output
tPZH
tPHZ
tPZL
tPLZ
tPZH
tPHZ
tPZL
tPLZ
20
20
ns
ns
ns
ns
µs
ns
µs
ns
DE at VCC
See Figure 13
,
Propagation delay time, high-level-to-high-impedance
output
Propagation delay time, high-impedance-to-low-level
output
20
20
DE at VCC
,
See Figure 14
Propagation delay time, low-level-to-high-impedance
output
Propagation delay time, high-impedance-to-high-level
output (standby to active)
1
13
2
4
20
4
DE at 0 V,
See Figure 12
Propagation delay time, high-level-to-high-impedance
output (active to standby)
Propagation delay time, high-impedance-to-low-level
output (standby to active)
DE at 0 V,
See Figure 12
Propagation delay time, low-level-to-high-impedance
output (active to standby)
13
20
(1) All typical values are at VCC = 5 V and 25°C.
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SLLS563D–JULY 2003–REVISED DECEMBER 2007
Table 1. SUPPLY CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
mA
mA
µA
Driver and receiver, RE at 0 V, DE at VCC, All other inputs open, no load
Driver only, RE at VCC, DE at VCC, All other inputs open, no load
Receiver only, RE at 0 V, DE at 0 V, All other inputs open, no load
Standby only, RE at VCC, DE at 0 V, All other inputs open
4
6
6
6
5
3.8
3.6
0.2
Supply
ICC
Current(1)
(1) Over recommended operating conditions
THERMAL CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(2)
208.3
MAX UNIT
°C/W
Low-K board(4), no air flow
High-K board(5), no air flow
High-K board
θJA
Junction-to-ambient thermal resistance(3)
128.7
°C/W
θJB
θJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
77.6
°C/W
43.9
°C/W
RL = 54 Ω, CL = 50 pF, 0 V to 3 V,
15 MHz, 50% duty cycle square wave
input, driver and receiver enabled
PD
Device power dissipation
SN65HVD1176
277
318
64
mW
–40
0
°C
°C
°C
°C
°C
Low-K board, no air flow,
PD = 318 mW
SN75HVD1176
Ambient air temperature
TA
SN65HVD1176
–40
0
89
High-K board, no air flow,
PD = 318 mW
SN75HVD1176
TSD
Thermal shut down junction temperature
150
(1) See Application Information section for an explanation of these parameters.
(2) All typical values are with VCC = 5 V and TA = 25°C.
(3) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(4) JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(5) JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
PARAMETER MEASUREMENT INFORMATION
NOTE:
Test load capacitance includes probe and jig capacitance (unless otherwise
specified).
Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50%
duty cycle, Zo = 50 Ω (unless otherwise specified).
I
O
O
A
B
27 Ω
27 Ω
I
I
V
OD
50 pF
0 V or 3 V
D
I
V
OC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
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SLLS563D–JULY 2003–REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
375 Ω
A
B
V
= −7 V to 12 V
TEST
V
OD
60 Ω
375 Ω
0 V or 3 V
D
V
TEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3 V
0 V
INPUT
V
OD
R
L
= 54 Ω
C
L
= 50 pF
V
OD(H)
OD(L)
Signal
90%
10%
50 Ω
Generator
OUTPUT
V
t
r
t
f
Figure 3. Driver Switching Test Circuit and Rise/Fall Time Measurement
D
1.5 V
1.5 V
t
t
PLH
PHL
A,B
50%
50%
A
B
t
t
t(MLH)
t(MHL)
50%
50%
Figure 4. Driver Switching Waveforms for Propagation Delay and Output Midpoint Time Measurements
27 Ω
A
V
A
≈ 3.25 V
≈ 1.75 V
D
27 Ω
V
B
Signal
B
50 Ω
V
Generator
V
OC
∆V
OC(PP)
OC(SS)
50 pF
V
OC
Figure 5. Driver VOC Test Circuit and Waveforms
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SLLS563D–JULY 2003–REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
OD(SS)
V
OD(RING)
V
OD(PP)
0 V Differential
V
OD(RING)
V
OD(SS)
(1) VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the
VOD(H) and VOD(L) steady state values.
Figure 6. VOD(RING) Waveform and Definitions
3 V
DE
1.5 V
R
L
= 110 Ω
V
CC
t
t
p(ALZ)
p(AZL)
A
B
C
C
= 50 pF
L
D
A
50%
50%
0 V
V
+0.5 V
OL
DE
R
= 110 Ω
L
0 V
t
p(BHZ)
t
p(BZH)
Signal
50 Ω
= 50 pF
L
Generator
V
OL
−0.5 V
B
a) D at Logic Low
3 V
DE
1.5 V 1.5 V
R
L
= 110 Ω
0 V
t
t
p(AHZ)
p(AZH)
A
B
C
C
= 50 pF
L
D
V
−0.5 V
OH
A
B
50%
3 V
R
= 110 Ω
DE
L
t
V
CC
p(BLZ)
t
p(BZL)
Signal
50 Ω
= 50 pF
L
Generator
50%
V
OH
+0.5 V
b) D at Logic High
Figure 7. Driver Enable/Disable Test
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PARAMETER MEASUREMENT INFORMATION (continued)
250
Output
Current |mA|
I
OS
D
135
60
V
OS
Voltage
Source
time
t
(CFB)
t
(TSD)
Figure 8. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t = 0)
I
A
A
I
O
R
V
A
V
I
ID
B
V
B
V
IC
V
O
B
V
A
+ V
B
2
Figure 9. Receiver DC Parameter Definitions
Signal
50 Ω
Generator
Input B
V
ID
1.5 V
0 V
A
50%
I
O
Input A
t
R
B
t
PHL
PLH
V
O
C
L
= 15 pF
V
Signal
OH
90%
50 Ω
Output
Generator
1.5 V
10%
V
OL
t
r
t
f
Figure 10. Receiver Switching Test Circuit and Waveforms
50 Ω
A
100 nF
R
V = A sin 2 ft
I
470 nF
1 MHz < f < 50 MHz
RE
DE
50 Ω
B
2.2 kΩ
V
R
Scope
2.2 kΩ
D
V
=
offset
GND
V
CC
Scope
−2 V to 7 V
100 nF
V
R
shall be greater than
2 V throughout this test.
Figure 11. Receiver Common-Mode Rejection Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
3 V
A
B
A
1 kΩ ± 1%
= 15 pF ±20%
0 V or 1.5 V
1.5 V or 0 V
R
V
O
S1
B
C
L
RE
Input
V
I
Generator
50 Ω
3 V
1.5 V
V
I
0 V
V
t
PZH(2)
OH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
V
O
GND
t
PZL(2)
3 V
A at 0 V
B at 1.5 V
S1 to A
1.5 V
V
O
V
OL
Figure 12. Receiver Enable Time From Standby (Driver Disabled)
D
V
V
CC
DE
CC
A
54 Ω
B
3 V
0 V
1 kΩ
R
RE
1.5 V
0 V
C
L
= 15 pF
RE
t
t
PHZ
PZH
Signal
Generator
V
OH
50 Ω
V
OH
−0.5 V
1.5 V
R
GND
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output High (Driver Active)
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PARAMETER MEASUREMENT INFORMATION (continued)
Ω
1 kΩ
Ω
Figure 14. Receiver Enable Test Circuit and Waveforms, Data Output Low (Driver Active)
V
TEST
100 Ω
0 V
15 ms
Pulse Generator,
15 ms Duration,
1% Duty Cycle
1.5 ms
−V
TEST
Figure 15. Test Circuit and Waveforms, Transient Over-Voltage Test
DEVICE INFORMATION
Table 2. Driver Function Table(1)
INPUT
ENABLE
OUTPUTS
D
DE
A
H
L
B
L
H
H
L
X
H
L
H
Z
Z
L
Z
Z
H
X
OPEN
H
OPEN
(1) H = high level, L = low level, X = don’t care,
Z = high impedance (off)
Table 3. Receiver Function Table(1)
DIFFRENTIAL INPUT
VID = (VA – VB)
ENABLE
RE
OUTPUT
R
VID ≥ 0.02 V
L
H
(1) H = high level, L = low level, X = don’t care,
Z = high impedance (off), ? = indeterminate
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Table 3. Receiver Function Table (continued)
DIFFRENTIAL INPUT
VID = (VA – VB)
ENABLE
RE
OUTPUT
R
–0.2 V < VID < –0.02 V
L
?
L
VID ≤ –0.2 V
L
X
X
H
Z
Z
H
H
H
OPEN
Open Circuit
Short Circuit
L
L
L
Idle (terminated) bus
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
V
CC
V
CC
200 kΩ
500 Ω
500 Ω
9 V
Input
Input
200 kΩ
9 V
A Input
B Input
V
CC
V
CC
18 kΩ
16 V
18 kΩ
16 V
90 kΩ
90 kΩ
18 kΩ
Input
Input
18 kΩ
16 V
16 V
A and B Outputs
R Output
V
CC
V
CC
16 V
5 Ω
Output
9 V
Output
16 V
Copyright © 2003–2007, Texas Instruments Incorporated
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SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D–JULY 2003–REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
vs
LOAD CURRENT
DRIVER SUPPLY CURRENT
vs
SIGNALING RATE
5
66
64
V
CC
= 5 V
4.5
4
100 Ω
V
CC
= 5.25 V
3.5
3
62
50 Ω
V
CC
= 4.75 V
2.5
2
60
58
56
V
= 5 V
CC
1.5
T
A
= 25°C
= 56 Ω,
R
L
1
0.5
0
DE and RE at 5 V
Input 0 V to 3 V PRBS
See NO TAG
T
A
= 25 C
54
0
10
20
30
40
50
0
20
40
60
80
I
L
− Load Current − mA
Signaling Rate − Mbps
Figure 16.
Figure 17.
DRIVER OUTPUT TRANSITION SKEW
DRIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
4
0.35
0.3
R
C
= 54 Ω,
L
R
C
= 54 Ω,
L
= 50 pF
L
= 50 pF
L
3.75
3.5
See NO TAG
See NO TAG
V
CC
= 4.75 V
V
CC
= 4.75 V
0.25
0.2
V
CC
= 5 V
3.25
3
V
CC
= 5 V
V
CC
= 5.25 V
0.15
0.1
V
CC
= 5.25 V
2.75
2.5
0.05
0
2.25
2
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T
A
− Free-Air Temperature −°C
T
A
− Free-Air Temperature −°C
Figure 18.
Figure 19.
12
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Product Folder Link(s): SN65HVD1176 SN75HVD1176
SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D–JULY 2003–REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
DRIVER ENABLE SKEW
vs
FREE-AIR TEMPERATURE
0.7
0.6
0.5
0.4
0.3
0.2
V
= 4.75 V
CC
V
CC
= 5.25 V
V
CC
= 5 V
R
C
= 110 Ω,
= 50 pF
L
L
0.1
0
See NO TAG
−40
−15
10
35
60
85
T
A
− Free-Air Temperature −°C
Figure 20.
Copyright © 2003–2007, Texas Instruments Incorporated
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SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D–JULY 2003–REVISED DECEMBER 2007
APPLICATION INFORMATION
Thermal Characteristics of IC Packages
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
•
•
•
PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card. θJB provides an overall thermal resistance between the die
and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA’s with thermal balls) and can be
used for simple 1-dimensional network analysis of package system (see Figure 21).
Ambient Node
q
Calculated
CA
Surface Node
q
JC Calculated/Measured
Junction
q
Calculated/Measured
JB
PC Board
Figure 21. Thermal Resistance
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Product Folder Link(s): SN65HVD1176 SN75HVD1176
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2007
PACKAGING INFORMATION
Orderable Device
SN65HVD1176D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD1176DG4
SN65HVD1176DR
SN65HVD1176DRG4
SN75HVD1176D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75HVD1176DG4
SN75HVD1176DR
SN75HVD1176DRG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65HVD1176DR
SN75HVD1176DR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65HVD1176DR
SN75HVD1176DR
SOIC
SOIC
D
D
8
8
2500
2500
340.5
340.5
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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