SN65HVD12P [TI]
3.3V RS 485 TRANSCEIVERS; 3.3V RS-485收发器
| 型号： | SN65HVD12P |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V RS 485 TRANSCEIVERS |
| 文件： | 总20页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢍ ꢉꢊ ꢀꢁ ꢌꢃ ꢄꢅ ꢆ ꢇꢍ
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
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FEATURES
DESCRIPTION
The
SN65HVD10,
SN75HVD10,
SN65HVD11,
D
D
D
Operates With a 3.3-V Supply
SN75HVD11, SN65HVD12, and SN75HVD12 combine a
3-state differential line driver and differential input line
receiver that operate with a single 3.3-V power supply.
They are designed for balanced transmission lines and
meet or exceed ANSI standard TIA/EIA-485-A and ISO
8482:1993. These differential bus transceivers are
monolithic integrated circuits designed for bidirectional
data communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and active-low
enables respectively, that can be externally connected
together to function as direction control. Very low device
standby supply current can be achieved by disabling the
driver and the receiver.
Bus-Pin ESD Protection Exceeds 16 kV HBM
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
D
Optional Driver Output Transition Times for
†
Signaling Rates of 1 Mbps, 10 Mbps and
25 Mbps
D
D
Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
Bus-Pin Short Circuit Protection From –7 V to
12 V
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/ output
(I/O) bus port that is designed to offer minimum loading to
the bus whenever the driver is disabled or VCC = 0. These
parts feature wide positive and negative common-mode
voltage ranges, making them suitable for party-line
applications.
D
D
Low-Current Standby Mode . . . 1 µA Typical
Open-Circuit, Idle-Bus, and Shorted-Bus
Failsafe Receiver
D
D
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
D OR P PACKAGE
(TOP VIEW)
D
SN75176 Footprint
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
CC
APPLICATIONS
GND
D
D
D
D
D
D
D
Digital Motor Control
Utility Meters
LOGIC DIAGRAM
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Control
Building Automation
(POSITIVE LOGIC)
1
R
2
RE
3
4
DE
D
Point-of-Sale (POS) Terminals and Networks
6
7
A
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
ꢙꢑ ꢚ ꢆꢛ ꢖ ꢔꢘ ꢚꢁ ꢆ ꢕꢔꢕ ꢜꢝ ꢞꢟ ꢠ ꢡꢢ ꢣꢜꢟꢝ ꢜꢤ ꢥꢦ ꢠ ꢠ ꢧꢝꢣ ꢢꢤ ꢟꢞ ꢨꢦꢩ ꢪꢜꢥ ꢢꢣꢜ ꢟꢝ ꢫꢢ ꢣꢧꢏ ꢙꢠ ꢟꢫꢦ ꢥꢣꢤ
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ꢙꢠ ꢟ ꢫꢦꢥ ꢣ ꢜꢟ ꢝ ꢨꢠ ꢟ ꢥ ꢧ ꢤ ꢤ ꢜꢝ ꢰ ꢫꢟ ꢧ ꢤ ꢝꢟꢣ ꢝꢧ ꢥꢧ ꢤꢤ ꢢꢠ ꢜꢪ ꢯ ꢜꢝꢥ ꢪꢦꢫ ꢧ ꢣꢧ ꢤꢣꢜ ꢝꢰ ꢟꢞ ꢢꢪ ꢪ ꢨꢢ ꢠ ꢢꢡ ꢧꢣꢧ ꢠ ꢤꢏ
Copyright 2002−2003, Texas Instruments Incorporated
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
SIGNALING RATE
UNIT LOADS
T
A
SOIC MARKING
(1)
SOIC
PDIP
25 Mbps
10 Mbps
1 Mbps
1/2
1/8
1/8
1/2
1/8
1/8
1/2
1/8
SN65HVD10D
SN65HVD11D
SN65HVD12D
SN75HVD10D
SN75HVD11D
SN75HVD12D
SN65HVD10QD
SN65HVD11QD
SN65HVD10P
SN65HVD11P
SN65HVD12P
SN75HVD10P
SN75HVD11P
SN75HVD12P
VP10
VP11
−40°C to 85°C
VP12
VN10
VN11
25 Mbps
10 Mbps
1 Mbps
−0°C to 70°C
VN12
VP10Q
VP11Q
25 Mbps
10 Mbps
SN65HVD10QP
SN65HVD11QP
−40°C to 125°C
(1)
The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN75HVD11DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1) (2)
SN65HVD10, SN75HVD10
SN65HVD11, SN75HVD11
SN65HVD12, SN75HVD12
Supply voltage range, V
Voltage range at A or B
−0.3 V to 6 V
−9 V to 14 V
CC
Input voltage range at D, DE, R or RE
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 11)
−0.5 V to V + 0.5 V
CC
−50 V to 50 V
A, B and GND
All pins
16 kV
(3)
Human body model
4 kV
Electrostatic discharge
(4)
Charged-device model
All pins Charge
1 kV
See Dissipation Rating Table
170°C
Continuous total power dissipation
Junction temperature, T
J
Storage temperature range, T
stg
−65°C to 150°C
260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(2)
(3)
(4)
Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE DISSIPATION RATINGS
(1)
DERATING FACTOR
T
≤ 25°C
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING POWER RATING
A
(2)
D
597 mW
4.97 mW/°C
8.26 mW/°C
10.75 mW/°C
373 mW
620 mW
806 mW
298 mW
496 mW
645 mW
100 mW
165 mW
215 mW
(3)
D
990 mW
P
1290 mW
(1)
(2)
(3)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51−3.
Tested in accordance with the High-K thermal metric definitions of EIA/JESD51−7.
2
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, V
CC
3
3.6
12
V
V
V
V
V
(1)
−7
Voltage at any bus terminal (separately or common mode) V or V
IC
I
High-level input voltage, V
IH
D, DE, RE
D, DE, RE
2
0
V
CC
0.8
Low-level input voltage, V
IL
Differential input voltage, V (see Figure 7)
ID
−12
−60
−8
12
Driver
High-level output current, I
mA
mA
OH
Receiver
Driver
60
8
Low-level output current, I
OL
Receiver
Differential load resistance, R
54
60
50
Ω
L
Differential load capacitance, C
pF
L
HVD10
HVD11
HVD12
25
10
1
Signaling rate
Mbps
(2)
Junction temperature, T
145
°C
J
(1)
(2)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
See thermal characteristics table for information regarding this specification.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
V
IK
Input clamp voltage
I = −18 mA
−1.5
2
V
I
I
O
= 0
V
CC
(2)
R
= 54 Ω, See Figure 1
1.5
1.5
|V
|
Differential output voltage
V
L
OD
V
test
= −7 V to 12 V, See Figure 2
Change in magnitude of differential output
voltage
∆|V
|
See Figure 1 and Figure 2
−0.2
0.2
2.5
V
OD
V
V
Peak-to-peak common-mode output voltage
Steady-state common-mode output voltage
400
mV
V
OC(PP)
OC(SS)
1.4
See Figure 3
Change in steady-state common-mode output
voltage
∆V
OC(SS)
−0.05
0.05
V
I
I
I
High-impedance output current
See receiver input currents
OZ
D
−100
0
0
100
250
Input current
DE
µA
I
Short-circuit output current
−7 V ≤ V ≤ 12 V
−250
mA
pF
OS
O
C
Differential output capacitance
V
OD
= 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
16
9
(OD)
RE at V
,
CC
D & DE at
No load
Receiver disabled and
driver enabled
15.5
5
mA
V
CC,
RE at V
,
CC
Receiver disabled and
driver disabled (standby)
D at V
,
CC
1
9
µA
I
Supply current
CC
DE at 0 V,
No load
RE at 0 V,
D & DE at
Receiver enabled and
driver enabled
15.5
mA
V , No load
CC
(1)
(2)
All typical values are at 25°C and with a 3.3-V supply.
For T > 85°C, V is 5%.
A
CC
3
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
MAX
16
UNIT
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
5
18
135
5
8.5
25
40
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
r
200
8.5
25
300
16
18
135
3
40
200
4.5
20
300
10
R
= 54 Ω, C = 50 pF,
L
See Figure 4
L
10
100
3
30
170
4.5
20
300
10
10
100
30
Differential output signal fall time
f
170
300
1.5
2.5
7
Pulse skew (|t |)
− t
sk(p)
sk(pp)
PZH
PHZ
PZL
PLZ
PHL PLH
6
(2)
11
Part-to-part skew
100
31
Propagation delay time,
high-impedance-to-high-level output
55
300
25
R
L
= 110 Ω, RE at 0 V,
See Figure 5
Propagation delay time,
high-level-to-high-impedance output
55
300
26
Propagation delay time,
high-impedance-to-low-level output
55
300
26
R
L
= 110 Ω, RE at 0 V,
See Figure 6
Propagation delay time,
low-level-to-high-impedance output
75
400
R
= 110 Ω, RE at 3 V,
L
t
t
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
6
6
µs
µs
PZH
See Figure 5
R
L
= 110 Ω, RE at 3 V,
PZL
See Figure 6
(1)
(2)
All typical values are at 25°C and with a 3.3-V supply.
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
t
sk(pp)
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
V
V
Positive-going input threshold voltage
I
I
= −8 mA
= 8 mA
−0.01
IT+
O
V
Negative-going input threshold
voltage
−0.2
IT−
O
V
V
V
V
Hysteresis voltage (V
IT+
− V
)
35
mV
V
hys
IT−
Enable-input clamp voltage
High-level output voltage
Low-level output voltage
I = −18 mA
−1.5
2.4
IK
I
V
ID
V
ID
V
O
= 200 mV,
I
I
= −8 mA,
= 8 mA,
See Figure 7
See Figure 7
V
OH
OL
OH
= −200 mV,
0.4
1
V
OL
I
High-impedance-state output current
= 0 or V
CC
RE at V
CC
−1
µA
OZ
V
or V = 12 V
0.05
0.06
0.11
0.13
A
B
V
A
or V = 12 V,
V
V
V
V
= 0 V
= 0 V
= 0 V
= 0 V
B
CC
CC
CC
CC
HVD11, HVD12,
Other input at 0 V
mA
mA
V
A
or V = −7 V
−0.1
−0.05
−0.04
0.2
B
V
A
or V = −7 V,
−0.05
B
I
I
Bus input current
V
A
or V = 12 V
0.5
0.5
B
V
A
or V = 12 V,
0.25
B
HVD10,
Other input at 0 V
V
A
or V = −7 V
−0.4
−0.4
−30
−30
−0.2
−0.15
B
V
A
or V = −7 V,
B
I
I
High-level input current, RE
Low-level input current, RE
Differential input capacitance
V
V
V
= 2 V
0
0
µA
µA
pF
IH
IH
= 0.8 V
IL
IL
C
= 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
15
4
ID
ID
RE at 0 V,
D & DE at 0 V,
No load
Receiver enabled and driver
disabled
8
5
mA
RE at V
D at V
DE at 0 V,
No load
,
CC
CC
Receiver disabled and driver
disabled (standby)
,
1
9
µA
I
Supply current
CC
RE at 0 V,
D & DE at V
No load
Receiver enabled and driver
enabled
,
15.5
mA
CC
(1)
All typical values are at 25°C and with a 3.3-V supply.
5
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
25
UNIT
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
HVD10
HVD10
12.5
20
20
PLH
ns
ns
ns
12.5
25
PHL
HVD11
HVD12
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
30
30
55
55
70
70
PLH
PHL
V
C
= −1.5 V to 1.5 V,
= 15 pF, See Figure 8
ID
L
HVD11
HVD12
t
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
1.5
4
t
Pulse skew (|t
− t
|)
ns
sk(p)
PHL PLH
4
8
(2)
15
15
5
t
Part-to-part skew
ns
ns
sk(pp)
t
t
t
t
t
t
t
t
Output signal rise time
Output signal fall time
1
1
2
2
r
C
C
= 15 pF, See Figure 8
= 15 pF, DE at 3 V,
L
5
f
(1)
PZH
Output enable time to high level
Output enable time to low level
Output disable time from high level
Output disable time from low level
15
15
20
15
6
(1)
PZL
PHZ
PLZ
PZH
L
ns
See Figure 9
(2)
(2)
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
C
L
= 15 pF, DE at 0,
µs
See Figure 10
6
PZL
(1)
(2)
All typical values are at 25°C and with a 3.3-V supply.
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
t
sk(pp)
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
(3)
MIN
TYP
121
93
MAX UNITS
High−K board , No airflow
(4)
D pkg
P pkg
D pkg
P pkg
D pkg
P pkg
(2)
θ
JA
θ
JB
θ
JC
Junction−to−ambient thermal resistance
Junction−to−board thermal resistance
Junction−to−case thermal resistance
°C/W
No airflow
High−K board
See Note (4)
67
°C/W
°C/W
57
41
°C/W
55
HVD10
(25 Mbps)
198
141
133
233
176
161
mW
mW
mW
R = 60Ω, C = 50 pF,
L
L
HVD11
(10 Mbps)
DE at V
RE at 0 V,
CC
P
D
Device power dissipation
Input to D a 50% duty cycle square
wave at indicated signaling rate
HVD12
(500 kbps)
High−K board, No airflow
D pkg
P pkg
−40
−40
116
123
T
Ambient air temperature
°C
°C
A
(4)
No airflow
T
JSD
Thermal shutdown junction temperature
165
(1)
(2)
See Application Information section for an explanation of these parameters.
The intent of θ specification is solely for a thermal performance comparison of one package to another in a standardized environment. This
JA
methodology is not meant to and will not predict the performance of a package in an application-specific environment.
JSD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
(3)
(4)
6
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
375 Ω 1%
V
CC
V
CC
I
I
DE
OA
I
I
DE
A
B
A
B
V
OD
D
54 Ω 1%
0 or 3 V
V
OD
60 Ω 1%
0 or 3 V
+
OB
−7 V < V
(test)
< 12 V
_
V
I
375 Ω 1%
V
V
OB OA
Figure 1. Driver V
and Voltage and Current Definitions
Test Circuit
Figure 2. Driver V
With Common-Mode
OD
OD
Loading Test Circuit
V
A
B
A
V
CC
27 Ω 1%
27 Ω 1%
V
B
DE
A
B
D
V
OC(PP)
∆V
OC(SS)
Input
V
OC
V
C
L
= 50 pF 20%
OC
C
Includes Fixture and
L
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t <6ns, t <6ns, Z = 50 Ω
r
f
O
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3 V
V
CC
1.5 V
1.5 V
V
t
I
DE
C
C
= 50 pF 20%
L
A
B
V
D
OD
t
Includes Fixture
and Instrumentation
Capacitance
PLH
PHL
L
≈ 2 V
Input
Generator
R
L
= 54 Ω
90%
90%
V
I
50 Ω
0 V
10%
0 V
10%
1%
V
OD
≈ −2 V
t
r
t
f
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
3 V
0 V
A
S1
D
V
O
V
1.5 V
1.5 V
I
3 V
B
C
DE
0.5 V
R
= 110 Ω
1%
= 50 pF 20%
t
L
L
PZH
Input
Generator
V
OH
V
I
C
L
Includes Fixture
and Instrumentation
Capacitance
50 Ω
V
O
2.3 V
≈ 0 V
t
PHZ
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
7
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ꢇꢇ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇ ꢋꢉ ꢊ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇꢇ
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
3 V
R
L
= 110 Ω
1%
≈ 3 V
A
V
I
1.5 V
1.5 V
S1
D
V
O
3 V
0 V
B
t
t
PZL
PLZ
DE
≈ 3 V
C
= 50 pF 20%
Input
Generator
L
V
I
50 Ω
0.5 V
C
L
Includes Fixture
and Instrumentation
Capacitance
V
O
2.3 V
V
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
I
A
A
B
I
O
R
V
A
V
I
ID
V
B
V
IC
V
O
V
A
+ V
2
B
B
Figure 7. Receiver Voltage and Current Definitions
A
V
O
R
Input
Generator
V
I
50 Ω
B
1.5 V
0 V
C
C
= 15 pF 20%
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
1.5 V
V
I
0 V
t
t
PLH
PHL
V
V
OH
90% 90%
V
O
1.5 V
10%
1.5 V
10%
OL
t
r
t
f
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
3 V
DE
3 V
A
B
A
1 kΩ 1%
R
V
O
D
S1
0 V or 3 V
C
C
= 15 pF 20%
L
RE
B
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
V
I
1.5 V
1.5 V
PHZ
0 V
V
t
t
PZH(1)
OH
D at 3 V
S1 to B
V
OH
−0.5 V
1.5 V
V
O
≈ 0 V
t
t
PLZ
PZL(1)
≈ 3 V
D at 0 V
S1 to A
1.5 V
V
O
V
OL
+0.5 V
V
OL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
9
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
3 V
A
A
1 kΩ 1%
= 15 pF 20%
0 V or 1.5 V
R
V
O
S1
B
B
1.5 V or 0 V
C
C
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
V
I
0 V
V
t
PZH(2)
OH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
V
O
GND
t
PZL(2)
3 V
A at 0 V
B at 1.5 V
S1 to A
1.5 V
V
O
V
OL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
RE
A
R
B
100 Ω
1%
Pulse Generator,
D
15 µs Duration,
1% Duty Cycle
+
_
t , t ≤ 100 ns
r
f
DE
3 V or 0 V
:
NOTE This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 11. Test Circuit, Transient Over Voltage Test
10
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
Function Tables
DRIVER
INPUT
D
ENABLE
DE
OUTPUTS
A
B
H
L
X
H
H
L
H
L
Z
H
L
H
Z
L
Open
H
RECEIVER
DIFFERENTIAL INPUTS
= V − V
ENABLE
RE
OUTPUT
R
V
ID
A
B
V
≤ −0.2 V
ID
L
L
L
H
L
L
L
?
H
Z
H
H
ID
−0.2 V < V < −0.01 V
−0.01 V ≤ V
ID
X
Open Circuit
Short Circuit
H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
11
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
V
CC
V
CC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
16 V
100 kΩ
16 V
R1
R1
R3
R2
R3
Input
Input
100 kΩ
16 V
R2
16 V
A and B Outputs
R Output
V
CC
V
CC
16 V
5 Ω
Output
9 V
Output
16 V
R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
SN65HVD10
SN65HVD11
SN65HVD12
12
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS
HVD11
RMS SUPPLY CURRENT
vs
HVD10 OR HVD12
RMS SUPPLY CURRENT
vs
SIGNALING RATE
SIGNALING RATE
70
70
T
= 25°C
R
L
C
L
= 54 Ω
= 50 pF
A
T
= 25°C
R
L
C
L
= 54 Ω
= 50 pF
A
V
CC
= 3.6 V
RE at V
DE at V
CC
CC
RE at V
DE at V
CC
CC
V
CC
= 3.6 V
60
50
60
50
V
CC
= 3 V
V
CC
= 3 V
V
CC
= 3.3 V
V
= 3.3 V
40
30
40
30
CC
0
2.5
5
7.5
10
0
5
10
15
20
25
30
35
40
Signaling Rate − Mbps
Signaling Rate − Mbps
Figure 12
Figure 13
HVD12
HVD10
RMS SUPPLY CURRENT
vs
BUS INPUT CURRENT
vs
SIGNALING RATE
BUS INPUT VOLTAGE
70
60
50
300
250
200
T
= 25°C
R
L
C
L
= 54 Ω
= 50 pF
A
T
= 25°C
A
RE at V
DE at V
CC
CC
DE at 0 V
V
CC
= 3.6 V
V
CC
= 0 V
150
100
50
V
CC
= 3.3 V
V
CC
= 3 V
V
CC
= 3.3 V
0
−50
40
30
−100
−150
−200
100
400
700
1000
−7−6−5 −4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
Signaling Rate − kbps
V − Bus Input Voltage − V
I
Figure 14
Figure 15
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
HVD11 OR HVD12
BUS INPUT CURRENT
vs
HIGH-LEVEL OUTPUT CURRENT
vs
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
BUS INPUT VOLTAGE
150
100
50
90
T
= 25°C
A
T
= 25°C
80
70
60
50
40
A
DE at V
D at V
CC
V
CC
DE at 0 V
= 3.3 V
CC
V
CC
= 0 V
30
20
0
10
0
−50
−100
−150
−200
V
CC
= 3.3 V
−10
−20
−30
−40
−50
−60
−4
−2
0
2
4
6
−7−6−5−4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
V
OH
− Driver High-Level Output Voltage − V
V − Bus Input Voltage − V
I
Figure 16
Figure 17
DRIVER DIFFERENTIAL OUTPUT
vs
LOW-LEVEL OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
200
180
160
140
120
100
2.5
T
= 25°C
V
= 3.3 V
A
CC
2.4
2.3
DE at V
DE at V
D at V
CC
CC
CC
D at 0 V
= 3.3 V
V
CC
2.2
2.1
2.0
1.9
1.8
1.7
1.6
80
60
40
20
0
−20
1.5
−40
−15
T
10
35
60
85
−4
−2
0
2
4
6
8
− Free-Air Temperature − °C
V
− Driver Low-Level Output Voltage − V
A
OL
Figure 19
Figure 18
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
TYPICAL CHARACTERISTICS
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
−40
−35
−30
−25
−20
−15
−10
T
= 25°C
A
DE at V
D at V
CC
R
CC
= 54 Ω
L
−5
0
0
0.50
1
1.50
2
2.50
3
3.50
V
CC
− Supply Voltage − V
Figure 20
15
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ꢇꢇ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢇ ꢋꢉ ꢊ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇꢇ
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SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
R
T
R
T
Stub
Device
HVD10
HVD11
HVD12
Number of Devices on Bus
64
256
256
:
NOTE The line should be terminated at both ends with its characteristic impedance (R = Z ). Stub lengths off the main line
T
O
should be kept as short as possible.
Figure 21. Typical Application Circuit
Driver Input
Driver Output
Receiver Input
Receiver Output
Figure 22. HVD12 Input and Output Through 2000 Feet of Cable
An example application for the HVD12 is illustrated in
bus is terminated at each end by a 100-Ω resistor,
matching the cable characteristic impedance. Figure 22
illustrates operation at a signaling rate of 250 kbps.
Figure 21. Two HVD12 transceivers are used to
communicate data through a 2000 foot (600 m) length of
Commscope 5524 category 5e+ twisted pair cable. The
16
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢁ
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇꢇ ꢉꢊ ꢀꢁ ꢂ ꢃ ꢄꢅꢆꢇꢇ ꢋ ꢉꢊ ꢀꢁ ꢌꢃ ꢄꢅ ꢆ ꢇꢇ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ ꢋ ꢉ ꢀ ꢁ ꢌꢃ ꢄꢅ ꢆꢇ ꢈ
www.ti.com
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢍ ꢉꢊ ꢀꢁꢌ ꢃꢄ ꢅꢆ ꢇ ꢍ
SLLS505F − FEBRUARY 2002 − REVISED NOVEMBER 2003
q
(Junction-to-Case Thermal Resistance) is defined
THERMAL CHARACTERISTICS OF IC
PACKAGES
JC
as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted
package up against a copper block cold plate to force heat
to flow from die, through the mold compound into the
copper block.
q
(Junction-to-Ambient Thermal Resistance) is
JA
defined as the difference in junction temperature to
ambient temperature divided by the operating power.
θ
is not a constant and is a strong function of:
the PCB design (50% variation)
JA
D
D
D
θ
θ
is a useful thermal characteristic when a heatsink is
JC
applied to package. It is not a useful characteristic to
predict junction temperature because it provides
pessimistic numbers if the case temperature is measured
in a nonstandard system and junction temperatures are
altitude (20% variation)
device power (5% variation)
can be used to compare the thermal performance of
JA
backed out. It can be used with θ in 1-dimensional
JB
packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB
construction, test chamber volume, sensor locations, and
thermal simulation of a package system.
q
(Junction-to-Board Thermal Resistance) is defined
the thermal characteristics of holding fixtures. θ is often
misused when it is used to calculate junction temperatures
for other installations.
JB
JA
as the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the
die) when the PCB is clamped in a cold-plate structure. θ
JB
TI uses two test PCBs as defined by JEDEC
specifications. The low-k board gives average in-use
condition thermal performance, and it consists of a single
copper trace layer 25 mm long and 2-oz thick. The high-k
board gives best case in-use condition, and it consists of
two 1-oz buried power planes with a single copper trace
layer 25 mm long and 2-oz thick. A 4% to 50% difference
is only defined for the high-k test card.
θ
provides an overall thermal resistance between the die
JB
and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and
can be used for simple 1-dimensional network analysis of
package system (see Figure 23).
in θ can be measured between these two test cards
JA
Figure 23. Thermal Resistance
17
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Digital Control
Military
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Logic
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logic.ti.com
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