SN65HVD1782QDRQ1 [TI]
具有故障保护功能和 3.3V 至 5V 工作电压的汽车类 RS-485 收发器 | D | 8 | -40 to 125;
| 型号： | SN65HVD1782QDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有故障保护功能和 3.3V 至 5V 工作电压的汽车类 RS-485 收发器 | D | 8 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总29页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1
SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
SN65HVD178x-Q1 Fault-Protected RS-485 Transceivers With 3.3-V to 5-V Operation
1 Features
3 Description
These devices are designed to survive overvoltage
faults such as direct shorts to power supplies, mis-
wiring faults, connector failures, cable crushes, and
tool mis-applications. They are also robust to ESD
events, with high levels of protection to the human-
body-model specification.
1
•
Qualified for Automotive Applications
•
AEC-Q100 Qualified With the Following Results
–
Device Temperature Grade 1:
–40°C to 125°C Ambient Operating
Temperature Range
–
–
Device HBM ESD Classification Level H2
Device CDM ESG Classification Level C3B
These devices combine a differential driver and a
differential receiver, which operate from a single
power supply. In the 'HVD1782, the driver differential
outputs and the receiver differential inputs are
connected internally to form a bus port suitable for
half-duplex (two-wire bus) communication. This port
features a wide common-mode voltage range, making
the devices suitable for multipoint applications over
long cable runs. These devices are characterized
from –40°C to 125°C. These devices are pin-
compatible with the industry-standard SN75176
transceiver, making them drop-in upgrades in most
systems.
•
Bus-Pin Fault Protection to:
–
–
> ±70 V ('HVD1780-Q1, 'HVD1781-Q1)
> ±30 V ('HVD1782-Q1)
•
•
•
•
Operation With 3.3-V to 5-V Supply Range
±16-kV HBM Protection on Bus Pins
Reduced Unit Load for up to 320 Nodes
Failsafe Receiver for Open-Circuit, Short-Circuit
and Idle-Bus Conditions
•
Low Power Consumption
These devices are fully compliant with ANSI TIA/EIA
485-A with a 5-V supply and can operate with a 3.3-V
supply with reduced driver output voltage for low-
power applications. For applications where operation
is required over an extended common-mode voltage
range, see the SN65HVD1785 (SLLS872) data sheet.
–
–
Low Standby Supply Current, 1 μA Maximum
ICC 4-mA Quiescent During Operation
•
•
Pin-Compatible With Industry-Standard SN75176
Signaling Rates of 115 kbps, 1 Mbps, and up to
10 Mbps
(1)
Device Information
2 Applications
NUMBER OF
PART NUMBER
SIGNALING RATE
Automotive Data Links
NODES
SN65HVD1780-Q1 Up to 115 kbps
SN65HVD1781-Q1 Up to 1 Mbps
SN65HVD1782-Q1 Up to 10 Mbps
Up to 320
Up to 320
Up to 64
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VFAULT up to 70 V
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1
SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
www.ti.com
Table of Contents
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ..................................... 3
6.2 ESD Ratings—AEC................................................... 4
6.3 ESD Ratings—IEC.................................................... 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Power Dissipation Ratings ........................................ 6
6.8 Switching Characteristics.......................................... 7
6.9 Package Dissipation Ratings .................................... 7
6.10 Typical Characteristics............................................ 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1 Device Support...................................................... 21
12.2 Documentation Support ........................................ 21
12.3 Receiving Notification of Documentation Updates 21
12.4 Community Resources.......................................... 21
12.5 Trademarks........................................................... 21
12.6 Electrostatic Discharge Caution............................ 21
12.7 Glossary................................................................ 21
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2016) to Revision D
Page
•
•
•
•
Changed the differential input to receive a valid bus high from VID < VIT+ to VID > VIT+ in the Receiver Function Table..... 15
Changed the Half-Duplex Layout Example .......................................................................................................................... 20
Added the Receiving Notification of Documentation Updates section ................................................................................. 21
Changed the Electrostatic Discharge Caution statement..................................................................................................... 21
Changes from Revision B (January 2016) to Revision C
Page
•
Changed the signaling rate for SN65HVD1780-Q1 from 115 to 0.115 Bin the Recommended Operating Conditions
table ....................................................................................................................................................................................... 4
Changes from Revision A (August 2015) to Revision B
Page
•
•
Changed HBM and CDM back to the AEC specification and split the IEC specification into a separate table .................... 4
Added the SN65HVD1780-Q1 and SN65HVD1782-Q1 devices to the Thermal Information table ....................................... 4
Changes from Original (September 2010) to Revision A
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added new ListItem in Features, second one with sub list items........................................................................................... 1
2
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Product Folder Links: SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1
SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1
www.ti.com
SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
V
ꢀ
CC
B
A
GND
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
6
A
Bus I/O
Bus I/O
Driver output or receiver input (complementary to B)
Driver output or receiver input (complementary to A)
B
7
D
4
Digital input Driver data input
DE
3
Digital input Driver enable, active high
Reference
GND
5
Local device ground
potential
R
1
2
8
Digital output Receive data output
RE
VCC
Digital input Receiver enable, active low
Supply
3.15-V-to-5.5-V supply
6 Specifications
6.1 Absolute Maximum Ratings
(1)
See Note
.
MIN
MAX
UNIT
VCC Supply voltage
Voltage range at bus pins
Input voltage range at any logic pin
–0.5
7
V
'HVD1780-Q1, 'HVD1781-
Q1
A, B pins
A, B pins
–70
70
V
'HVD1782-Q1
–70
–0.3
–70
–24
30
VCC + 0.3
70
V
V
Transient overvoltage pulse through 100 Ω per TIA-485
Receiver output current
24
mA
Continuous total power dissipation
Junction temperature
See Power Dissipation Ratings
TJ
170
°C
°C
Tstg
Storage temperature
–40
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2010–2017, Texas Instruments Incorporated
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SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
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6.2 ESD Ratings—AEC
VALUE
UNIT
Bus terminals and GND
All pins
±16000
±4000
±2000
±400
Human-body model (HBM), per AEC Q100-002(1)
Electrostatic
V(ESD)
V
discharge
Charged-device model (CDM), per AEC Q100-011
Machine Model (MM), AEC-Q100-003
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC
VALUE
UNIT
Electrostatic
discharge
V(ESD)
Human body model (HBM), per IEC 60749-26
Bus terminals and GND
±16000
V
6.4 Recommended Operating Conditions
MIN
3.15
–7
NOM
MAX
5.5
12
UNIT
VCC
VI
Supply voltage
5
V
V
Input voltage at any bus terminal (separately or common mode)(1)
High-level input voltage (driver, driver enable, and receiver enable inputs)
Low-level input voltage (driver, driver enable, and receiver enable inputs)
Differential input voltage
VIH
VIL
VID
2
VCC
0.8
12
V
0
V
–12
–60
–8
V
Output current, driver
60
mA
mA
Ω
IO
Output current, receiver
8
RL
CL
Differential load resistance
54
60
50
Differential load capacitance
pF
SN65HVD1780-Q1
0.115
1
1/tUI
Signaling rate
SN65HVD1781-Q1
SN65HVD1782-Q1
5-V supply
Mbps
10
–40
–40
–40
105
125
150
Operating free-air temperature (See the
Thermal Information table)
TA
TJ
°C
°C
3.3-V supply
Junction Temperature
(1) By convention, the least positive (most negative) limit is designated as minimum in this data sheet.
6.5 Thermal Information
SN65HVD1780-Q1
SN65HVD1781-Q1
SN65HVD1782-Q1
THERMAL METRIC(1)
UNIT
D (SOIC)
8 PINS
138
JEDEC high-K model
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance
JEDIC low-K model
242
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
61
62
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.8
ψJB
38.6
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
6.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
RL = 60 Ω, 4.75 V ≤ VCC 375 Ω
TA < 85°C
1.5
on each output to –7 V to 12 V,
SeeFigure 6
TA < 125°C
1.4
TA < 85°C
1.7
1.5
2
RL = 54 Ω,
4.75 V ≤ VCC ≤ 5.25 V
TA < 125°C
|VOD
|
Driver differential output voltage magnitude
V
RL = 54 Ω,
3.15 V ≤ VCC ≤ 3.45 V
0.8
1
TA < 85°C
2.2
2
2.5
RL = 100 Ω,
4.75 V ≤ VCC ≤ 5.25 V
TA < 125°C
Change in magnitude of driver differential
output voltage
Δ|VOD
|
RL = 54 Ω
–50
1
0
VCC/2
0
50
3
mV
V
VOC(SS)
Steady-state common-mode output voltage
Change in differential driver output common-
mode voltage
ΔVOC
–50
50
mV
Peak-to-peak driver common-mode output
voltage
Center of two 27-Ω load resistors,
See Figure 7
VOC(PP)
COD
500
23
mV
pF
Differential output capacitance
Positive-going receiver differential input
voltage threshold
VIT+
–100
–35
mV
Negative-going receiver differential input
voltage threshold
VIT–
–180
30
–150
50
mV
mV
Receiver differential input voltage threshold
hysteresis
(VIT+ – VIT–
VHYS
(1)
)
VCC
– 0.3
VOH
Receiver high-level output voltage
Receiver low-level output voltage
IOH = –8 mA
2.4
V
V
TA < 85°C
0.2
0.4
0.5
VOL
IOL = 8 mA
TA < 125°C
Driver input, driver enable, and receiver
enable input current
II(LOGIC)
–50
50
μA
IOZ
IOS
Receiver output high-impedance current
Driver short-circuit output current
VO = 0 V or VCC, RE at VCC
–1
1
μA
–200
200
mA
HVD1780-Q1,
HVD1781-Q1
75
400
–40
-300
4
100
500
VI = 12 V
VI = –7 V
HVD1782-Q1
VCC = 3.15 to 5.5 V or
VCC = 0 V, DE at 0 V
II(BUS)
Bus input current (disabled driver)
μA
HVD1780-Q1,
HVD1781-Q1
–60
HVD1782-Q1
-400
DE = VCC, RE = GND,
no load
Driver and receiver enabled
6
5
4
Driver enabled, receiver
disabled
DE = VCC, RE = VCC
,
3
2
mA
no load
Driver disabled, receiver
enabled
DE = GND, RE = GND,
no load
ICC
Supply current (quiescent)
DE = GND, D = open,
RE = VCC, no load, TA
85°C
<
0.15
1
Driver and receiver disabled,
standby mode
μA
DE = GND, D = open,
RE = VCC, no load, TA
125°C
<
12
Supply current (dynamic)
See the Typical Characteristics section
(1) Ensured by design. Not production tested.
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SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
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UNIT
6.7 Power Dissipation Ratings
PARAMETER
TEST CONDITIONS
VCC = 3.6 V, TJ = 150°C, RL = 300 Ω,
VALUE
CL = 50 pF (driver), CL = 15 pF (receiver)
75
3.3-V supply, unterminated(1)
VCC = 3.6 V, TJ = 150°C, RL = 100 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
3.3-V supply, RS-422 load(1)
95
VCC = 3.6 V, TJ = 150°C, RL = 54 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
3.3-V supply, RS-485 load(1)
115
290
320
PD
Power dissipation
mW
VCC = 5.5 V, TJ = 150°C, RL = 300 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, unterminated(1)
VCC = 5.5 V, TJ = 150°C, RL = 100 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, RS-422 load(1)
VCC = 5.5 V, TJ = 150°C, RL = 54 Ω,
CL = 50 pF (driver), CL = 15 pF (receiver)
5-V supply, RS-485 load(1)
400
170
TSD Thermal-shutdown junction temperature
°C
(1) Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: 1 Mbps.
6
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SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
6.8 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
DRIVER (SN65HVD1780)
RL = 54 Ω,
TEST CONDITIONS
MIN
TYP
MAX UNIT
3.15 V < VCC < 3.45 V
3.15 V < VCC < 5.5 V
0.4
0.4
1.4
1.7
1.8
2.6
μs
µs
μs
ns
μs
tr, tf
Driver differential output rise/fall time
CL = 50 pF,
See Figure 8
tPHL, tPLH
tSK(P)
Driver propagation delay
RL = 54 Ω, CL = 50 pF, See Figure 8
RL = 54 Ω, CL = 50 pF, See Figure 8
0.8
20
2
Driver differential output pulse skew,
250
|tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
See Figure 9 and Figure 10
Receiver enabled
0.1
0.2
3
5
3
See Figure 9 and
Figure 10
tPZH, tPZL
Driver enable time
μs
Receiver disabled
12
DRIVER (SN65HVD1781)
tr, tf
Driver differential output rise/fall time
RL = 54 Ω, CL = 50 pF, See Figure 8
RL = 54 Ω, CL = 50 pF, See Figure 8
50
300
200
ns
ns
tPHL, tPLH
Driver propagation delay
Driver differential output pulse skew,
tSK(P)
RL = 54 Ω, CL = 50 pF, See Figure 8
25
ns
|tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
See Figure 9 and Figure 10
Receiver enabled
3
300
10
μs
ns
μs
See Figure 9 and
tPZH, tPZL
Driver enable time
Figure 10
Receiver disabled
DRIVER (SN65HVD1782)
All VCC and Temp
50
RL = 54 Ω,
CL = 50 pF
tr, tf
Driver differential output rise/fall time
ns
VCC > 4.5V and T < 105°C
16
tPHL, tPLH
tSK(P)
Driver propagation delay
RL = 54 Ω, CL = 50 pF, See Figure 8
RL = 54 Ω, CL = 50 pF, See Figure 8
55
10
ns
ns
Driver differential output pulse skew,
|tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
See Figure 9 and Figure 10
Receiver enabled
3
300
9
μs
ns
μs
See Figure 9 and
tPZH, tPZL
Driver enable time
Figure 10
Receiver disabled
RECEIVER (ALL DEVICES UNLESS OTHERWISE NOTED)
CL = 15 pF,
See Figure 11
4
15
(1)
tr, tf
Receiver output rise/fall time
All devices
ns
ns
HVD1780-Q1,
HVD1781-Q1
100
200
80
CL = 15 pF,
See Figure 11
tPHL, tPLH
Receiver propagation delay time
HVD1782-Q1
HVD1780-Q1,
HVD1781-Q1
6
20
Receiver output pulse skew,
CL = 15 pF,
See Figure 11
tSK(P)
ns
|tPHL – tPLH
|
HVD1782-Q1
5
100
300
9
(1)
tPLZ, tPHZ
Receiver disable time
Receiver enable time
Driver enabled, See Figure 12
Driver enabled, See Figure 12
Driver disabled, See Figure 13
15
80
3
ns
ns
μs
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)
(1) Ensured by design. Not production tested.
6.9 Package Dissipation Ratings
JEDEC
THERMAL
MODEL
TA = 125°C
RATING (3.3 V
ONLY)
TA < 25°C
RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
RATING
TA = 105°C
RATING
PACKAGE(1)
High-K
Low-K
905 mW
516 mW
7.25 mW/°C
4.1 mW/°C
470 mW
268 mW
325 mW
186 mW
180 mW
103 mW
SOIC (D) 8-pin
(1) For the most current package and ordering information, see the Mechanical, Packaging, and Orderable Information section, or see the
TI website at www.ti.com.
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6.10 Typical Characteristics
80
70
60
50
40
30
20
10
T
= 25°C
A
RE at V
DE at V
CC
0
V
= 5 V
CC
CC
R
C
= 54 W
= 50 pF
L
L
−10
−20
−30
V
CC
= 3.3 V
T
= 25°C
A
DE at V
CC
D at V
−40
−50
CC
R
= 54 W
L
0
100 200 300 400 500 600 700 800 900 1000
Signaling Rate − kbps
0
1
2
3
4
5
6
V
− Supply Voltage − V
CC
G002
G001
Figure 2. RMS Supply Current vs Signaling Rate
Figure 1. Driver Output Current vs Supply Voltage
4.4
35
4.0
30
V
= 5.5 V
CC
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
VCC = 3.3 V
25
20
Load = 300 W
Load = 100 W
Load = 60 W
15
VCC = 5 V
10
V
CC
= 3.3 V
5
0
V
CC
= 3.15 V
0
5
10 15 20 25 30 35 40 45 50
− Differential Load Current − mA
-50
0
50
100
150
I
(diff)
Temperature - (°C)
G003
Figure 3. Differential Output Voltage vs Differential Load
Current
Figure 4. SN65HVD1782 Rise and Fall Time
2.5
R
C
= 50 W,
V
= 5.5 V
L
L
CC
2.3
2.1
1.9
= 50 pF
V
= 5 V
CC
1.7
1.5
1.3
1.1
0.9
V
= 4.5 V
CC
V
= 4 V
CC
V
= 3.6 V
CC
V
= 3.3 V
CC
V
= 3 V
CC
0.7
0.5
Transition Time − ns
Figure 5. SN65HVD1780 Differential Output Amplitude and Transition Time vs Supply Voltage
8
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SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
7 Parameter Measurement Information
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 ns, output impedance 50 Ω.
375 W ±1%
VCC
DE
A
B
D
VOD
0 V or 3 V
60 W ±1%
+
_
–7 V < V(test) < 12 V
375 W ±1%
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load
VCC
VA
A
B
27 W ±1%
DE
A
B
VB
D
Input
VOC(PP)
VOC
DVOC(SS)
CL = 50 pF ±20%
27 W ±1%
VOC
CL Includes Fixture and
Instrumentation Capacitance
Copyright © 2016, Texas Instruments Incorporated
Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
3 V
VCC
VI
50%
50%
DE
CL = 50 pF ±20%
A
B
D
tPLH
tPHL
VOD
CL Includes Fixture
» 2 V
and Instrumentation
Capacitance
Input
Generator
RL = 54 W
±1%
90%
90%
VI
VOD
50 W
0 V
10%
0 V
10%
» –2 V
tr
tf
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3 V
A
S1
VO
D
VI
50%
50%
3 V
B
0 V
DE
0.5 V
RL = 110 W
± 1%
CL = 50 pF ±20%
tPZH
VOH
90%
Input
Generator
CL Includes Fixture
50 W
VI
and Instrumentation
Capacitance
VO
50%
» 0 V
tPHZ
Copyright © 2016, Texas Instruments Incorporated
NOTE: D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
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Parameter Measurement Information (continued)
3 V
RL = 110 W
±1%
» 3 V
A
B
VI
50%
50%
S1
D
VO
3 V
0 V
tPZL
tPLZ
DE
CL = 50 pF ±20%
» 3 V
Input
Generator
VI
50 W
CL Includes Fixture
VO
50%
and Instrumentation
Capacitance
10%
VOL
Copyright © 2016, Texas Instruments Incorporated
NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 10. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
A
VO
R
Input
Generator
50 W
VI
B
1.5 V
0 V
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
3 V
VI
50%
50%
0 V
tPLH
tPHL
VOH
90% 90%
VO
50%
10%
50%
10%
VOL
tr
tf
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
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SLLSE49D –SEPTEMBER 2010–REVISED JULY 2017
Parameter Measurement Information (continued)
3 V
DE
VCC
A
B
VO
1 kW ± 1%
CL = 15 pF ±20%
R
D
0 V or 3 V
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
3 V
VI
50%
50%
0 V
tPZH(1)
tPHZ
VOH
D at 3 V
S1 to GND
90%
VO
50%
» 0 V
tPZL(1)
tPLZ
VCC
D at 0 V
S1 to VCC
VO
50%
10%
VOL
Copyright © 2016, Texas Instruments Incorporated
Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled
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Parameter Measurement Information (continued)
VCC
A
B
VO
0 V or 1.5 V
1.5 V or 0 V
1 kW ± 1%
CL = 15 pF ±20%
R
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
3 V
VI
50%
0 V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to GND
VO
50%
GND
VCC
tPZL(2)
A at 0 V
B at 1.5 V
S1 to VCC
VO
50%
VOL
Copyright © 2016, Texas Instruments Incorporated
Figure 13. SN65HVD1781 Measurement of Receiver Enable Times With Driver Disabled
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8 Detailed Description
8.1 Overview
The SN65HVD1780-Q1, SN65HVD1781-Q1, and SN65HVD1782-Q1 devices are half-duplex RS-485
transceivers available in three speed grades suitable for data transmission up to 115 kbps, 1 Mbps, and 10
Mbps.
These devices feature a wide common-mode operating range and bus-pin fault protection up to ±70 V. Each
device has an active-high driver enable and active-low receiver enable. A standby current of less than 1 µA can
be achieved by disabling both driver and receiver.
8.2 Functional Block Diagram
VCC
R
RE
A
B
DE
D
GND
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
Internal ESD protection circuits protect the transceiver bus terminals against ±16-kV Human Body Model (HBM)
electrostatic discharges.
Device operation is specified over a wide temperature range from –40°C to 125°C.
8.3.1 Bus Fault Conditions
The SN65HVD178x-Q1 family of RS-485 transceivers is designed to survive bus pin faults up to ±70 V. The
SN65HVD1782-Q1 device will not survive a bus pin fault with a direct short to voltages above 30 V when all of
the following occurs:
•
•
The device is powered on
The driver is enabled (DE = HIGH), and one of of the following is true
–
–
D = HIGH AND the bus fault is applied to the A pin
D = LOW AND the bus fault is applied to the B pin
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Feature Description (continued)
Under other conditions, the device survives shorts to bus pin faults up to ±70 V. Table 1 summarizes the
conditions under which the device may be damaged, and the conditions under which the device will not be
damaged.
Table 1. Bus Fault Conditions for the HVD1782
POWER
OFF
ON
DE
X
D
X
X
L
A
B
RESULTS
–70 V < VA < 70 V
–70 V < VA < 70 V
–70 V < VA < 70 V
–70 V < VA < 70 V
–70 V < VA < 30 V
30 V < VA
–70 V < VB < 70 V
–70 V < VB < 70 V
–70 V < VB < 30 V
30 V < VB
Device survives
Device survives
Device survives
Damage may occur
Device survives
Damage may occur
LO
HI
HI
HI
HI
ON
ON
L
ON
H
H
–70 V < VB < 30 V
–70 V < VB < 30 V
ON
8.3.2 Receiver Failsafe
The SN65HVD178x-Q1 family of half-duplex transceivers provides internal biasing of the receiver input
thresholds in combination with large input-threshold hysteresis. At a positive input threshold of VIT+ = –35 mV
and an input hysteresis of VHYS = 30 mV, the receiver output remains logic high under bus-idle, bus-short, or
open bus conditions in the presence of up to 130-mVPP differential noise without the need for external failsafe
biasing resistors.
8.3.3 Hot-Plugging
These devices are designed to operate in hot swap or hot-pluggable applications. Key features for hot-pluggable
applications are power-up and power-down glitch free operation, default disabled input and output pins, and
receiver failsafe.
As shown in the Functional Block Diagram, an internal power-on reset circuit keeps the driver outputs in a high
impedance state until the supply voltage has reached a level at which the device will reliably operate. This circuit
ensures that no problems occur on the bus pin outputs as the power supply turns on or off.
As shown in Device Functional Modes, the driver and receiver enable inputs (DE and RE) are disabled by
default. This default ensures that the device neither drives the bus nor reports data on the R pin until the
associated controller actively drivers the enable pins.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 2. Driver Function Table
INPUT
ENABLE
OUTPUTS
DRIVER STATE
D
DE
A
B
L
H
H
H
L
Actively drive bus High
L
X
H
L
H
Z
Z
L
Actively drive bus Low
Driver disabled
Z
Z
H
X
OPEN
H
Driver disabled by default
Actively drive bus High by default
OPEN
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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns
low. If VID is between VIT+ and VIT– the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 3. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
VID > VIT+
ENABLE OUTPUT
RECEIVER STATE
RE
R
H
?
L
Receive valid bus High
VIT– < VID < VIT+
VID < VIT–
L
Indeterminate bus state
Receive valid bus Low
Receiver disabled
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN65HVD178x-Q1 family of devices is a half-duplex RS-485 transceiver commonly used for asynchronous
data transmissions. The driver and receiver enable pins allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
B
RE
A
B
RE
A
B
DE
D
DE
D
DE
D
D
D
D
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Half-Duplex Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high, and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
R
R
A
B
A
B
RE
RE
RT
RT
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Typical RS-485 Network With Half-Duplex Transceivers
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Typical Application (continued)
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 16. Cable Length vs Data Rate Characteristic
9.2.1.2 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65HVD7x-Q1 family of devices
consists of 1/10 UL transceivers, it is possible to connect up to 320 receivers to the bus.
9.2.2 Detailed Design Procedure
Although the SN65HVD178x-Q1 family of devices is internally protected against human-body-model ESD strikes
up to 16 kV, additional protection against higher-energy transients can be provided at the application level by
implementing external protection devices.
Figure 17 shows a protection circuit intended to withstand 8-kV IEC ESD (per IEC 61000-4-2) as well as 4-kV
EFT (per IEC 61000-4-4).
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Typical Application (continued)
3.3 V
100 nF
100 nF
VCC
10 kꢀ
R1
TVS
R
RxD
RE
DE
D
A
B
MCU/
UART
DIR
TxD
R2
GND
10 kꢀ
Copyright © 2016, Texas Instruments Incorporated
Figure 17. RS-485 Transceiver with External Transient Protection
Table 4. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
RS-485 Transceiver
SN65HVD178x-Q1
TI
10-Ω, Pulse-Proof Thick-Film
R1, R2
TVS
CRCW0603010RJNEAHP
SMBJ43CA
Vishay
Resistor
Bidirectional 600-W Transient
Suppressor
Littlefuse
9.2.2.1 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
9.2.2.2 Receiver Failsafe
The differential receivers of the SN65HVD178x-Q1 family have receiver input thresholds that are offset so that
receiver output state is known for the following three fault conditions:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the
receiver is not indeterminate.
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Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a High when the differential input VID is more positive than 200 mV, and must output a Low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT(+), VIT(–), and VHYS (the separation between VIT(+) and VIT(–)). As shown in the Electrical Characteristics table,
differential signals more negative than –200mV will always cause a Low receiver output, and differential signals
more positive than 200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –35 mV, and
the receiver output will be High. Only when the differential input is more than VHYS below VIT(+) will the receiver
output transition to a Low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition
includes the receiver hysteresis value, VHYS, as well as the value of VIT(+)
.
R
Vhys (min)
30 mV
VID (mV)
-65
-35
0
+65
Vn max = 130 mVpp
Figure 18. Noise Immunity Under Bus Fault Conditions
9.2.3 Application Curve
SN65HVD1781-Q1 D Input
Differential Output
R Output
1-Mbps Operation
Figure 19. SN65HVD1781-Q1 PRBS Data Pattern
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS7A6150-Q1 is a linear voltage
regulator suitable for the 5-V supply.
11 Layout
11.1 Layout Guidelines
On-chip IEC-ESD protection is good for laboratory and portable equipment but often insufficient for EFT and
surge transients occurring in industrial environments. Therefore robust and reliable bus node design requires the
use of external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-
frequency layout techniques must be applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
2. Use VCC and ground planes to provide low-inductance. High-frequency currents follow the path of least
inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of the transceiver, UART, or
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
7. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example
5
Via to ground
Via to VCC
4
C
R
R
6
6
R
R
1
MCU
5
TVS
SN65HVD178x
5
Figure 20. Half-Duplex Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
RS-485 Half-Duplex Evaluation Module
SN65HVD17xx Fault-Protected RS-485 Transceivers With Extended Common-Mode Range
TPS7A6xxx-Q1 300-mA 40-V Low-Dropout Regulator With 25-µA Quiescent Current
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2017, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65HVD1780QDRQ1
SN65HVD1781QDRQ1
SN65HVD1782QDRQ1
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
1780Q
NIPDAU
NIPDAU
1781Q
1782Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD1780-Q1, SN65HVD1781-Q1, SN65HVD1782-Q1 :
Catalog: SN65HVD1780, SN65HVD1781, SN65HVD1782
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD1780QDRQ1
SN65HVD1781QDRQ1
SN65HVD1782QDRQ1
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
6.4
5.2
5.2
5.2
2.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65HVD1780QDRQ1
SN65HVD1781QDRQ1
SN65HVD1782QDRQ1
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
367.0
356.0
367.0
367.0
356.0
367.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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