SN65HVD251DRG4 [TI]
CAN TRANSCEIVER; CAN收发器
| 型号： | SN65HVD251DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CAN TRANSCEIVER |
| 文件： | 总19页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD251
www.ti.com
SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
CAN TRANSCEIVER
Designed for operation in harsh environments, the
device features cross-wire, over-voltage and loss of
ground protection to ±36 V. Also featured are
over-temperature protection as well as -7 V to 12 V
common-mode range, and tolerance to transients of
±200 V. The transceiver interfaces the single-ended
CAN controller with the differential CAN bus found in
industrial, building automation, and automotive appli-
cations.
FEATURES
•
Drop-In Improved Replacement for the
PCA82C250 and PCA82C251
•
•
•
•
Bus-Fault Protection of ±36 V
Meets or Exceeds ISO 11898
Signaling Rates(1) Up to 1 Mbps
High Input Impedance Allows up to 120
SN65HVD251 Nodes on a Bus
•
•
•
•
•
Bus Pin ESD Protection Exceeds 14 kV HBM
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode — 200 µA Typical
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down Bus
Protection For Hot-Plugging
Rs, pin 8, selects one of three different modes of
operation: high-speed, slope control, or low-power
mode. The high-speed mode of operation is selected
by connecting pin 8 to ground, allowing the transmit-
ter output transistors to switch as fast as possible
with no limitation on the rise and fall slope. The rise
and fall slope can be adjusted by connecting a
resistor to ground at pin 8; the slope is proportional to
the pin's output current. Slope control with an external
resistor value of 10 kΩ gives ~ 15 V/us slew rate; 100
kΩ gives ~ 2 V/us slew rate.
•
(1)
DeviceNet Vendor ID # 806
The signaling rate of a line is the number of voltage transitions
that are made per second expressed in bps (bits per second).
If a high logic level is applied to the Rs pin 8, the
device enters a low-current standby mode where the
driver is switched off and the receiver remains active.
The local protocol controller returns the device to the
normal mode when it transmits to the bus.
APPLICATIONS
•
CAN Data Buses
•
Industrial Automation
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
The SN65HVD251 may be used in CAN,
DeviceNet™ or SDS™ applications with the Texas
Instruments' TMS320F241 and TMS320F243 DSPs
with CAN 2.0B controllers.
•
•
•
function diagram
(positive logic)
DESCRIPTION
3
5
The SN65HVD251 is intended for use in applications
employing the Controller Area Network (CAN) serial
communication physical layer in accordance with the
ISO 11898 Standard. The SN65HVD251 provides
differential transmit capability to the bus and differen-
tial receive capability to a CAN controller at speeds
up to 1 megabits per second (Mbps).
V
V
1
2
ref
8
7
Rs
D
CC
GND
CANH
CANL
Vref
1
8
D
Vcc
R
3
4
6
5
R
S
7
6
CANH
CANL
4
R
ORDERING INFORMATION
PART NUMBER
SN65HVD251D
SN65HVD251DR
SN65HVD251P
PACKAGE
8-pin SOIC (Tube)
8-pin SOIC (Tape & Reel)
8-pin DIP
MARKED AS
VP251
VP251
65HVD251
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNet is a trademark of Allen-Bradley.
SDS is a trademark of Honeywell.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD251
www.ti.com
SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)(2)
SN65HVD251
Supply voltage range, VCC
-0.3 V to 7 V
-36 V to 36 V
±200 V
Voltage range at any bus terminal (CANH or CANL)
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b
Input voltage range, VI (D, Rs, or R)
Receiver output current, IO
CANH, CANL
-0.3 V to VCC + 0.5
–10 mA to 10 mA
14 kV
CANH, CANL and GND
All pins
(3)
Human Body Model
Electrostatic discharge
6 kV
(4)
Charged-Device Model
All pins
1 kV
Continuous total power dissipation
(see Dissipation Rating
Table)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS
(1)
CIRCUIT BOARD
MODEL
TA = 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C POWER
RATING
TA = 125°C POWER
RATING
PACKAGE
Low-K(2)
High-K(3)
Low-K(2)
High-K(3)
576 mW
924 mW
888 mW
1212 mW
4.8 mW/°C
7.7 mW/°C
7.4 mW/°C
10.1 mW/°C
288 mW
462 mW
444 mW
606 mW
96 mW
154 mW
148 mW
202 mW
SOIC (D)
PDIP (P)
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
TYP
78.7
UNITS
MIN
MAX
D
P
D
P
Θ
Θ
Junction-to-board thermal resistance
Junction-to-case thermal resistance
°C/W
JB
JC
48.9
44.6
66.6
°C/W
mW
VCC = 5 V, Tj = 27 °C, RL = 60Ω,
RS at 0 V, Input to D a 500-kHz
50% duty cycle square wave
97.7
142
PD
Device power dissipation
VCC = 5.5 V, Tj = 130°C, RL = 60Ω,
RS at 0 V, Input to D a 500-kHz 50%
duty cycle square wave
mW
°C
TSD
Thermal shutdown junction temperature
165
2
SN65HVD251
www.ti.com
SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
RECOMMENDED OPERATING CONDITIONS
over recommended operating conditions (unless otherwise noted).
PARAMETER
Supply voltage, VCC
MIN
NOM
MAX
UNIT
V
4.5
-7(1)
5.5
12
Voltage at any bus terminal (separately or common mode) VI or VIC
V
High-level input voltage, VIH
Low-level input voltage, VIL
Differential input voltage, VID
Input voltage to Rs, VI(Rs)
D input
D input
0.7 VCC
V
0.3 VCC
6
V
-6
V
0
VCC
VCC
100
V
Input voltage at Rs for standby, VI(Rs)
Rs wave-shaping resistance
0.75 VCC
V
0
-50
-4
kΩ
Driver
High-level output current, IOH
mA
Receiver
Driver
50
4
Low-level output current, IOL
Operating free-air temperature, TA
Junction temperature, Tj
mA
°C
Receiver
-40
125
145
145
PDIP Package
SOIC Package
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN TYP( MAX UNIT
1)
CANH
CANL
CANH
CANL
2.75
0.5
2
3.5
4.5
2
Bus output voltage
(Dominant)
Figure 1 & Figure 2 ,
D at 0 V Rs at 0 V
VO(D)
V
2.5
2.5
2
3
Bus output voltage
(Recessive)
VO(R)
Figure 1 & Figure 2 , D at 0.7VCC , Rs at 0 V
2
3
VOD(D)
VOD(D)
VOD(R)
VOD(R)
Differential output voltage (Dominant)
Differential output voltage (Dominant)
Differential output voltage (Recessive)
Differential output voltage (Recessive)
Figure 1 , D at 0 V, Rs at 0 V
Figure 2 & Figure 3 , D at 0 V, Rs at 0 V
Figure 1 & Figure 2 , D at 0.7 VCC
D at 0.7 VCC, no load
1.5
1.2
-120
-0.5
3
V
V
2
3.1
12 mV
0.05
V
VOC(pp) Peak-to-peak common-mode output voltage
Figure 9, Rs at 0 V
600
mV
µA
µA
IIH
IIL
High-level input current, D Input
Low-level input current, D Input
D at 0.7 VCC
-40
-60
0
0
D at 0.3 VCC
Figure 11, VCANH at -7 V, CANL Open
Figure 11, VCANH at 12 V, CANL Open
Figure 11, VCANL at -7 V, CANH Open
Figure 11, VCANL at 12 V, CANH Open
See receiver input capacitance
See receiver input current
Rs at 0.75 VCC
-200
2.5
IOS(SS)
Short-circuit steady-state output current
mA
-2
200
CO
Output capacitance
IOZ
High-impedance output current
Rs input current for standby
Rs input current for full speed operation
Standby
IIRs(s)
IIRs(f)
-10
µA
µA
Rs at 0 V
-550
0
Rs at VCC, D at VCC
275 µA
ICC
Supply current
Dominant
Recessive
D at 0 V, 60Ω load, Rs at 0 V
D at VCC, no load, Rs at 0 V
65
mA
14
(1) All typical values are at 25°C and with a 5-V supply.
3
SN65HVD251
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
40
MAX UNIT
Figure 4, Rs at 0 V
70
125
800
125
260
1450
85
tpLH
tpHL
tsk(p)
Propagation delay time, low-to-high-level output
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
Figure 4, Rs at 0 V
90
500
85
Propagation delay time, high-to-low-level output
Pulse skew (|tpHL - tpLH|)
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
Figure 4, Rs at 0 V
200
1150
45
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
110
650
180
900
100
100
250
250
1550
1550
0.5
ns
tr
Differential output signal rise time
Differential output signal fall time
Differential output signal rise time
Differential output signal fall time
Differential output signal rise time
Differential output signal fall time
Enable time from standby to dominant
35
35
Figure 4, Rs at 0 V
tf
tr
100
100
600
600
Figure 4, Rs with 10 kΩ to ground
tf
tr
Figure 4, Rs with 100 kΩ to ground
tf
ten
Figure 8
µs
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage
750 900
VIT-
Negative-going input threshold voltage
Rs at 0 V, (See Table 1)
500 650
100
mV
Vhys Hysteresis voltage (VIT+ - VIT-
)
VOH High-level output voltage
Figure 6, IO = -4mA
Figure 6, IO = 4mA
CANH or CANL at 12 V
0.8
Vcc
V
V
VOL Low-level output voltage
0.2
Vcc
600
Other bus
pin at 0 V,
Rs at 0 V,
D at 0.7
VCC
CANH or CANL at 12 V,
VCC at 0 V
715
II
Bus input current
µA
CANH or CANL at -7 V
-460
-340
CANH or CANL at -7 V,
VCC at 0 V
Pin-to-ground, VI = 0.4 sin (4E6πt) +
0.5 V, D at 0.7 VCC
pF
pF
CI
Input capacitance, (CANH or CANL)
Differential input capacitance
20
10
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5
V, D at 0.7 VCC
CID
RID
RIN
Differential input resistance
D at 0.7 VCC, Rs at 0 V
D at 0.7 VCC, Rs at 0 V
Rs at VCC, D at VCC
40
20
100 kΩ
50 kΩ
275 µA
Input resistance, (CANH or CANL)
Standby
ICC
Supply current
Dominant
Recessive
D at 0 V, 60Ω Load, Rs at 0 V
D at VCC, No Load, Rs at 0 V
65
mA
14
4
SN65HVD251
www.ti.com
SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
35
MAX
50
50
20
4
UNIT
tpLH
tpHL
tsk(p)
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew (|tpHL - tpLH|)
35
Figure 6
ns
Output signal rise time
2
2
tf
Output signal fall time
4
tp(sb)
Propagation delay time in standby
Figure 12, Rs at VCC
500
VREF-PIN CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
0.45 VCC
0.4 VCC
TYP
MAX
0.55 VCC
0.6 VCC
UNIT
-5 µA < IO < 5 µA
VO
Reference output voltage
V
-50 µA < IO < 50 µA
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
100
150
800
150
290
1450
145
UNIT
Figure 10, Rs at 0 V
60
100
440
115
235
1070
105
Total loop delay, driver input to receiver
output, recessive to dominant
tloop1
Figure 10, Rs with 10 kΩ to ground
Figure 10, Rs with 100 kΩ to ground
Figure 10, Rs at 0 V
ns
Total loop delay, driver input to receiver
output, dominant to recessive
tloop2
Figure 10, Rs with 10 kΩ to ground
Figure 10, Rs with 100 kΩ to ground
ns
ns
tloop2
Total loop delay, driver input to receiver
output, dominant to recessive
Figure 10, Rs at 0 V, VCC from 4.5 V to 5.1
V,
PARAMETER MEASUREMENT INFORMATION
I
O(CANH)
V
O(CANH)
D
V
OD
I
I
60 W + 1%
V
+ V
2
O(CANH)
O(CANL)
I
Rs
V
OC
IRs
V
I
+
I
O(CANL)
V
I(Rs)
_
V
O(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
5
SN65HVD251
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Dominant
V
O(CANH)
9 3.5 V
9 2.5 V
9 1.5 V
Recessive
V
O(CANL)
Figure 2. Bus Logic State Voltage Definitions
330 W + 1%
CANH
D
60 W + 1%
V
OD
V
I
+
–7 V 3 V
3 12 V
_
TEST
R
S
CANL
330 W + 1%
Figure 3. Driver VOD
CANH
D
R
=
C
=
L
L
V
O
60 W + 1%
50 pF + 20%
(see Note B)
V
I
+
Rs
(see Note A)
V
I(Rs)
_
CANH
V
CC
V
CC/2
V
CC/2
V
I
0 V
t
t
PHL
PLH
V
O(D)
O(R)
90%
10%
0.9V
V
O
0.5V
V
t
r
t
f
Figure 4. Driver Test Circuit and Voltage Waveforms
CANH
R
V
I
O
I(CANH)
V
ID
V
V
I(CANH) + I(CANL)
2
V
IC
=
V
O
CANL
V
I(CANL)
Figure 5. Receiver Voltage and Current Definitions
6
SN65HVD251
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
CANH
R
I
O
V
I
CANL
C = 15 pF
L
+ 20% (see Note B)
V
O
(see Note A)
1.5 V
3.5 V
1.5 V
2.4 V
V
I
2 V
t
t
PLH
PHL
V
OH
90%
0.7 V
CC
V
O
0.3 V
CC
10%
10%
V
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 6. Receiver Test Circuit and Voltage Waveforms
CANH
R
CANL
100 W
Pulse Generator
15 ms Duration
D at 0 V
or V
CC
1% Duty Cycle
t , t 3 100 ns
r
r
R
S
at 0 V or V
CC
A. This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 7. Test Circuit, Transient Over-Voltage Test
Table 1. Receiver Characteristics Over Common Mode Voltage
INPUT
MEASURED
|VID
OUTPUT
R
VCANH
12 V
-6.1 V
-1 V
VCANL
11.1 V
-7 V
|
900 mV
900 mV
6 V
L
L
VOL
-7 V
L
12 V
-6.5 V
12 V
-7 V
6 V
6 V
L
-7 V
500 mV
500 mV
6 V
H
H
H
H
H
11.5 V
-1 V
VOH
6 V
12 V
open
6 V
open
X
7
SN65HVD251
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
DUT
CANH
CANL
D
0 V
60 W + 1%
Rs
V
I
R
+
V
15 pF + 20%
O
_
V
CC
0.7 V
CC
V
I
0 V
V
OH
0.3 V
0.3 V
CC
V
O
CC
V
OL
t
en
Figure 8. ten Test Circuit and Voltage Waveforms
27 W + 1%
CANH
D
V
I
CANL
27 W + 1%
50 pF +20%
V
OC
R
S
V
OC(PP)
V
OC
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
Figure 9. Peak-to-Peak Common Mode Output Voltage
8
SN65HVD251
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
DUT
CANH
D
60 W + 1%
CANL
V
I
10 kW or 100 kW + 5%
R
S
_
V
Rs
+
R
+
15 pF + 20%
V
O
_
V
CC
50%
D Input
0 V
t
t
Loop1
Loop2
V
OH
0.7 Vcc
R Output
0.3 Vcc
V
OL
Figure 10. tLOOP Test Circuit and Voltage Waveforms
I
OS
CANH
D
0 V or V
CC
CANL
V
–7 V or 12 V
Rs
in
JI
J
OS(SS)
JI
OS(P)
J
15 s
0 V
12 V
V
in
0 V
0 V
10 ms
or
V
in
–7 V
Figure 11. Driver Short-Circuit Test
9
SN65HVD251
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
CANH
CANL
R
V
I
C = 15 pF
L
(see Note A)
V
1.5 V
O
(see Note B)
3.5 V
1.5 V
2.4 V
V
I
t
p(sb)
V
V
OH
V
O
0.3 V
CC
OL
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 12. Receiver Propagation Delay in Standby Test Circuit and Waveform
DEVICE INFORMATION
5 V
R2+ 1%
R1+ 1%
CANH
+
R
V
ID
–
CANL
Vac
R1+ 1%
V
I
R2+ 1%
V
ID
R1
R2
50 W
50 W
450 W
500 mV
900 mV
227 W
12 V
V
I
–7 V
A. All input pulses are supplied by a generator having the following characteristics: f < 1.5 MHz, TA = 25oC, VCC = 5.0 V.
Figure 13. Common-Mode Input Voltage Rejection Test
10
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
DEVICE INFORMATION (continued)
FUNCTION TABLES
Table 2. DRIVER
INPUTS
OUTPUTS
Voltage at Rs, VRs
D
BUS STATE
CANH
CANL
L
H
VRs < 1.2 V
VRs < 1.2 V
X
H
Z
Z
Z
L
Z
Z
Z
Dominant
Recessive
Recessive
Recessive
Open
X
VRs > 0.75 VCC
Table 3. RECEIVER
DIFFERENTIAL INPUTS [VID = V(CANH) - V(CANL)]
ID≥ 0.9 V
0.5V < VID < 0.9 V
OUTPUT R(1)
V
L
?
V
ID ≤ 0.5 V
H
H
Open
(1) H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
11
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
D Input
R Output
Vcc
Vcc
100 kW
1 kW
15 W
Input
Output
9 V
9 V
CANH Input
CANL Input
Vcc
Vcc
110 kW
9 kW
110 kW
45 kW
9 kW
45 kW
Input
Input
9 kW
9 kW
40 V
40 V
CANH and CANL Outputs
Vcc
Rs Input
Vcc
Output
40 V
+
Input
Figure 14. Equivalent Input and Output Schematic Diagrams
12
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SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
tLOOP1-LOOP TIME
tLOOP2-LOOP TIME
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT (RMS)
vs
vs
FREE-AIR TEMPERATURE
SIGNALING RATE
150
145
140
135
130
33
32
31
30
29
28
27
R
S
= 0 V
R
S
= 0 V
V
= 5 V,
CC
74
72
70
68
66
T
= 25°C,
= 0 V,
A
R
R
C
S
L
L
V
= 5.5 V
CC
V
= 4.5 V
CC
= 60 Ω,
= 50 pF
V
= 5 V
CC
V
= 5 V
CC
V
= 4.5 V
CC
V
= 5.5 V
CC
125
120
64
62
26
25
–40 –25 –10
5
20
65 80 95 110 125
35 50
–40 –25 –10
5
20 35 50 65 80 95 110 125
0
250 500 750 1000 1250 1500 1750 2000
T
A
– Free-Air Temperature – 5C
T
A
– Free-Air Temperature – 5C
Signaling Rate – kbps
Figure 15.
Figure 16.
Figure 17.
DRIVER LOW-LEVEL OUTPUT CUR-
DRIVER HIGH-LEVEL OUTPUT CUR-
DOMINANT DIFFERENTIAL
OUTPUT VOLTAGE
vs
RENT
RENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
FREE-AIR TEMPERATURE
140
120
100
80
80
V
T
R
= 5 V,
= 25°C,
= 0 V,
3
CC
V
= 5 V,
= 25°C,
= 0 V,
CC
V
= 5.5 V
A
70
60
50
40
30
20
CC
T
A
S
R
S
2.5
D at 0V
D at 0V
2
V
= 4.5 V
CC
V
= 5 V
CC
60
1.5
1
40
R
= 0 V,
S
20
0.5
D at 0V,
= 60 Ω
10
0
R
L
0
0
1
2
3
4
5
0
1
2
3
4
5
0
–55 –40
0
25
70
85
125
V
CANH – High-Level Output Voltage – V
V
CANL – Low-Level Output Voltage – V
O
O
T
A
– Free-Air Temperature – 5 C
Figure 18.
Figure 19.
Figure 20.
DRIVER OUTPUT CURRENT
vs
DIFFERENTIAL OUTPUT
FALL TIME
INPUT RESISTANCE MATCHING
vs
SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
SLOPE RESISTANCE (Rs)
0
−0.50
−1
1000
900
800
700
600
500
400
300
200
100
0
60
50
40
30
20
T
A
= 25°C
V
= 5.5 V
CC
T
R
= 25°C,
= 0 V,
A
S
V
= 5.5 V
CC
V
= 5 V
D at 0V,
R
CC
= 60 Ω
L
V
= 4.5 V
CC
−1.50
−2
V
= 5 V
CC
V
= 4.5 V
CC
−2.50
−3
10
0
0
10 20 30 40 50 60 70 80 90 100
−50
0
50
100
150
1
2
3
4
5
6
T
A
− Free-Air Temperature − °C
R
S
- Slope Resistance - kW
V
– Supply Voltage – V
CC
Figure 21.
Figure 22.
Figure 23.
13
SN65HVD251
www.ti.com
SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
APPLICATION INFORMATION
lators in a system must also be accounted for with
adjustments in signaling rate and stub & bus length.
Table 4 lists the maximum signaling rates achieved
with the SN65HVD251 in high-speed mode with
several bus lengths of category-5, shielded
twisted-pair (CAT 5 STP) cable.
The basics of bus arbitration require that the receiver
at the sending node designate the first bit as domi-
nant or recessive after the initial wave of the first bit
of a message travels to the most remote node on a
network and back again. Typically, this sample is
made at 75% of the bit width, and within this
limitation, the maximum allowable signal distortion in
a CAN network is determined by network electrical
parameters.
Table 4. Maximum Signaling Rates for Various
Cable Lengths
BUS LENGTH (m)
SIGNALING RATE (kbps)
Factors to be considered in network design include
the 5 ns/m propagation delay of typical twisted-pair
bus cable; signal amplitude loss due to the loss
mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under
strict analysis, variations among the different oscil-
30
100
250
500
1000
1000
500
250
125
62.5
The ISO 11898 standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A bus
with a large number of nodes requires a transceiver with high input impedance such as the HVD251.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the ISO 11898 standard, should have as little effect as possible on standard
operating parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the –2-V to 7-V common-mode range of tolerable
ground noise specified in the standard, helps to ensure data integrity. The HVD251 extends data integrity beyond
that of the standard with an extended –7-V to 12-V range of common-mode operation.
NOISE MARGIN
900 mV Threshold
75% SAMPLE POINT
NOISE MARGIN
RECEIVER DETECTION WINDOW
500 mV Threshold
ALLOWABLE JITTER
Figure 24. Typical CAN Differential Signal Eye-Pattern
14
SN65HVD251
www.ti.com
SLLS545C–NOVEMBER 2002–REVISED SEPTEMBER 2005
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 24, the differential
signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic
crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all effects of
systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces & cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC & ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the HVD251 mitigate most sources of signal corruption, and when used with a
quality shielded twisted-pair cable, help ensure data integrity.
Typical Application
Bus Lines – 40 m max
CANH
120 W
120 W
Stub Lines –– 0.3 m max
CANL
5 V
5 V
3.3 V
V
ref
V
ref
V
ref
V
CC
V
CC
V
CC
0.1 m F
0.1 m F
0.1 m F
SN65HVD251
SN65HVD251
SN65HVD230
R
S
R
S
R
S
GND
GND
GND
D
R
D
R
D
R
CANTX CANRX
TMS320F243
CANTX CANRX
TMS320F243
CANTX CANRX
TMS320LF2407A
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Figure 25. Typical HVD251 Application
15
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
Drawing
SN65HVD251D
SN65HVD251DR
SN65HVD251DRG4
ACTIVE
ACTIVE
ACTIVE
D
D
D
8
8
8
75
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2500
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD251P
ACTIVE
ACTIVE
PDIP
PDIP
P
P
8
8
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD251PE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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