SN65HVD3082E_17 [TI]
Low-Power RS-485 Transceivers, Available in a Small MSOP-8 Package;
| 型号： | SN65HVD3082E_17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power RS-485 Transceivers, Available in a Small MSOP-8 Package |
| 文件： | 总26页 (文件大小：892K) |
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SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
DGK
D
P
www.ti.com
SLLS562G –AUGUST 2009–REVISED MAY 2009
Low-Power RS-485 Transceivers, Available in a Small MSOP-8
Package
1
FEATURES
DESCRIPTION
•
Available in a Small MSOP-8 Package
These devices are half-duplex transceivers designed
for RS–485 data bus networks. Powered by a 5–V
supply, they are fully compliant with TIA/EIA-485A
standard. With controlled transition times, these
devices are suitable for transmitting data over long
•
Meets or Exceeds the Requirements of the
TIA/EIA−485A Standard
•
Low Quiescent Power
–
–
0.3 mA Active Mode
1 nA Shutdown Mode
twisted-pair
cables.
SN65HVD3082E
and
SN75HVD3082E devices are optimized for signaling
rates up to 200 kbps. SN65HVD3085E is suitable for
•
•
•
•
1/8 Unit Load—Up to 256 Nodes on a Bus
Bus-Pin ESD Protection Up to 15 kV
Industry-Standard SN75176 Footprint
data transmission up to
1
Mbps, whereas
SN65HVD3088E is suitable for applications requiring
signaling rates up to 20 Mbps. These devices are
designed to operate with very low supply current,
typically 0.3 mA, exclusive of the load. When in the
inactive shutdown mode, the supply current drops to
a few nanoamps, making these devices ideal for
power-sensitive applications.
Failsafe Receiver (Bus Open, Bus Shorted,
Bus Idle)
•
Glitch–Free Power–Up/Down Bus Inputs and
Outputs
APPLICATIONS
The wide common-mode range and high ESD
protection levels of these devices make them suitable
for demanding applications such as energy meter
networks, electrical inverters, status/command signals
across telecom racks, cabled chassis interconnects,
and industrial automation networks where noise
tolerance is essential. These devices match the
industry-standard footprint of SN75176. Power-on
reset circuits keep the outputs in a high impedance
state until the supply voltage has stabilized. A thermal
shutdown function protects the device from damage
due to system fault conditions. The SN75HVD3082E
is characterized for operation from 0°C to 70°C and
SN65HVD308xE are characterized for operation from
–40°C to 85°C air temperature.
•
•
•
•
•
•
•
Energy Meter Networks
Motor Control
Power Inverters
Industrial Automation
Building Automation Networks
Battery-Powered Applications
Telecommunications Equipment
ORDERING INFORMATION:
PACKAGE TYPE
TA
SIGNALING RATE (Mbps)
P
D(1)
DGK(2)
SN75HVD3082EP
Marked as 75HVD3082
SN75HVD3082ED
Marked as VN3082
SN75HVD3082EDGK
Marked as NWM
0°C to 70°C
0.2
0.2
1
SN65HVD3082EP
Marked as 65HVD3082
SN65HVD3082ED
Marked as VP3082
SN65HVD3082EDGK
Marked as NWN
SN65HVD3085ED
Marked as VP3085
SN65HVD3085EDGK
Marked as NWK
–40°C to 85°C
SN65HVD3088ED
Marked as VP3088
SN65HVD3088EDGK
Marked as NWH
20
(1) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDR).
(2) The DGK package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDGKR).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
SLLS562G –AUGUST 2009–REVISED MAY 2009
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
(2)
UNIT
Supply voltage range, VCC
–0.5 V to 7 V
–9 V to 14 V
Voltage range at A or B
Voltage range at any logic pin
–0.3 V to VCC + 0.3 V
–24 mA to 24 mA
–50 to 50 V
Receiver output current
Voltage input, transient pulse, A and B, through 100 Ω. See Figure 13
Junction Temperature, TJ
170°C
Continuous total power dissipation
See the Package Dissipation Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
(1)
JEDEC BOARD
MODEL
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
TA = 85°C
PACKAGE
POWER RATING
POWER RATING
Low k(2)
High k(3)
Low k(2)
Low k(2)
High k(3)
507 mW
824 mW
686 mW
394 mW
583 mW
4.82 mW/°C
7.85 mW/°C
6.53 mW/°C
3.76 mW/°C
5.55 mW/°C
289 mW
471 mW
392 mW
255 mW
333 mW
217 mW
353 mW
294 mW
169 mW
250 mW
D
P
DGK
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the low-k thermal metric definitions of EIA/JESD51-3
(3) In accordance with the high-k thermal metric definitions of EIA/JESD51-7
2
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Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E
SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
www.ti.com
SLLS562G –AUGUST 2009–REVISED MAY 2009
RECOMMENDED OPERATING CONDITIONS(1)
over operating free-air temperature range unless otherwise noted
MIN
4.5
–7
NOM
MAX
5.5
12
UNIT
Supply voltage, VCC
V
Voltage at any bus terminal (separately or common mode) , VI
High-level input voltage (D, DE, or RE inputs), VIH
Low-level input voltage (D, DE, or RE inputs), VIL
Differential input voltage, VID
2
VCC
0.8
12
V
V
V
0
–12
–60
–8
Driver
Output current, IO
60
mA
Receiver
8
Differential load resistance, RL
54
60
Ω
SN65HVD3082E, SN75HVD3082E
0.2
1
Signaling rate, 1/tUI
SN65HVD3085E
Mbps
SN65HVD3088E
20
85
70
130
SN65HVD3082E, SN65HVD3085E, SN65HVD3088E
SN75HVD3082E
–40
0
Operating free–air temperature, TA
°C
°C
(2)
Junction temperature, TJ
–40
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information on maintenance of this specification for the DGK package.
SUPPLY CURRENT
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
D at VCC or open, DE at VCC
RE at 0 V, No load
,
Driver and receiver enabled
425
900
µA
D at VCC or open, DE at VCC
RE at VCC, No load
,
Driver enabled, receiver disabled
Receiver enabled, driver disabled
Driver and receiver disabled
330
300
600
600
2
µA
µA
µA
ICC
D at VCC or open, DE at 0 V,
RE at 0 V, No load
D at VCC or open, DE at 0 V,
RE at VCC
0.001
(1) All typical values are at 25°C and with a 5–V supply.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
TEST CONDITIONS
Bus terminals and GND
MIN TYP(1)
MAX
UNIT
kV
Human body model
Human body model(2)
±15
±4
All pins
kV
Charged-device-model(3)
Electrical Fast Transient/Burst(4)
All pins
±1
kV
A, B, and GND
±4
kV
(1) All typical values at 25°C.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114–A and IEC 60749–26.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
(4) Tested in accordance with IEC 61000–4–4.
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E
SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
SLLS562G –AUGUST 2009–REVISED MAY 2009
www.ti.com
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
3
TYP(1)
4.3
MAX UNIT
IO = 0, No Load
RL = 54 Ω, See Figure 1
RL = 100 Ω
1.5
2
2.3
|VOD
|
Differential output voltage
V
VTEST = –7 V to 12 V, See Figure 2
1.5
Change in magnitude of differential
output voltage
Δ|VOD
|
See Figure 1 and Figure 2
See Figure 3
–0.2
1
0
2.6
0
0.2
3
V
V
Steady-state common-mode output
voltage
VOC(SS)
ΔVOC(SS)
VOC(PP)
Change in steady-state common-mode
output voltage
–0.1
0.1
Peak-to-peak common-mode output
voltage
See Figure 3
500
mV
IOZ
II
High-impedance output current
Input current
See receiver input currents
D, DE
–100
–250
100
250
µA
IOS
Short-circuit output current
−7 V ≤ VO ≤ 12 V, See Figure 7
mA
(1) All typical values are at 25°C and with a 5–V supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
700
150
12
MAX
UNIT
Propagation delay time, low-to-high-level
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
1300
500
20
tPLH
tPHL
output
RL = 54 Ω, CL = 50 pF,
See Figure 4
ns
Propagation delay time, high-to-low-level
output
500
900
200
7
1500
300
15
tr
tf
Differential output signal rise time
Differential output signal fall time
RL = 54 Ω, CL = 50 pF,
See Figure 4
ns
ns
ns
ns
ns
20
200
50
RL = 54 Ω, CL = 50 pF,
See Figure 4
tsk(p)
Pulse skew (|tPHL – tPLH|)
5
1.4
2
Propagation delay time, high-impedance-to-
high-level output
Propagation delay time, high-impedance-to-
low-level output
2500
1000
13
7000
2500
30
RL = 110 Ω, RE at 0 V,
See Figure 5 and
Figure 6
tPZH
tPZL
Propagation delay time, high-level-to-high-
impedance output
Propagation delay time, low-level-to-high-
impedance output
80
200
100
30
RL = 110 Ω, RE at 0 V,
See Figure 5 and
Figure 6
tPHZ
tPLZ
60
12
Propagation delay time, shutdown-to-high-
tPZH(SHDN) level output
tPZL(SHDN) Propagation delay time, shutdown-to-low-
level output
3500
2500
1600
7000
4500
2600
RL = 110 Ω, RE at VCC,
See Figure 5
4
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Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E
SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
www.ti.com
SLLS562G –AUGUST 2009–REVISED MAY 2009
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
Positive-going differential input threshold
voltage
VIT+
VIT-
IO = –8 mA
IO = 8 mA
–85
–10
mV
mV
Negative-going differential input threshold
voltage
–200
–115
Vhys
VOH
VOL
IOZ
Hysteresis voltage (VIT+ - VIT-
High-level output voltage
Low-level output voltage
)
30
4.6
mV
V
VID = 200 mV, IOH = –8 mA, See Figure 8
VID = –200 mV, IO = 8 mA, See Figure 8
VO = 0 or VCC, RE = VCC
VIH = 12 V, VCC = 5 V
4
0.15
0.4
1
V
High-impedance-state output current
–1
μA
0.04
0.1
VIH = 12 V, VCC = 0 V
0.06 0.125
II
Bus input current
mA
VIH = –7 V, VCC = 5 V
–0.1
–0.05
–60
–0.04
–0.03
–30
–30
7
VIH = –7 V, VCC = 0 V
IIH
High-level input current, (RE)
Low-level Input current, (RE)
Differential input capacitance
VIH = 2 V
μA
μA
pF
IIL
VIL = 0.8 V
–60
Cdiff
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
(1) All typical values are at 25°C and with a 5-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
200
100
200
100
30
UNIT
HVD3082E
HVD3085E
75
79
4
Propagation delay time, low-to-high-
level output
tPLH
tPHL
tsk(p)
ns
ns
ns
HVD3086E
HVD3082E
HVD3085E
Propagation delay time, high-to-low-
level output
CL = 15 pF, See
Figure 9
HVD3088E
HVD3082E
HVD3085E
Pulse skew (|tPHL – tPLH|)
HVD3088E
10
3
tr
tf
Output signal rise time
Output signal fall time
1.5
1.8
ns
ns
VID = –1.5 V to 1.5 V,
CL = 15 pF, See Figure 9
3
HVD3082E
HVD3085E
HVD3088E
5
10
5
50
30
tPZH
tPZL
tPHZ
tPLZ
Output enable time to high level
Output enable time to low level
Output enable time from high level
Output disable time from low level
ns
ns
ns
ns
HVD3082E
HVD3085E
50
CL = 15 pF,
DE at 3 V
See Figure 10 and
Figure 11
HVD3088E
30
HVD3082E
HVD3085E
50
HVD3088E
30
HVD3082E
HVD3085E
8
50
HVD3088E
30
Propagation delay time, shutdown-to-
high-level output
tPZH(SHDN)
tPZL(SHDN)
1600
1700
3500
ns
ns
CL = 15 pF, DE at 0 V,
See Figure 12
Propagation delay time, shutdown-to-low-
level output
3500
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SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
SLLS562G –AUGUST 2009–REVISED MAY 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION
NOTE: Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator
characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise
specified).
I
OA
A
27 W
27 W
I
I
V
OD
50 pF
0 V or 3 V
B
I
OB
V
OC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 W
I
OA
V
= -7 V to 12 V
TEST
V
60 W
375 W
OD
0 V or 3 V
I
OB
V
TEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
27 W
A
V
A
-3.25 V
-1.75 V
V
27 W
B
Signal
Generator
B
50 W
V
V
DV
OC
OC(PP)
OC(SS)
50 pF
V
OC
Figure 3. Driver VOC Test Circuit and Waveforms
3 V
1.5 V
1.5 V
Input
0 V
V
R
= 50 W
t
t
PHL
V
L
PLH
OD
C
= 50 pF
Signal
Generator
OD(H)
L
90%
10%
50 W
0 V
Output
V
OD(L)
t
t
f
r
Figure 4. Driver Switching Test Circuit and Waveforms
6
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Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E
SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
www.ti.com
SLLS562G –AUGUST 2009–REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION (continued)
A
B
S1
Output
3 V
D
0 V or 3 V
3 V if Testing A Output
0 V if Testing B Output
1.5 V
1.5 V
DE
0 V
V
0.5 V
t
R
L
= 110 W
C
= 50 pF
PZH
L
DE
OH
2.5 V
Signal
Generator
Output
V
0
50 W
Off
t
PHZ
Figure 5. Driver Enable/Disable Test Circuit and Waveforms, High Output
5 V
R
= 110 W
L
A
B
S1
C
3 V
D
Output
0 V or 3 V
0 V if Testing A Output
3 V if Testing B Output
1.5 V
1.5 V
PLZ
DE
0 V
5 V
V
t
PZL
= 50 pF
L
t
DE
Output
Signal
Generator
2.5 V
50 W
OL
0.5 V
Figure 6. Driver Enable/Disable Test Circuit and Waveforms, Low Output
I
OS
I
O
V
ID
V
O
V
O
Voltage
Source
Figure 8. Receiver Switching Test Circuit and
Waveforms
Figure 7. Driver Short-Circuit
Signal
Generator
50 W
Input B
V
ID
1.5 V
0 V
50%
I
A
B
O
Input A
R
t
t
PHL
PLH
V
O
V
Signal
Generator
OH
OL
C
= 15 pF
90%
50 W
L
Output
10%
V
t
t
f
r
Figure 9. Receiver Switching Test Circuit and Waveforms
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SN65HVD3085E, SH65HVD3088E
SLLS562G –AUGUST 2009–REVISED MAY 2009
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PARAMETER MEASUREMENT INFORMATION (continued)
D
V
V
CC
CC
DE
A
54 W
B
3 V
1 kW
RE
R
1.5 V
0 V
0 V
RE
C
= 15 pF
L
t
t
PZH
PHZ
V
Signal
Generator
OH
50 W
V
-0.5 V
OH
1.5 V
R
GND
Figure 10. Receiver Enable/Disable Test Circuit and Waveforms, Data Output High
D
0 V
DE
V
CC
A
54 W
B
3 V
0 V
1 kW
RE
R
1.5 V
PZL
5 V
C
= 15 pF
RE
L
t
t
PLZ
Signal
Generator
V
CC
50 W
R
1.5 V
V
+0.5 V
OH
V
OL
Figure 11. Receiver Enable/Disable Test Circuit and Waveforms, Data Output Low
V
CC
Switch Down for V = 1.5 V
(A)
Switch Up for V = -1.5 V
(A)
A
B
1.5 V or
-1.5 V
R
3 V
0 V
RE
1 kW
1.5 V
C
= 15 pF
L
RE
t
t
PZH(SHDN)
PZL(SHDN)
Signal
Generator
50 W
5 V
V
OH
R
1.5 V
V
OL
0 V
Figure 12. Receiver Enable From Shutdown Test Circuit and Waveforms
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SN65HVD3085E, SH65HVD3088E
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SLLS562G –AUGUST 2009–REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION (continued)
V
TEST
100 W
0 V
15 ms
Pulse Generator,
15 ms Duration,
1% Duty Cycle
15 ms
-V
TEST
Figure 13. Test Circuit and Waveforms, Transient Overvoltage Test
DEVICE INFORMATION
PIN ASSIGNMENT
LOGIC DIAGRAM (POSITIVE LOGIC)
D, P OR DGK PACKAGE
(TOP VIEW)
4
V
D
R
1
8
7
6
5
CC
B
3
2
2
3
4
RE
DE
D
DE
RE
A
GND
6
7
A
B
1
R
FUNCTION TABLE
DRIVER
RECEIVER
ENABLE
OUTPUTS
INPUT
D
INPUT
DE
DIFFERENTIAL INPUTS
VID = VA - VB
OUTPUT
RE
R
A
H
L
B
L
H
L
H
H
VID ≤ –0.2 V
L
L
?
H
Z
L
–0.2 V < VID < –0.01 V
L
X
L
Z
H
Z
–0.01 V ≤ VID
X
L
H
Z
H
H
H
Z
Open
X
H
H
Open
Z
Open circuit
Short circuit
IDLE Bus
X
L
L
L
Open
Receiver Failsafe
The differential receiver is “failsafe” to invalid bus states caused by:
•
•
•
open bus conditions such as a disconnected connector,
shorted bus conditions such as cable damage shorting the twisted-pair together, or
idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
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SLLS562G –AUGUST 2009–REVISED MAY 2009
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Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a High when the differential input VID is more positive than +200 mV, and must output a Low when
the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are
VIT+ and VIT-and VHYS. As seen in the RECEIVER ELECTRICAL CHARACTERISTICS table, differential signals
more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive
than +200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output
is High. Only when the differential input is more negative than VIT-will the receiver output transition to a Low state.
So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value
VHYS (the separation between VIT+ and VIT-) as well as the value of VIT+
.
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Input
DE Input
V
V
CC
CC
50 kW
500 W
500 W
Input
Input
50 kW
9 V
9 V
A Input
B Input
V
V
CC
CC
36 kW
36 kW
16 V
16 V
180 kW
180 kW
Input
Input
36 kW
16 V
36 kW
16 V
A and B Output
R Output
V
CC
V
CC
16 V
5 W
Output
Output
16 V
9 V
10
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Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E
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SN65HVD3085E, SH65HVD3088E
www.ti.com
SLLS562G –AUGUST 2009–REVISED MAY 2009
PACKAGE THERMAL INFORMATION
PARAMETER
TEST CONDITIONS
PACKAGE
MIN
TYP
266
210
155
180
130
70
MAX
UNIT
MOSP (DGK)
Low-k board, no air flow
SOIC (D)
°C/W
PDIP (P)
Junction-to-ambient
thermal resistance
θJA
MOSP (DGK)
SOIC (D)
High-k board, no air flow
Low-k board, no air flow
°C/W
°C/W
°C/W
PDIP (P)
MOSP (DGK)
SOIC (D)
110
55
Junction-to-board
thermal resistance
θJB
PDIP (P)
40
MOSP (DGK)
SOIC (D)
66
Junction-to-case
thermal resistance
θJC
80
PDIP (P)
80
Input to D is a 50% duty
cycle square wave at max
rec'd signal rate
RL = 54 Ω VCC = 5.5 V, TJ =
130°C
ALL HVD3082E
ALL HVD3085E
203
205
Average power
dissipation
P(AVG)
mW
°C
ALL HVD3088E
ALL
276
Thermal shut-down
junction temperature
TSD
165
TYPICAL CHARACTERISTICS
SN65HVD3082E
RMS SUPPLY CURRENT
vs
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
SIGNALING RATE
80
60
10
No Load,
= 5 V,
V
CC
= 25oC
T
A
50% Square Wave Input
40
20
0
Driver and Receiver
V
= 0 V
CC
1
V
= 5 V
CC
-20
Receiver Only
-40
-60
0.1
-8
-6 -4 -2
0
2
4
6
8
10 12
1
10
100
Signal Rate - kbps
V - Bus Input Voltage - V
I
Figure 14.
Figure 15.
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SLLS562G –AUGUST 2009–REVISED MAY 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SN65HVD3085E
RMS SUPPLY CURRENT
vs
SN65HVD3088E
RMS SUPPLY CURRENT
vs
SIGNALING RATE
SIGNAL RATE
100
100
No Load,
= 5 V,
No Load,
= 5 V,
V
CC
= 25oC
V
CC
= 25oC
T
A
50% Square Wave Input
T
A
50% Square Wave Input
10
10
Driver and Receiver
Driver and Receiver
1
1
Receiver Only
Receiver Only
0.1
0.1
1
10
100
1000
Signal Rate - kbps
Figure 16.
Figure 17.
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
vs
DRIVER OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
5
5
= 25oC
= 5 V
T
= 25oC
T
A
A
4.5
4.5
V
V
= 5 V
V
CC
= 0.75 V
CC
R
= 120W
L
IC
4
4
3.5
3.5
3
3
R
= 60W
L
2.5
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
0
10
20
30
40
50
-200 -180 -160 -140 -120 -100 -80 -60 -40 -20
0
I
- Differential Output Current - mA
V
- Differential Input Voltage - V
ID
O
Figure 18.
Figure 19.
12
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www.ti.com
SLLS562G –AUGUST 2009–REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)
SN65HVD3088E
DRIVER RISE/FALL TIME
vs
TEMPERATURE
10
9
V
= 4.5 V
CC
8
7
6
5
V
= 5 V
CC
V
= 5.5 V
CC
-40
-20
0
20
40
60
80
T
- Temperature - oC
A
Figure 20.
APPLICATION INFORMATION
R
T
R
T
Note: The line should be terminated at both ends with its characteristic impedance (RT = ZO).
Note: Stub lengths off the main line should be kept as short as possible.
Figure 21. Typical Application Circuit
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SLLS562G –AUGUST 2009–REVISED MAY 2009
www.ti.com
POWER USAGE IN AN RS-485 TRANSCEIVER
Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well
as to the transceiver circuitry. For a typical RS–485 bus configuration, the load that an active driver must drive
consists of all of the receiving nodes, plus the termination resistors at each end of the bus.
The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A
standard defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current
supplied to all receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown
in , the bus input current is less than 1/8 mA, allowing up to 256 nodes on a single bus.
The current in the termination resistors depends on the differential bus voltage. The standard requires active
drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at
each end, this sums to 25 mA differential output current whenever the bus is active. Typically the HVD308xE can
drive more than 25 mA to a 60 Ω load, resulting in a differential output voltage higher than the minimum required
by the standard. (See Figure 16.)
Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by
the transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled,
and only 0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode,
neither the driver nor receiver is active, and the supply current is low.
Supply current increases with signaling rate primarily due to the totum pole outputs of the driver (see Figure 15).
When these outputs change state, there is a moment when both the high-side and low-side output transistors are
conducting and this creates a short spike in the supply current. As the frequency of state changes increases,
more power is used.
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against
inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode,
most internal circuitry is powered down, and the supply current is typically 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open
when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe
feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching
characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation
section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
14
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SLLS562G –AUGUST 2009–REVISED MAY 2009
THERMAL CHARACTERISTICS OF IC PACKAGES
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is NOT a constant and is a strong function of:
•
•
•
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board
gives best case in–use condition and consists of two 1–oz buried power planes with a single trace layer 25 mm
long with 2-oz thick copper. A 4% to 50% difference in θJA can be measured between these two test cards.
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force
heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to
predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-
standard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of
package system (see Figure 22).
Ambient Node
q
Calculated
CA
Surface Node
Calculated/Measured
q
JC
Junction
Calculated/Measured
q
JB
PC Board
Figure 22. Thermal Resistance
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SLLS562G –AUGUST 2009–REVISED MAY 2009
www.ti.com
REVISION HISTORY
Changes from Revision F (March 2009) to Revision G
Page
•
•
•
Added IDLE Bus to the Function Table ................................................................................................................................ 9
Added Receiver Failsafe section .......................................................................................................................................... 9
Added Graph - DRIVER RISE/FALL TIME vs TEMPERATURE ........................................................................................ 13
16
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN65HVD3082ED
SN65HVD3082EDG4
SN65HVD3082EDGK
SN65HVD3082EDGKR
SN65HVD3082EDR
SN65HVD3082EDRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
8
8
8
8
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
VSSOP
VSSOP
SOIC
DGK
DGK
D
80
Green (RoHS
& no Sb/Br)
2500
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SN65HVD3082EP
SN65HVD3082EPE4
SN65HVD3085ED
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
SOIC
P
P
D
8
8
8
50
50
75
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
SN65HVD3085EDG4
SN65HVD3085EDGK
SN65HVD3085EDGKG4
SN65HVD3085EDGKR
SN65HVD3085EDGKRG4
SN65HVD3085EDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
D
DGK
DGK
DGK
DGK
D
8
8
8
8
8
8
8
8
8
75
80
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN65HVD3085EDRG4
SN65HVD3088ED
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SN65HVD3088EDG4
SOIC
D
75
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN65HVD3088EDGK
SN65HVD3088EDGKG4
SN65HVD3088EDGKR
SN65HVD3088EDGKRG4
SN65HVD3088EDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
80
80
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN65HVD3088EDRG4
SN75HVD3082ED
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SN75HVD3082EDG4
SN75HVD3082EDGK
SN75HVD3082EDGKG4
SN75HVD3082EDGKR
SN75HVD3082EDGKRG4
SN75HVD3082EDR
SOIC
D
75
Green (RoHS
& no Sb/Br)
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN75HVD3082EDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
SN75HVD3082EP
SN75HVD3082EPE4
SNHVD3082EDGKG4
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
P
P
8
8
8
50
50
80
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
VSSOP
DGK
Green (RoHS
& no Sb/Br)
SNHVD3082EDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD3082EDGKR VSSOP
SN65HVD3082EDR SOIC
SN65HVD3085EDGKR VSSOP
SN65HVD3085EDR SOIC
SN65HVD3088EDGKR VSSOP
SN65HVD3088EDR SOIC
SN75HVD3082EDGKR VSSOP
SN75HVD3082EDR SOIC
DGK
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
6.4
5.3
6.4
5.3
6.4
5.3
6.4
3.4
5.2
3.4
5.2
3.4
5.2
3.4
5.2
1.4
2.1
1.4
2.1
1.4
2.1
1.4
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
DGK
D
DGK
D
DGK
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65HVD3082EDGKR
SN65HVD3082EDR
SN65HVD3085EDGKR
SN65HVD3085EDR
SN65HVD3088EDGKR
SN65HVD3088EDR
SN75HVD3082EDGKR
SN75HVD3082EDR
VSSOP
SOIC
DGK
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
367.0
340.5
367.0
340.5
367.0
340.5
367.0
340.5
367.0
338.1
367.0
338.1
367.0
338.1
367.0
338.1
35.0
20.6
35.0
20.6
35.0
20.6
35.0
20.6
VSSOP
SOIC
DGK
D
VSSOP
SOIC
DGK
D
VSSOP
SOIC
DGK
D
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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