SN65HVD3088EDGKR [TI]
LOW-POWER RS-485 TRANSCEIVER; 低功耗RS - 485收发器
| 型号： | SN65HVD3088EDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-POWER RS-485 TRANSCEIVER |
| 文件： | 总23页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DGK
D
P
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
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FEATURES
DESCRIPTION
These devices are half-duplex transceivers designed for
RS-485 data bus networks. Powered by a 5-V supply, they
are fully compliant with TIA/EIA-485A standard. With
controlled transition times, these devices are suitable for
transmitting data over long twisted-pair cables.
SN65HVD3082E and SN75HVD3082E devices are
optimized for signaling rates up to 200 kbps.
SN65HVD3085E is suitable for data transmission up to 1
Mbps, whereas SN65HVD3088E is suitable for
applications requiring signaling rates up to 20 Mbps.
These devices are designed to operate with very low
supply current, typically 0.3 mA, exclusive of the load.
When in the inactive shutdown mode, the supply current
drops to a few nanoamps, making these devices ideal for
power-sensitive applications.
D
Available in Small MSOP-8 Package
D
Meets or Exceeds the Requirements of the
TIA/EIA−485A Standard
D
Low Quiescent Power
− 0.3 mA Active Mode
− 1 nA Shutdown Mode
D
D
D
D
1/8 Unit Load—Up to 256 Nodes on a Bus
Bus-Pin ESD Protection Up to 15 kV
Industry-Standard SN75176 Footprint
Failsafe Receiver
(Bus Open, Bus Shorted, Bus Idle)
D
Glitch−Free Power−Up/Down Bus Inputs and
Outputs
The wide common-mode range and high ESD protection
levels of these devices make them suitable for demanding
applications such as energy meter networks, electrical
inverters, status/command signals across telecom racks,
cabled chassis interconnects, and industrial automation
networks where noise tolerance is essential. These
devices match the industry-standard footprint of SN75176.
Power-on reset circuits keep the outputs in a high-
impedance state until the supply voltage has stabilized. A
thermal shutdown function protects the device from
damage due to system fault conditions. The
SN75HVD3082E is characterized for operation from 0°C
to 70°C and SN65HVD308xE are characterized for
operation from −40°C to 85°C air temperature.
APPLICATIONS
D
D
D
D
D
D
D
Energy Meter Networks
Motor Control
Power Inverters
Industrial Automation
Building Automation Networks
Battery-Powered Applications
Telecommunications Equipment
ORDERING INFORMATION
PACKAGE TYPE
SIGNALING RATE
T
A
(1)
D
(2)
DGK
(Mbps)
P
SN75HVD3082EP
Marked as 75HVD3082
SN75HVD3082ED
Marked as VN3082
SN75HVD3082EDGK
Marked as NWM
0°C to 70°C
0.2
SN65HVD3082EP
Marked as 65HVD3082
SN65HVD3082ED
Marked as VP3082
SN65HVD3082EDGK
Marked as NWN
0.2
1
SN65HVD3085ED
Marked as VP3085
SN65HVD3085EDGK
Marked as NWK
−40°C to 85°C
SN65HVD3088ED
Marked as VP3088
SN65HVD3088EDGK
Marked as NWH
20
(1)
(2)
The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDR).
The DGK package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDGKR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004 − 2005, Texas Instruments Incorporated
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SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range unless otherwise noted
UNITS
Supply voltage range, V
Voltage range at A or B
−0.5 V to 7 V
−9 V to 14 V
CC
Voltage range at any logic pin
Receiver output current
−0.3 V to V
+ 0.3 V
CC
−24 mA to 24 mA
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 13)
Junction temperature, T
−50 V to 50 V
170°C
J
Continuous total power dissipation
Refer to Package Dissipation Table
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under recommendedoperating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
(3)
DERATING FACTOR
T
<25°C
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
JEDEC BOARD MODEL
POWER RATING
ABOVE T = 25°C
POWER RATING
A
(1)
Low k
507 mW
4.82 mW/°C
7.85 mW/°C
6.53 mW/°C
3.76 mW/°C
5.55 mW/°C
289 mW
217 mW
D
P
(2)
High k
824 mW
471 mW
353 mW
(1)
Low k
686 mW
392 mW
294 mW
(1)
Low k
394 mW
255 mW
169 mW
DGK
(2)
High k
583 mW
333 mW
250 mW
(1)
(2)
(3)
In accordance with the low-k thermal metric definitions of EIA/JESD51-3
In accordance with the high-k thermal metric definitions of EIA/JESDS1-7
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
2
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SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
RECOMMENDED OPERATING CONDITIONS(1)
MIN
4.5
−7
2
TYP
MAX
5.5
UNIT
Supply voltage, V
CC
V
V
V
V
V
Input voltage at any bus terminal (separately or common mode), V
12
I
High-level input voltage (D, DE, or RE inputs), V
IH
V
CC
0.8
Low-level input voltage (D, DE, or RE inputs), V
IL
0
Differential input voltage, V
ID
−12
−60
−8
54
12
60
8
Driver
Output current, I
mA
O
Receiver
Differential load resistance, R
60
Ω
L
SN65HVD3082E, SN75HVD3082E
SN65HVD3085E
0.2
1
Signaling rate, 1/t
UI
Mbps
SN65HVD3088E
20
85
70
SN65HVD3082E, SN65HVD3085E, SN65HVD3088E
SN75HVD3082E
−40
0
Operating free−air temperature, T
°C
°C
A
(2)
Junction temperature, T
−40
130
J
(1)
(2)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
See thermal characteristics table for information on maintenance of this specification for the DGK package.
SUPPLY CURRENT
over recommended operating conditions unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
or open, DE at V , RE at 0 V, No load
MAX
900
600
600
2
UNIT
µA
Driver and receiver enabled
D at V
D at V
D at V
D at V
425
330
CC
CC
CC
CC
CC
Driver enabled, receiver disabled
Receiver enabled, driver disabled
Driver and receiver disabled
or open, DE at V , RE at V
No load
µA
CC CC,
I
CC
or open, DE at 0 V, RE at 0 V, No load
300
µA
or open, DE at 0 V, RE at V
0.001
µA
CC
(1)
All typical values are at 25°C and with a 5-V supply.
ELECTROSTATIC DISCHARGE PROTECTION
(1)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
kV
Human body model
Human body model
Bus terminals and GND
15
4
(2)
All pins
All pins
kV
(3)
Charged-device-model
1
kV
(1)
(2)
(3)
All typical values at 25°C
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
3
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SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
= 0, No load
MAX
UNIT
I
3
1.5
2
4.3
2.3
O
R
= 54 Ω, See Figure 1
= 100 Ω
L
V
OD
Differential output voltage
V
V
R
L
V
= −7 V to 12 V, See Figure 2
1.5
−0.2
1
TEST
∆V
OD
Change in magnitude of differential output voltage
Steady-state common-mode output voltage
See Figure 1 and Figure 2
0
2.6
0
0.2
3
V
OC(SS)
∆V
See Figure 3
V
Change in steady-state common-mode output voltage
−0.1
0.1
OC(SS)
V
See Figure 3
500
mV
OC(PP)
I
I
I
High-impedance output current
Input current
See receiver input currents
D, DE
OZ
µA
−100
−250
100
250
I
Short-circuit output current
−7 V ≤ V ≤ 12 V, See Figure 7
mA
OS
O
(1)
All typical values are at 25°C and with a 5V-supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
700
150
12
MAX
1300
500
20
UNIT
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
HVD3082E
HVD3085E
HVD3088E
R
C
= 54 Ω,
= 50 pF,
See Figure 4
L
L
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
PLH
PHL
ns
500
900
200
7
1500
300
15
R
L
C
L
= 54 Ω,
= 50 pF,
See Figure 4
t
r
t
f
Differential output signal rise time
Differential output signal fall time
ns
ns
ns
20
200
50
R
L
C
L
= 54 Ω,
= 50 pF,
See Figure 4
5
t
Pulse skew ( |t | )
- t
sk(p)
PHL PLH
1.4
5
2500 7000
1000 2500
R
L
= 110 Ω,
RE at 0 V,
See Figure 5
and Figure 6
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low−level output
t
t
PZH
PZL
13
80
60
12
30
200
100
30
R
L
= 110 Ω,
RE at 0 V,
See Figure 5
and Figure 6
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
t
t
PHZ
PLZ
ns
ns
3500 7000
2500 4500
1600 2600
R
at V
= 110 Ω, RE
L
Propagation delay time, shutdown-to-high-level output
t
t
PZH(SHDN)
,
CC
PZL(SHDN) Propagation delay time, shutdown-to-low-level output
See Figure 5
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SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
mV
mV
mV
V
V
IT+
V
IT−
V
hys
V
OH
V
OL
Positive-going input threshold voltage
Negative-going input threshold voltage
I
I
= −8 mA
= 8 mA
−85
−10
O
−200
4
−115
30
O
Hysteresis voltage (V
IT+
− V )
IT−
High-level output voltage
Low-level output voltage
V
V
V
V
V
V
V
V
V
= 200 mV, I
OH
= −8 mA, See Figure 8
= 8 mA, See Figure 8
4.6
ID
ID
O
= −200 mV, I
OH
0.15
0.4
1
V
I
High-impedance-state output current
= 0 to V , RE= V
CC CC
−1
µA
OZ
= 12 V, V
= 12 V, V
= −7 V, V
= −7 V, V
= 2 V
= 5 V
= 0
0.04
0.1
IH
IH
IH
IH
IH
IL
CC
CC
CC
CC
0.06 0.125
I
I
Bus input current
mA
= 5 V
= 0
−0.1
−0.05
−60
−0.04
−0.03
−30
−30
7
I
I
High-level input current (RE)
Low-level input current (RE)
Differential input capacitance
µA
µA
pF
IH
= 0.8 V
−60
IL
C
diff
V = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
I
(1)
All typical values are at 25°C and with a 5-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
200
100
200
100
30
UNIT
HVD3082E
HVD3085E
75
79
4
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
ns
ns
ns
PLH
PHL
sk(p)
HVD3088E
HVD3082E
C
L
= 15 pF,
See Figure 9
HVD3085E
HVD3088E
HVD3082E
HVD3085E
Pulse skew ( |t | )
− t
PHL PLH
HVD3088E
10
3
t
t
Output signal rise time
Output signal fall time
1.5
1.8
ns
ns
r
V
C
= −1.5 V to 1.5 V,
= 15 pF, See Figure 9
ID
3
L
L
f
HVD3082E
HVD3085E
5
50
30
50
30
t
t
t
t
Output enable time to high level
Output enable time to low level
Output enable time from high level
Output enable time from low level
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
HVD3088E
HVD3082E
HVD3085E
10
C
= 15 pF,
HVD3088E
DE at 3 V,
See Figure 10
and Figure 11
HVD3082E
HVD3085E
5
8
50
30
50
HVD3088E
HVD3082E
HVD3085E
HVD3088E
30
3500
3500
t
t
Propagation delay time, shutdown-to-high-level output
Propagation delay time, shutdown-to-low-level output
1600
1700
ns
ns
PZH(SHDN)
C = 15 pF, DE at 0 V,
L
See Figure 12
PZL(SHDN)
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PARAMETER MEASUREMENT INFORMATION
NOTE:Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and
fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. Z = 50 Ω (unless otherwise specified).
O
I
A
B
OA
OB
27 Ω
27 Ω
I
I
V
OD
50 pF
0 V or 3 V
D
I
V
OC
Figure 1. Driver Test Circuit, V
and V
Without Common-Mode Loading
OC
OD
375 Ω
I
I
OA
V
= −7 V to 12 V
TEST
V
OD
60 Ω
375 Ω
0 V or 3 V
OB
V
TEST
Figure 2. Driver Test Circuit, V
With Common-Mode Loading
OD
27 Ω
A
V
A
≈3.25 V
≈1.75 V
D
27 Ω
V
B
Signal
Generator
B
50 Ω
V
V
OC
∆V
OC(PP)
OC(SS)
50 pF
V
OC
Figure 3. Driver V
Test Circuit and Waveforms
OC
3 V
0 V
INPUT
t
1.5 V
1.5 V
V
OD
R
L
= 54 Ω
t
PLH
PHL
C
L
= 50 pF
V
OD(H)
OD(L)
Signal
Generator
90%
10%
50 Ω
0 V
OUTPUT
V
t
r
t
f
Figure 4. Driver Switching Test Circuit and Waveforms
6
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A
B
S1
3 V
Output
R
D
0 V or 3 V
1.5 V 1.5 V
DE
3 V if Testing A Output
0 V if Testing B Output
0 V
0.5 V
C
= 50 pF
t
L
PZH
= 110 Ω
L
DE
V
OH
Output
Signal
Generator
2.5 V
50 Ω
V
Off
0
t
PHZ
Figure 5. Driver Enable/Disable Test Circuit and Waveforms, High Output
5 V
R
L
= 110 Ω
A
B
S1
3 V
D
Output
0 V or 3 V
1.5 V 1.5 V
DE
t
0 V if Testing A Output
3 V if Testing B Output
0 V
5 V
C
L
= 50 pF
PZL
t
DE
PLZ
Output
Signal
Generator
2.5 V
V
OL
50 Ω
0.5 V
Figure 6. Driver Enable/Disable Test Circuit and Waveforms, Low Output
I
OS
I
O
V
O
V
ID
Voltage
Source
V
O
Figure 7. Driver Short-Circuit Test
Figure 8. Receiver Parameter Definitions
Signal
Generator
50 Ω
Input B
V
ID
1.5 V
0 V
A
B
50%
I
O
Input A
t
R
t
PHL
PLH
V
C
= 15 pF
O
V
OH
Signal
Generator
L
90%
50 Ω
Output
1.5 V
10%
V
OL
t
r
t
f
Figure 9. Receiver Switching Test Circuit and Waveforms
7
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊꢋ ꢌ ꢀ ꢁꢍ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢋ
ꢃ
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢆ
ꢇ
ꢈꢉ
ꢃꢋ
ꢌ
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉꢉ
ꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
D
V
V
CC
DE
CC
A
54 Ω
B
3 V
0 V
1 kΩ
R
RE
1.5 V
0 V
C
L
= 15 pF
RE
t
t
PHZ
PZH
Signal
Generator
V
OH
−0.5 V
50 Ω
V
OH
1.5 V
R
GND
Figure 10. Receiver Enable/Disable Test Circuit and Waveforms, Data Output High
D
0 V
DE
V
CC
A
54 Ω
B
3 V
0 V
1 kΩ
R
RE
1.5 V
PZL
5 V
C
L
= 15 pF
RE
t
t
PLZ
Signal
Generator
V
CC
50 Ω
1.5 V
R
V
OL
+0.5 V
V
OL
Figure 11. Receiver Enable/Disable Test Circuit and Waveforms, Data Output Low
V
CC
Switch Down for V
= 1.5 V,
(A)
= −1.5 V
Switch Up for V
(A)
A
B
1.5 V or
−1.5 V
R
3 V
1 kΩ
1.5 V
RE
C
L
= 15 pF
0 V
RE
t
t
PZH(SHDN)
PZL(SHDN)
Signal
Generator
50 Ω
5 V
R
V
V
OH
1.5 V
OL
0 V
Figure 12. Receiver Enable From Shutdown Test Circuit and Waveforms
8
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊꢋ ꢌ ꢀꢁꢍ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋ
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢃꢋ ꢌ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
V
TEST
100 Ω
0 V
Pulse Generator,
15 µs Duration,
1% Duty Cycle
1.5 ms
15 µs
−V
TEST
Figure 13. Test Circuit and Waveforms, Transient Over-Voltage Test
DEVICE INFORMATION
PIN ASSIGNMENTS
LOGIC DIAGRAM (POSITIVE LOGIC)
D, P OR DGK PACKAGE
(TOP VIEW)
4
D
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
3
CC
DE
RE
2
6
A
1
GND
R
7
B
FUNCTION TABLE
DRIVER
RECEIVER
OUTPUTS
INPUT
D
ENABLE
DE
DIFFERENTIAL INPUTS
= V – V
ENABLE
RE
OUTPUT
R
V
ID
A
H
L
B
L
A
B
H
L
H
H
V
≤ −0.2 V
L
L
?
ID
−0.2 V < V < −0.01 V
H
Z
L
L
ID
X
L
Z
H
Z
−0.01 V ≤ V
L
H
H
Z
H
H
Z
ID
Open
X
H
X
Open
Z
Open circuit
Short circuit
X
L
L
Open
:
NOTE H= high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
9
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊꢋ ꢌ ꢀ ꢁꢍ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢋ
ꢃ
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢆ
ꢇ
ꢈꢉ
ꢃꢋ
ꢌ
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉꢉ
ꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Input
DE Input
V
CC
V
CC
50 kΩ
500 ꢀ
500 ꢀ
Input
Input
50 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
16 V
16 V
180 kΩ
36 kΩ
36 kΩ
180 k Ω
Input
Input
36 kΩ
16 V
16 V
36 kΩ
A and B Outputs
R Outputs
V
CC
V
CC
16 V
5 Ω
Output
Output
16 V
9 V
10
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊꢋ ꢌ ꢀꢁꢍ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋ
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢃꢋ ꢌ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
DGK Package
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
Low-k board, no air flow
MIN
TYP
266
MAX
UNIT
(2)
(1)
Θ
JA
Junction-to-ambient thermal resistance
°C/W
(3)
High-k board, no air flow
180
108
66
(3)
Θ
Θ
Junction-to-board thermal resistance
Junction-to-case thermal resistance
High-k board, no air flow
JB
°C/W
JC
R
= 54 Ω, Input to D is a 200 kbps
L
50% duty cycle square wave
P
P
P
Average power dissipation
Average power dissipation
HVD3082E
HVD3085E
HVD3088E
203
205
276
mW
(AVG)
(AVG)
(AVG)
V
at 5.5 V, T = 130°C
cc
J
R
= 54 Ω, Input to D is a 1 Mbps
L
50% duty cycle square wave
mW
mW
V
cc
at 5.5 V, T = 130°C
J
R
= 54 Ω, Input to D is a 20 Mbps
L
Average power dissipation
Ambient air temperature
50% duty cycle square wave
at 5.5 V, T = 130°C
V
cc
J
High k board model
Low k board model
−40
−40
93
75
T
A
°C
°C
T
SD
Thermal shut-down junction temperature
165
(1)
(2)
(3)
See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
11
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊꢋ ꢌ ꢀ ꢁꢍ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢋ
ꢃ
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢆ
ꢇ
ꢈꢉ
ꢃꢋ
ꢌ
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉꢉ
ꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
SN65HVD3082E
RMS SUPPLY CURRENT
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
vs
SIGNALING RATE
80
60
10
No Load,
= 5 V
T
A
V
CC
= 25°C
50% Square wave input
40
20
0
Driver and Receiver
V
CC
= 0 V
1
V
CC
= 5 V
−20
Receiver Only
−40
−60
0.1
−8 −6 −4 −2
0
2
4
6
8
10 12
1
10
100
V − Bus Input Voltage − V
I
Signaling Rate − kbps
Figure 14
Figure 15
SN65HVD3085E
RMS SUPPLY CURRENT
vs
SN65HVD3088E
RMS SUPPLY CURRENT
vs
SIGNALING RATE
SIGNALING RATE
100
10
100
10
1
No Load,
= 5 V
No Load,
= 5 V
V
CC
= 25°C
V
CC
= 25°C
T
A
T
A
50% Square wave input
50% Square wave input
Driver and Receiver
Driver and Receiver
1
Receiver Only
Receiver Only
0.1
0.1
0.001
10
100
1000
1
0.010
0.100
1
10
100
Signaling Rate − kbps
Signaling Rate − Mbps
Figure 17
Figure 16
12
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊꢋ ꢌ ꢀꢁꢍ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋ
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢃꢋ ꢌ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
vs
DIFFERENTIAL OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
5
5
T
V
= 25°C
T
V
V
= 25°C
A
A
4.5
4.5
= 5 V
= 5 V
= 0.75 V
CC
CC
R
L
= 120Ω
IC
4
4
3.5
3.5
3
3
R
L
= 60Ω
2.5
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
−200−180−160 −140−120−100 −80 −60 −40 −20
0
0
10
20
30
40
50
V
ID
− Differential Input Voltage − V
I
O
− Differential Output Current − mA
Figure 18
Figure 19
13
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊꢋ ꢌ ꢀ ꢁꢍ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢋ
ꢃ
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢆ
ꢇ
ꢈꢉ
ꢃꢋ
ꢌ
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉꢉ
ꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
APPLICATION INFORMATION
R
T
R
T
:
NOTE The line should be terminated at both ends with its characteristic impedance (R = Z ).
T
O
Stub lengths off the main line should be kept as short as possible.
Figure 20. Typical Application Circuit
POWER USAGE IN AN RS-485 TRANSCEIVER
Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the
transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the
receiving nodes, plus the termination resistors at each end of the bus.
The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard
defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current supplied to all
receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown in Figure 14, the bus input
current is less than 1/8 mA, allowing up to 256 nodes on a single bus.
The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to
produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at each end, this sums
to 25 mA differential output current whenever the bus is active. Typically the HVD308xE can drive more than 25 mA to a
60 Ω load, resulting in a differential output voltage higher than the minimum required by the standard. (See Figure 16.)
Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by the
transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled, and only
0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode, neither the driver nor
receiver is active, and the supply current is very low.
Supply current increases with signaling rate primarily due to the totum pole outputs of the driver (see Figure 15). When
these outputs change state, there is a moment when both the high-side and low-side output transistors are conducting and
this creates a short spike in the supply current. As the frequency of state changes increases, more power is used.
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the enable inputs
are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against inadvertently entering
shutdown mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the
device is assured to be in shutdown mode. In this low-power shutdown mode, most internal circuitry is powered down, and
the supply current is typically 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable
times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open when the driver is
enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs
(A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching characteristics. If there is no
valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus
inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the
inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid.
14
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊꢋ ꢌ ꢀꢁꢍ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋ
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢃꢋ ꢌ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢉꢋ
www.ti.com
SLLS562D − MARCH 2003 − REVISED SEPTEMBER 2005
THERMAL CHARACTERISTICS OF IC PACKAGES
Θ
JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature
divided by the operating power
Θ
D
D
D
Θ
JA is NOT a constant and is a strong function of
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures.
installations.
is often misused when it is used to calculate junction temperatures for other
Θ
JA
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
Θ
JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is
only defined for the high-k test card.
Θ
JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 21).
Ambient Node
ꢁ
Calculated
CA
Surface Node
Calculated/Measured
ꢁ
JC
Junction
Calculated/Measured
ꢁ
JB
PC Board
Figure 21. Thermal Resistance
15
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
SN65HVD3082ED
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD3082EDG4
SN65HVD3082EDGK
SN65HVD3082EDGKR
SN65HVD3082EDR
SN65HVD3082EDRG4
SN65HVD3082EP
SOIC
MSOP
MSOP
SOIC
SOIC
PDIP
D
DGK
DGK
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD3082EPE4
SN65HVD3085ED
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
SOIC
SOIC
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
SOIC
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD3085EDG4
SN65HVD3085EDGK
SN65HVD3085EDGKG4
SN65HVD3085EDGKR
SN65HVD3085EDGKRG4
SN65HVD3085EDR
SN65HVD3085EDRG4
SN65HVD3088ED
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
DGK
DGK
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD3088EDG4
SN65HVD3088EDGK
SN65HVD3088EDGKG4
SN65HVD3088EDGKR
SN65HVD3088EDGKRG4
SN65HVD3088EDR
SN65HVD3088EDRG4
SN75HVD3082ED
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
DGK
DGK
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
Orderable Device
SN75HVD3082EDG4
SN75HVD3082EDGK
SN75HVD3082EDGKG4
SN75HVD3082EDGKR
SN75HVD3082EDGKRG4
SN75HVD3082EDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP
MSOP
MSOP
MSOP
SOIC
DGK
DGK
DGK
DGK
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75HVD3082EDRG4
SN75HVD3082EP
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD3082EPE4
SNHVD3082EDGKG4
SNHVD3082EDGKRG4
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
MSOP
MSOP
DGK
DGK
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
330
(mm)
12
SN65HVD3082EDGKR
SN65HVD3082EDR
SN65HVD3085EDGKR
SN65HVD3085EDR
SN65HVD3088EDGKR
SN65HVD3088EDR
SN75HVD3082EDGKR
SN75HVD3082EDR
DGK
D
8
8
8
8
8
8
8
8
SITE 60
SITE 27
SITE 60
SITE 27
SITE 60
SITE 27
SITE 60
SITE 27
5.3
6.4
5.3
6.4
5.3
6.4
5.3
6.4
3.4
5.2
3.4
5.2
3.4
5.2
3.4
5.2
1.4
2.1
1.4
2.1
1.4
2.1
1.4
2.1
8
8
8
8
8
8
8
8
12
12
12
12
12
12
12
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
12
DGK
D
12
12
DGK
D
12
12
DGK
D
12
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65HVD3082EDGKR
SN65HVD3082EDR
SN65HVD3085EDGKR
SN65HVD3085EDR
SN65HVD3088EDGKR
SN65HVD3088EDR
SN75HVD3082EDGKR
SN75HVD3082EDR
DGK
D
8
8
8
8
8
8
8
8
SITE 60
SITE 27
SITE 60
SITE 27
SITE 60
SITE 27
SITE 60
SITE 27
346.0
342.9
346.0
342.9
346.0
342.9
346.0
342.9
346.0
338.1
346.0
338.1
346.0
338.1
346.0
338.1
29.0
20.64
29.0
DGK
D
20.64
29.0
DGK
D
20.64
29.0
DGK
D
20.64
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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