SN65HVD33MDREPG4 [TI]
3.3-V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS; 3.3 -V全双工RS - 485驱动器和接收
| 型号： | SN65HVD33MDREPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS |
| 文件： | 总25页 (文件大小：853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
3.3-V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS
Check for Samples: SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP, SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
1
FEATURES
APPLICATIONS
•
1/8 Unit-Load Option Available (up to 256
Nodes on the Bus)
•
•
•
•
Utility Meters
DTE/DCE Interfaces
•
•
Bus-Pin ESD Protection Exceeds 15-kV HBM
Industrial, Process, and Building Automation
Point-of-Sale (POS) Terminals and Networks
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 5 Mbps, and
25 Mbps
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
Low-Current Standby Mode: <1 μA
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
•
•
•
•
5-V-Tolerant Inputs
Bus Idle, Open, and Short-Circuit Fail Safe
Driver Current Limiting and Thermal Shutdown
Available in Military (–55°C/125°C)
Temperature Range
Meet or Exceed the Requirements of ANSI
TIA/EIA-485-A and RS-422 Compatible
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
DESCRIPTION
The SN65HVD3x devices are 3-state differential line drivers and differential-input line receivers that operate with
3.3-V power supply.
Each driver and receiver has separate input and output pins for full-duplex bus communication designs. They are
designed for balanced transmission lines and interoperation with ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11,
and ISO 8482:1993 standard-compliant devices.
The SN65HVD30, SN65HVD31, and SN65HVD32 are fully enabled with no external enabling pins.
The SN65HVD33, SN65HVD34, and SN65HVD35 have active-high driver enables and active-low receiver
enables. A low (less than 1 μA) standby current can be achieved by disabling both the driver and receiver.
All devices are characterized for operation from –55°C to 125°C.
IMPROVED REPLACEMENT FOR:
Part Number
Replace With
xxx3491
xxx3490
SN65HVD33:
SN65HVD30:
Better ESD protection (15 kV vs 2 kV or not specified), higher signaling rate (25 Mbps vs 20 Mbps),
fractional unit load (64 nodes vs 32)
MAX3491E
MAX3490E
SN65HVD33:
SN65HVD30:
Higher signaling rate (25 Mbps vs 12 Mbps), fractional unit load (64 nodes vs 32)
Higher signaling rate (25 Mbps vs 16 Mbps), lower standby current (1 μA vs 10 μA)
Higher signaling rate (5 Mbps vs 500 kbps), lower standby current (1 μA vs 10 μA)
Higher signaling rate (1 Mbps vs 250 kbps), lower standby current (1 μA vs 10 μA)
MAX3076E
MAX3077E
SN65HVD33:
SN65HVD30:
MAX3073E
MAX3074E
SN65HVD34:
SN65HVD31:
MAX3070E
MAX3071E
SN65HVD35:
SN65HVD32:
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
xxx
SN65HVD30, SN65HVD31, SN65HVD32
SN65HVD33, SN65HVD34, SN65HVD35
D PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
VCC
R
1
2
3
4
8
7
6
5
A
B
Z
Y
NC
R
VCC
VCC
A
1
2
3
4
5
6
7
14
13
12
11
10
9
D
RE
GND
DE
B
D
Z
GND
GND
Y
8
7
2
A
8
NC
R
B
NC - No internal connection
5
6
3
Y
Z
D
2
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Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
AVAILABLE OPTIONS(1)
BASE
PART NUMBER
SIGNALING
RATE
RECEIVER
EQUALIZATION
UNIT LOADS
ENABLES
SOIC MARKING
SN65HVD30MDREP
SN65HVD31MDREP(2)
SN65HVD32MDREP(2)
SN65HVD33MDREP
SN65HVD34MDREP(2)
SN65HVD35MDREP(2)
25 Mbps
5 Mbps
1 Mbps
25 Mbps
5 Mbps
1 Mbps
1/2
1/8
1/8
1/2
1/8
1/8
No
No
No
No
No
No
No
No
HVD30EP
PREVIEW
PREVIEW
HVD33EP
PREVIEW
PREVIEW
No
Yes
Yes
Yes
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Product Preview
Absolute Maximum Ratings(1) (2)
over operating free-air temperature range (unless otherwise noted)
UNIT
VCC
Supply voltage range
–0.3 V to 6 V
–9 V to 14 V
–50 V to 50 V
–0.5 V to 7 V
Internally limited(4)
11 mA
V(A), V(B), V(Y), V(Z)
Voltage range at any bus terminal (A, B, Y, Z)
Voltage input, transient pulse through 100 Ω (see Figure 12) (A, B, Y, Z)(3)
Input voltage range (D, DE, RE)
V(TRANS)
VI
PD(cont)
IO
Continuous total power dissipation
Output current (receiver output only, R)
Junction temperature
TJ
165°C
TSTG
Storage temperature range
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) This tests survivability only and the output state of the receiver is not specified.
(4) The thermal shutdown protection circuit internally limits the continuous total power dissipation. Thermal shutdown typically occurs when
the junction temperature reaches 165°C.
Copyright © 2006–2012, Texas Instruments Incorporated
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
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Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
Supply voltage
3
–7(1)
3.6
12
25
5
V
V
VI or VIC
Voltage at any bus terminal (separately or common mode)
'HVD30, 'HVD33
1/tUI
Signaling rate
'HVD31, 'HVD34
'HVD32, 'HVD35
Mbps
1
RL
Differential load resistance
High-level input voltage
Low-level input voltage
Differential input voltage
54
2
60
Ω
V
V
V
VIH
VIL
VID
D, DE, RE
D, DE, RE
VCC
0.8
12
0
–12
–60
–8
Driver
IOH
High-level output current
mA
Receiver
Driver
60
8
125(2)
IOL
TA
Low-level output current
mA
°C
Receiver
Ambient still-air temperature
–55
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Electrostatic Discharge Protection
PARAMETER
TEST CONDITIONS
Bus terminals and GND
TYP(1)
±16
±4
UNIT
Human-Body Model
Human-Body Model(2)
Charged-Device Model(3)
All pins
All pins
kV
±1
(1) All typical values at 25°C with 3.3-V supply
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A
(3) Tested in accordance with JEDEC Standard 22, Test Method C101
4
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Product Folder Link(s): SN65HVD30-EP SN65HVD31-EP SN65HVD32-EP SN65HVD33-EP SN65HVD34-EP
SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
Driver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
VI(K)
Input clamp voltage
II = –18 mA
IO = 0
–1.5
V
VCC
0.1
+
2.3
RL = 54 Ω, See Figure 1 (RS-485)
RL = 100 Ω, See Figure 1 (RS-422)
Vtest = –7 V to 12 V, See Figure 2
1.5
2
2
|VOD(SS)
|
Steady-state differential output voltage
V
2.3
1.5
Change in magnitude of steady-state
differential output voltage between
states
Δ|VOD(SS)
|
RL = 54 Ω, See Figure 1 and Figure 2
–0.2
0.2
V
V
Differential output voltage overshoot
and undershoot
RL = 54 Ω, CL = 50 pF, See Figure 5 and
Figure 3
VOD(RING)
10%(2)
'HVD30, 'HVD33
0.5
Peak-to-peak
common-mode
output voltage
VOC(PP)
See Figure 4
V
'HVD31, 'HVD32,
'HVD34, 'HVD35
0.25
Steady-state common-mode output
voltage
VOC(SS)
See Figure 4
See Figure 4
1.6
2.3
0.05
90
V
V
Change in steady-state common-mode
output voltage
ΔVOC(SS)
–0.05
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
'HVD30, 'HVD31,
'HVD32
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
–10
–10
0
High-impedance
state output
IZ(Z) or
IY(Z)
μA
VCC = 3 V or 0 V, DE = 0 V,
VZ or VY = 12 V
current
90
'HVD33, 'HVD34,
'HVD35
Other input
at 0 V
VCC = 3 V or 0 V, DE = 0 V,
VZ or VY = –7 V
VZ or VY = –7 V
VZ or VY = 12 V
IZ(S) or
IY(S)
Other input
at 0 V
Short-circuit output current
±250
16
mA
II
Input current
D, DE
100
μA
C(OD)
Differential output capacitance
VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
pF
(1) All typical values at 25°C with 3.3-V supply
(2) 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
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Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
'HVD30, 'HVD33
4
25
10
38
23
65
Propagation delay time,
low- to high-level output
tPLH
tPHL
tr
'HVD31, 'HVD34
'HVD32, 'HVD35
'HVD30, 'HVD33
'HVD31, 'HVD34
'HVD32, 'HVD35
'HVD30, 'HVD33
'HVD31, 'HVD34
'HVD32, 'HVD35
'HVD30, 'HVD33
'HVD31, 'HVD34
'HVD32, 'HVD35
'HVD30, 'HVD33
'HVD31, 'HVD34
'HVD32, 'HVD35
'HVD33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
4
175 305
9
23
65
Propagation delay time,
high- to low-level output
25
38
120
2.5
20
175 305
5
18
60
Differential output signal
rise time
RL = 54 Ω, CL = 50 pF,
See Figure 5
37
120
2.5
20
185 300
5
18
60
Differential output signal
fall time
tf
35
120
180 300
0.6
tsk(p)
tPZH1
tPHZ
tPZL1
tPLZ
tPZH2
tPZL2
Pulse skew (|tPHL – tPLH|)
2.0
5.1
45
Propagation delay time, high-
impedance to high-level output
'HVD34
235
490
25
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z,
See Figure 6
'HVD35
'HVD33
Propagation delay time, high-
level to high-impedance output
'HVD34
65
'HVD35
165
35
'HVD33
Propagation delay time, high-
impedance to low-level output
'HVD34
190
490
30
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y,
See Figure 7
'HVD35
'HVD33
Propagation delay time, low-
level to high-impedance output
'HVD34
120
290
4000
'HVD35
'HVD30
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z,
See Figure 6
Propagation delay time, standby
to high-level output
'HVD33
'HVD30
'HVD33
5000
4000
5000
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y,
See Figure 7
Propagation delay time, standby
to low-level output
(1) All typical values at 25°C with 3.3-V supply
6
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
Positive-going differential input threshold
voltage
VIT+
IO = –8 mA
IO = 8 mA
–0.02
V
Negative-going
differential input
threshold voltage
'HVD30
'HVD33
–0.15
VIT–
V
-0.2
Vhys
VIK
Hysteresis voltage (VIT+ – VIT–
Enable-input clamp voltage
)
50
mV
V
II = –18 mA
–1.5
2.4
VID = 200 mV, IO = –8 mA, See Figure 8
VID = –200 mV, IO = 8 mA, See Figure 8
VO = 0 or VCC, RE at VCC
VA or VB = 12 V
VO
Output voltage
V
0.4
1
IO(Z)
High-impedance-state output current
–1
μA
0.05
0.06
0.1
0.1
VA or VB = 12 V, VCC = 0 V
VA or VB = –7 V
'HVD31, 'HVD32,
'HVD34, 'HVD35
Other input
at 0 V
–0.10 –0.04
–0.10 –0.03
0.20
VA or VB = –7 V, VCC = 0 V
VA or VB = 12 V
IA or
IB
Bus input current
Input current, RE
mA
0.35
0.4
VA or VB = 12 V, VCC = 0 V
VA or VB = –7 V
0.24
Other input
at 0 V
'HVD30, 'HVD33
–0.35 –0.18
–0.25 –0.13
–60
VA or VB = –7 V, VCC = 0 V
VIH = 0.8 V or 2 V
IIH
μA
CID
Differential input capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
15
pF
Supply Current
'HVD30
2.1
6.4
1.8
D at 0 V or VCC and no load
'HVD31, 'HVD32
'HVD33
mA
RE at 0 V, D at 0 V or VCC, DE at 0 V,
No load (receiver enabled and driver
disabled)
'HVD34, 'HVD35
2.2
RE at VCC, D at VCC, DE at 0 V,
No load (receiver disabled and driver
disabled)
'HVD33, 'HVD34,
'HVD35
0.022
1.5
μA
ICC
Supply current
'HVD33
RE at 0 V, D at 0 V or VCC, DE at VCC
No load (receiver enabled and driver
enabled)
,
2.1
6.5
1.8
6.2
'HVD34, 'HVD35
'HVD33
mA
RE at VCC, D at 0 V or VCC, DE at VCC
No load (receiver disabled and driver
enabled)
'HVD34, 'HVD35
(1) All typical values at 25°C with 3.3-V supply
Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
'HVD30, 'HVD33
26
47
29
49
60
ns
70
Propagation delay time,
low- to high-level output
tPLH
tPHL
tsk(p)
'HVD31, 'HVD32, 'HVD34, 'HVD35
'HVD30, 'HVD33
60
ns
70
Propagation delay time,
high- to low-level output
'HVD31, 'HVD32, 'HVD34, 'HVD35
'HVD30, 'HVD33
VID = –1.5 V to 1.5 V,
CL = 15 pF, See Figure 9
12
ns
10
Pulse skew (|tPHL – tPLH|)
'HVD31, 'HVD34, 'HVD32, 'HVD35
'HVD30
10
ns
18
tr
tf
Output signal rise time
Output signal fall time
'HVD33
12.5
ns
(1) All typical values 25°C with 3.3-V supply
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
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Receiver Switching Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DE at 3 V
MIN TYP(1)
MAX UNIT
tPHZ
Output disable time from high level
Output enable time to high level
20
20
ns
ns
tPZH1
CL = 15 pF,
See Figure 10
'HVD30
4000
5000
20
Propagation delay time,
standby to high-level output
tPZH2
DE at 0 V
DE at 3 V
DE at 0 V
ns
'HVD33
tPLZ
Output disable time from low level
Output enable time to low level
ns
ns
tPZL1
20
CL = 15 pF,
See Figure 11
'HVD30
'HVD33
4000
5000
Propagation delay time,
standby to low-level output
tPZL2
ns
Receiver Equalization Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DEVICE
'HVD33(2)
MIN
TYP(1)
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
MAX UNIT
100 m
25 Mbps
150 m
200 m
200 m
250 m
300 m
500 m
'HVD33(2)
'HVD33(2)
'HVD33(2)
'HVD33(2)
'HVD33(2)
'HVD34(2)
'HVD33(2)
'HVD34(2)
Pseudo-random NRZ code
with a bit pattern length of
216 – 1, Belden 3105A cable
10 Mbps
Peak-to-peak
eye-pattern jitter
tj(pp)
ns
5 Mbps
3 Mbps
1 Mbps
500 m
1000 m 'HVD34(2)
(1) All typical values are at VCC = 5 V and temperature = 25°C.
(2) The SN65HVD33 and the SN65HVD34 do not have receiver equalization, but are specified for comparison.
Device Power Dissipation – PD
DEVICE
'HVD30 (25 Mbps)
'HVD31 (5 Mbps)
'HVD32 (1 Mbps)
'HVD33 (25 Mbps)
'HVD34 (5 Mbps)
'HVD35 (1 Mbps)
TEST CONDITIONS
MIN MAX UNIT
197
RL = 60 Ω, CL = 50 pF,
213 mW
193
Input to D a 50% duty cycle square wave at indicated signaling rate, TA = 85°C
197
RL = 60 Ω, CL = 50 pF, DE at VCC, RE at 0 V,
Input to D a 50% duty cycle square wave at indicated signaling rate, TA = 85°C
193 mW
248
8
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION
V
CC
I
DE
Y
Z
I
I
Y
Z
V
OD
RL
0 or 3 V
I
V
I
V
Z
V
Y
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
V
CC
DE
Y
Z
D
V
OD
60 Ω ±1%
0 or 3 V
+
_
−7 V < V
< 12 V
(test)
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
V
OD(SS)
V
OD(RING)
0 V Differential
V
OD(RING)
–V
OD(SS)
Figure 3. VOD(RING) Waveform and Definitions
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
the VOD(H) and VOD(L) steady state values.
V
Y
Y
V
CC
27 Ω ± 1%
27 Ω ± 1%
V
DE
Z
Z
Y
Z
D
V
OC(PP)
∆V
Input
OC(SS)
V
OC
V
C
L
= 50 pF ±20%
OC
Input: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 4. Test Circuit and Definitions for Driver Common-Mode Output Voltage
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
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PARAMETER MEASUREMENT INFORMATION (continued)
Y
Z
»
»
W
W
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
3 V
D
S1
Y
3 V
0 V
1.5 V
Z
1.5 V
Y
Z
VI
S1
D
0 V
VO
0.5 V
tPZH(1 & 2)
VOH
DE
RL = 110 W
1ꢀ
VO
2.3 V
CL = 50 pF
20ꢀ
~ 0 V
Input
Generator
VI 50 W
tPHZ
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
B. CL Includes Fixture and Instrumentation Capacitance
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
VCC
D
3 V
0 V
S1
Z
Y
R
= 110 Ω
3 V
L
± 1%
Y
V
I
1.5 V
1.5 V
S1
D
V
O
0 V
Z
t
t
PZL(1&2)
PLZ
DE
50 Ω
VCC
C
= 50 pF ±20%
Input
L
V
I
0.5 V
Generator
C
L
Includes Fixture
and Instrumentation
Capacitance
V
O
2.3 V
V
OL
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
I
A
A
I
O
R
V
A
V
I
ID
B
V
B
V
IC
V
O
B
V
A
+ V
B
RE
2
I
I
V
I
Figure 8. Receiver Voltage and Current Definitions
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION (continued)
3 V
0 V
A
B
1.5 V
1.5 V
V
I
V
O
R
Input
Generator
V
I
50 Ω
t
t
PHL
PLH
1.5 V
0 V
C
L
= 15 pF
V
OH
OL
90% 90%
±20%
RE
V
O
1.5 V
10%
1.5 V
10%
V
t
t
f
r
A. CL Includes Fixture and Instrumentation Capacitance
B. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
V
CC
A
3 V
1.5 V
0 V
V
A
B
S1
1 kW ±1ꢀ
V
R
O
V
1.5V
1.5V
I
B
C
= 15 pF
L
±±0ꢀ
0V
V
RE
t
t
PHZ
PZH(1 & ±)
Input
Generator
OH
50 W
I
1.5 V
0.5V
~0 V
V
O
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
V
CC
A
3 V
0 V
1.5 V
V
A
S1
1 k W ±1ꢀ
V
R
O
V
1.5V
1.5V
I
B
C
= 15 pF
L
±±0ꢀ
B
0V
V
RE
t
PZL(1 & ±)
t
PLZ
Input
Generator
CC
50 W
I
1.5 V
V
0.5 V
O
V
OL
A. Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω
Figure 11. Receiver Enable Time From Standby (Driver Disabled)
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
0 V or 3 V
DE
A
B
Y
D
R
Z
100 W
1ꢀ
100 W
1ꢀ
RE
Pulse Generator
15 ms duration
1ꢀ Duty Cycle
tr, tf £ 100 ns
0 V or 3 V
+
-
+
-
Figure 12. Test Circuit, Transient Over Voltage Test
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
www.ti.com
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
DEVICE INFORMATION
Low-Power Standby Mode
When both the driver and receiver are disabled (DE low and RE high), the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this
state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
12
A
2
R
11
B
3
RE
Low-Power
Standby
4
DE
9
Y
5
D
10
Z
Figure 13. Low-Power Standby Logic Diagram
If only the driver is re-enabled (DE transitions to high), the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver fail-safe feature.
If only the receiver is re-enabled (RE transitions to low), the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus, the receiver responds as described in the fail-safe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
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SN65HVD35-EP
SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
FUNCTION TABLES
Table 1. SN65HVD33, SN65HVD34, SN65HVD35
DRIVER(1)
INPUTS
OUTPUTS
D
H
DE
H
Y
H
L
Z
L
L
H
H
Z
H
X
L or open
H
Z
L
Open
(1) H = high level, L = low level, Z = high impedance, X = irrelevant
Table 2. SN65HVD33, SN65HVD34, SN65HVD35
RECEIVER(1)
DIFFERENTIAL INPUTS
VID = V(A) – V(B)
ENABLE
RE
OUTPUT
R
VID ≤ −0.2 V
−0.2 V < VID < −0.02 V
−0.02 V ≤ VID
X
L
L
?
L
L
H
Z
H
H
H
H or open
Open circuit
L
L
L
Idle circuit
Short circuit, V(A) = V(B)
(1) H = high level, L = low level, Z = high impedance, X = irrelevant,
? = indeterminate
Table 3. SN65HVD30, SN65HVD31, SN65HVD32
DRIVER(1)
OUTPUTS
INPUT
D
Y
H
L
Z
L
H
L
H
H
Open
L
(1) H = high level, L = low level
Table 4. SN65HVD30, SN65HVD31, SN65HVD32
RECEIVER(1)
DIFFERENTIAL INPUTS
VID = V(A) – V(B)
OUTPUT
R
V
ID ≤ −0.15 V
L
?
−0.15 V < VID < −0.02 V
−0.02 V ≤ VID
H
H
H
H
Open circuit
Idle circuit
Short circuit, V(A) = V(B)
(1) H = high level, L = low level, ? = indeterminate
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
RE Input
D and DE Input
VCC
VCC
130 kW
470 W
470 W
Input
Input
9 V
9 V
125 kW
A Input
B Input
R1
VCC
VCC
R1
22 V
R3
22 V
R3
Input
Input
R2
22 V
R2
22 V
R Output
Y and Z Outputs
VCC
VCC
16 V
5 W
Output
9 V
Output
16 V
R1/R2
9 kΩ
R3
SN65HVD30, SN65HVD33
SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35
45 kΩ
180 kΩ
36 kΩ
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS
'HVD30, 'HVD33
RMS SUPPLY CURRENT
vs
'HVD31, 'HVD34
RMS SUPPLY CURRENT
vs
SIGNALING RATE
SIGNALING RATE
55
50
45
40
35
30
60
55
50
45
40
35
30
TA = 25°C RL = 54 W
TA = 25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
RE = VCC CL = 50 pF
DE = VCC
VCC = 3.3 V
VCC = 3.3 V
0
5
10
15
20
25
0
1
2
3
4
5
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 14.
Figure 15.
'HVD32, 'HVD35
RMS SUPPLY CURRENT
vs
SIGNALING RATE
60
55
50
45
40
35
TA = 25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
VCC = 3.3 V
30
0
0.2
0.4
0.6
0.8
1
Signaling Rate - Mbps
Figure 16.
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SN65HVD30-EP, SN65HVD31-EP, SN65HVD32-EP
SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
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SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
'HVD30, 'HVD33
BUS INPUT CURRENT
vs
'HVD31, 'HVD32, 'HVD34, 'HVD35
BUS INPUT CURRENT
vs
INPUT VOLTAGE
INPUT VOLTAGE
250
200
150
100
50
60
40
20
0
TA = 25°C
TA = 25°C
RE = 0 V
DE = 0 V
RE = 0 V
DE = 0 V
VCC = 3.3 V
VCC = 3.3 V
0
–50
–100
–150
–200
-20
-40
-60
–7
–4
–1
2
5
8
11
14
-7
-4
-1
2
5
8
11
14
VI - Bus Input Voltage - V
VI - Bus Input Voltage - V
Figure 17.
Figure 18.
DRIVER LOW-LEVEL OUTPUT CURRENT
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.01
–0.01
–0.03
–0.05
–0.07
–0.09
–0.11
–0.13
0.14
0.12
0.1
VCC = 3.3 V
DE = VCC
D = 0 V
VCC = 3.3 V
DE = VCC
D = 0 V
0.08
0.06
0.04
0.02
0
–0.02
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
VOL - Low-Level Output Voltage - V
VOH - High-Level Output Voltage - V
Figure 19.
Figure 20.
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SN65HVD33-EP, SN65HVD34-EP, SN65HVD35-EP
SGLS367D –SEPTEMBER 2006–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
DRIVER OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
2.2
2.1
2.0
1.9
1.8
40
35
30
25
20
15
10
5
VCC = 3.3 V
DE = VCC
D = VCC
TA = 25°C
RL = 54 W
D = VCC
DE = VCC
0
0
0.5
1
1.5
2
2.5
3
3.5
–40
–15
10
35
60
85
TA - Free-Air Temperature - °C
VCC Supply Voltage - V
Figure 21.
Figure 22.
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SN65HVD35-EP
PACKAGE OPTION ADDENDUM
www.ti.com
22-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN65HVD30MDREP
SN65HVD30MDREPG4
SN65HVD33MDREP
SN65HVD33MDREPG4
V62/06634-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
14
14
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06634-04YE
14
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD30-EP, SN65HVD33-EP :
Catalog: SN65HVD30, SN65HVD33
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD30MDREP
SN65HVD33MDREP
SOIC
SOIC
D
D
8
2500
2500
330.0
330.0
12.4
16.4
6.4
6.5
5.2
9.0
2.1
2.1
8.0
8.0
12.0
16.0
Q1
Q1
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65HVD30MDREP
SN65HVD33MDREP
SOIC
SOIC
D
D
8
2500
2500
367.0
333.2
367.0
345.9
35.0
28.6
14
Pack Materials-Page 2
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