SN65HVD50D [TI]
HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS; 高输出全双工RS - 485驱动器和接收
| 型号： | SN65HVD50D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS |
| 文件： | 总23页 (文件大小：1502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS
The SN65HVD50, SN65HVD51, SN65HVD52,
SN65HVD56 and SN65HVD57 are fully enabled with
no external enabling pins. The SN65HVD56 and
FEATURES
•
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
SN65HVD57
implement
receiver
equalization
•
•
Bus-Pin ESD Protection Exceeds 15 kV HBM
technology for improved performance in long distance
applications.
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 5 Mbps and 25
Mbps
The SN65HVD53, SN65HVD54, SN65HVD55,
SN65HVD58, and SN65HVD59 have active-high
driver enables and active-low receiver enables. A
very low, less than 1 uA, standby current can be
achieved by disabling both the driver and receiver.
The SN65HVD58 and SN65HVD59 implement
receiver equalization technology for improved
performance in long distance applications.
•
•
Low-Current Standby Mode < 1 µA
Glitch-Free Power-Up and Power-Down Bus
I/Os
•
•
Bus Idle, Open, and Short Circuit Failsafe
Meets or exceeds the requirements of ANSI
TIA/EIA-485-A and RS-422 Compatible
All devices are characterized for operation from -40°
C to +85°.
•
3.3-V Devices available, SN65HVD30-39
100
APPLICATIONS
SN65HVD50
SN65HVD56
•
•
•
•
•
Utility Meters
Chassis-to-Chassis Interconnects
DTE/DCE Interfaces
Industrial, Process, and Building Automation
Point-of-Sale (POS) Terminals and Networks
SN65HVD53
SN65HVD58
10
SN65HVD57
SN65HVD51
SN65HVD59
SN65HVD54
1
DESCRIPTION
SN65HVD52
SN65HVD55
The SN65HVD5X devices are 3-state differential line
drivers and differential-input line receivers that
operate with a 5-V power supply. Each driver and
receiver has separate input and output pins for
full-duplex bus communication designs. They are
designed for balanced transmission lines and
0.1
10
100
Cable Length (meters)
1000
interoperation
TIA/EIA-422-B, ITU-T v.11 and ISO 8482:1993
standard-compliant devices.
with
ANSI
TIA/EIA-485A,
The SN65HVD56 and SN65HVD58 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates up to 20 Mbps at cable lengths up to 160
meters.
The SN65HVD57 and SN65HVD59 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates in the range of 1 to 5 Mbps at cable lengths up
to 1000 meters.
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2005, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SN65HVD50, SN65HVD51, SN65HVD52, SN65HVD56,
SN65HVD57
SN65HVD53, SN65HVD54, SN65HVD55, SN65HVD58,
SN65HVD59
D PACKAGE (TOP VIEW)
NC
R
V
V
A
B
Z
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
CC
V
1
2
3
4
8
7
6
5
A
B
Z
Y
CC
R
RE
D
DE
GND
D
GND
GND
8
8
NC
2
A
R
7
NC - No internal connection
B
5
3
Y
D
6
Z
AVAILABLE OPTIONS
SIGNALING
RATE
RECEIVER
EQUALIZATION
BASE
PART NUMBER
UNIT LOADS
ENABLES
SOIC MARKING
25 Mbps
5 Mbps
1 Mbps
25 Mbps
5 Mbps
1 Mbps
25 Mbps
5 Mbps
25 Mbps
5 Mbps
1/2
1/8
1/8
1/2
1/8
1/8
1/2
1/8
1/2
1/8
No
No
No
No
SN65HVD50
SN65HVD51
SN65HVD52
SN65HVD53
SN65HVD54
SN65HVD55
SN65HVD56
SN65HVD57
SN65HVD58
SN65HVD59
PREVIEW
PREVIEW
PREVIEW
65HVD53
65HVD54
65HVD55
PREVIEW
PREVIEW
PREVIEW
PREVIEW
No
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Yes
2
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)(2)
UNIT
VCC
Supply voltage range
–0.3 V to 6 V
–9 V to 14 V
–50 to 50 V
-0.5 V to 7 V
Internally limited
11 mA
Voltage range at any bus terminal (A, B, Y, Z)
Voltage input, transient pulse through 100 Ω. See Figure 12 (A, B, Y, Z)(3)
Voltage input range (D, DE, RE)
VI
IO
Continuous total power dissipation
Output current (receiver output only, R)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) This tests survivability only and the output state of the receiver is not specified.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN NOM
4.5
–7(1)
MAX UNIT
VCC
Supply voltage
Voltage at any bus terminal (separately or common mode)
5.5
V
VI or
VIC
12
1/tUI
SN65HVD50, SN65HVD53, SN65HVD56, SN65HVD58
25
5
Signaling rate
SN65HVD51, SN65HVD54, SN65HVD57, SN65HVD59
SN65HVD52, SN65HVD55
Mbps
Ω
1
RL
Differential load resistance
High-level input voltage
Low-level input voltage
Differential input voltage
54
2
60
VIH
VIL
VID
D, DE, RE
D, DE, RE
VCC
0.8
12
0
V
-12
-60
–8
Driver
IOH
High-level output current
mA
Receiver
Driver
60
8
IOL
Low-level output current
Junction temperature
mA
Receiver
(2)
TJ
–40
150
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
TEST CONDITIONS
Bus terminals and GND
All pins
MIN
TYP(1)
±16
±4
MAX
UNIT
Human body model
Human body model(2)
kV
Charged-device-model(3)
All pins
±1
(1) All typical values at 25°C and with a 5-V supply.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
3
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VI(K)
Input clamp voltage
II = –18 mA
–1.5
4
IO = 0
VCC
RL = 54 Ω, See Figure 1 (RS-485)
RL = 100 Ω, See Figure 1 (RS-422)
Vtest = –7 V to 12 V, See Figure 2
RL = 54 Ω, See Figure 1 and
1.7
2.4
1.6
2.6
3.2
|VOD(SS)
|
Steady-state differential output voltage
Change in magnitude of steady-state
∆|VOD(SS)
|
–0.2
0.2
differential output voltage between states Figure 2
RL = 54 Ω, CL = 50 pF, See
Figure 5
See Figure 3 for definition
Differential Output Voltage overshoot
and undershoot
VOD(RING)
0.05 |VOD(SS)
|
V
HVD50, HVD53,
HVD56, HVD58
0.5
Peak-to-peak
VOC(PP)
common-mode
output voltage
HVD51, HVD54,
HVD57, HVD59
See Figure 4
0.4
0.4
HVD52, HVD55
Steady-state common-mode
output voltage
VOC(SS)
2.2
3.3
0.1
90
See Figure 4
Change in steady-state common-mode
output voltage
∆VOC(SS)
–0.1
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
–10
High-impedance state
output current
HVD53, HVD54,
HVD55, HVD58,
HVD59
VCC = 5 V or 0 V,
DE = 0 V
VZ or VY = 12 V
IZ(Z) or IY(Z)
µA
90
Other input
at 0 V
VCC = 5 V or 0 V,
DE = 0 V
–10
VZ or VY = –7 V
VZ or VY = –7 V
VZ or VY = 12 V
–250
–250
0
250
250
100
Other input
at 0 V
IZ(S) or IY(S) Short Circuit output Current
mA
II
Input current
D, DE
µA
pF
VOD = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
C(OD)
Differential output capacitance
16
(1) All typical values are at 25°C and with a 5-V supply.
4
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
4
TYP(1)
8
MAX UNIT
HVD50, HVD53, HVD56, HVD58
Propagation delay time,
12
tPLH
tPHL
tr
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
20
90
4
29
46
230
12
46
230
12
60
300
11
60
300
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
low-to-high-level output
143
8
HVD50, HVD53, HVD56, HVD58
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
Propagation delay time,
high-to-low-level output
20
90
3
30
143
6
HVD50, HVD53, HVD56, HVD58
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
Differential output signal
rise time
25
130
3
34
197
6
RL = 54 Ω, CL = 50 pF,
See Figure 5
HVD50, HVD53, HVD56, HVD58
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
Differential output signal fall
time
tf
25
130
33
192
HVD50, HVD53, HVD56, HVD58
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
tsk(p)
tsk(pp)
tPZH1
tPHZ
tPZL1
tPLZ
tPZH2
tPZL2
Pulse skew (|tPHL - tPLH|)
Part-to-part skew
2
8
HVD50, HVD53, HVD56, HVD58
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
1
4
(2)
22
HVD53, HVD58
30
180
380
16
Propagation delay time,
high-impedance-to-high-
level output
HVD54, HVD59
RL = 110 Ω, RE at 0 V,
See Figure 6
D = 3 V and S1 = Y,
D = 0 V and S1 = Z
HVD55
HVD53, HVD58
Propagation delay time,
high-level-to-high-
HVD54, HVD59
40
impedance output
HVD55
110
23
HVD53, HVD58
Propagation delay time,
high-impedance-to-low-level HVD54, HVD59
200
420
19
RL = 110 Ω, RE at 0 V,
See Figure 7
D = 3 V and S1 = Z,
D = 0 V and S1 = Y
output
HVD55
HVD53, HVD58
Propagation delay time,
low-level-to-high-impedance HVD54, HVD59
70
output
HVD55
160
RL = 110 Ω, RE at 3 V,
See Figure 6
D = 3 V and S1 = Y,
D = 0 V and S1 = Z
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
3300
3300
RL = 110 Ω, RE at 3 V,
See Figure 7
D = 3 V and S1 = Z,
D = 0 V and S1 = Y
(1) All typical values are at 25°C and with a 5-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Positive-going differential input
threshold voltage
VIT+
VIT-
IO = –8 mA
IO = 8 mA
–0.02
V
Negative-going differential input
threshold voltage
–0.20
Vhys
VIK
Hysteresis voltage (VIT+ - VIT-
)
50
mV
V
Enable-input clamp voltage
II = –18 mA
–1.5
4.0
VID = 200 mV, IO = –8 mA, See Figure 8
VID = –200 mV, IO = 8 mA, See Figure 8
VO
Output voltage
V
0.3
1
High-impedance-state output
current
IO(Z)
VO = 0 or VCCRE at VCC
–1
µA
VA or VB = 12 V
0.19
0.24
0.3
0.4
HVD50,
HVD53,
HVD56,
HVD58
VA or VB = 12 V, VCC = 0 V
VA or VB = -7 V
Other input
at 0 V
mA
mA
–0.35
–0.25
–0.19
–0.14
0.05
VA or VB = -7 V, VCC = 0 V
VA or VB = 12 V
IA or IB
Bus input current
HVD51,
0.10
0.10
HVD52,
HVD54,
HVD55,
HVD57,
HVD59
VA or VB = 12 V, VCC = 0 V
VA or VB = -7 V
0.06
Other input
at 0 V
–0.10
–0.10
–0.05
VA or VB = -7 V, VCC = 0 V
–0.03
16
VIH = 2 V
–60
–60
µA
µA
pF
IIH
Input current, RE
VIL = 0.8 V
CID
Differential input capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
HVD50,
HVD51,
HVD52
8.0
D at 0 V or VCC and No Load
HVD56,
HVD57
9.5
2.3
2.9
mA
HVD53
HVD54,
HVD55
RE at 0 V, D at 0 V or VCC, DE at 0 V,
No load (Receiver enabled and
driver disabled)
HVD58,
HVD59
4.5
HVD53,
HVD54,
HVD55,
RE at VCC, D at VCC, DE at 0 V,
No load (Receiver disabled and
driver disabled)
0.08
1
µA
ICC
Supply current
HVD58,
HVD59
HVD53
2.7
8.0
HVD54,
HVD55
RE at 0 V, D at 0 V or VCC, DE at VCC
No load (Receiver enabled and
driver enabled)
,
HVD58
HVD59
HVD53
4.3
9.7
2.3
mA
HVD54,
HVD55
RE at VCC, D at 0 V or VCC, DE at VCC
No load (Receiver disabled and
driver enabled)
7.7
HVD58
HVD59
3.2
8.5
(1) All typical values are at 25°C and with a 5-V supply.
6
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
HVD50, HVD53, HVD56, HVD58
Propagation delay time,
low-to-high-level output
24
40
tPLH
tPHL
tsk(p)
HVD51, HVD52, HVD54, HVD55,
HVD57, HVD59
43
26
47
55
35
60
HVD50, HVD53, HVD56, HVD58
Propagation delay time,
high-to-low-level output
HVD51, HVD52, HVD54, HVD55,
HVD57, HVD59
VID = -1.5 V to 1.5 V,
CL = 15 pF,
See Figure 9
HVD50, HVD53, HVD56, HVD57,
HVD58, HVD59
5
7
Pulse skew (|tPHL - tPLH|)
Part-to-part skew
HVD51, HVD54, HVD52, HVD55
HVD50, HVD53, HVD56, HVD58
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
5
6
(2)
tsk(pp)
ns
6
tr
Output signal rise time
2.3
2.4
4
4
tf
Output signal fall time
tPHZ
tPZH1
Output disable time from high level
Output enable time to high level
17
10
DE at 3 V, CL = 15 pF
See Figure 10
DE at 0 V, CL = 15 pF
See Figure 10
tPZH2
Propagation delay time, standby-to-high-level output
3300
tPLZ
Output disable time from low level
Output enable time to low level
13
10
DE at 3 V, CL = 15 pF
See Figure 11
tPZL1
DE at 0 V, CL = 15 pF
See Figure 11
tPZL2
Propagation delay time, standby-to-low-level output
3300
(1) All typical values are at 25°C and with a 5-V supply
(2) .tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
7
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
RECEIVER EQUALIZATION CHARACTERISTICS
over recommended operating conditions unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
MIN
TYP(2)
MAX
UNIT
ns
0 m
HVD56, HVD58
HVD53
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
100 m
HVD56, HVD58
HVD53
25 Mbps
150 m
200 m
200 m
250 m
300 m
500 m
HVD56, HVD58
HVD53
HVD56, HVD58
HVD53
HVD56, HVD58
HVD53
Pseudo-random NRZ
code with a bit pattern
length o 216-1, Belden
3105A cable
Peak-to-peak
tj(pp) eye-pattern
jitter
10 Mbps
HVD56, HVD58
HVD53
HVD56, HVD58
HVD54
5 Mbps
3 Mbps
1 Mbps
HVD57, HVD59
HVD53
HVD54
500 m
HVD56, HVD58
HVD57, HVD59
HVD54
1000 m
HVD57, HVD59
(1) The HVD53 and HVD54 do not have receiver equalization but are specified for comparison.
(2) All typical values are at VCC = 5 V, and temperature = 25°C.
8
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted(1)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Low-K board(3), No airflow
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD56 (25Mbps)
230.8
162.6
135.1
Junction–to–ambient
thermal resistance(2)
θJA
High-K board(4), No airflow
Junction–to–ambient
thermal resistance(2)
92.1
°C/W
44.4
Junction–to–board
thermal resistance
θJB
High-K board
No board
61.1
43.5
58.6
420
404
383
Junction–to–case
thermal resistance
θJC
RL= 60Ω, CL = 50 pF,
Input to D a 50% duty cycle
square wave at indicated
signaling rate
HVD51, HVD57 (10Mbps)
HVD52 (1Mbps)
Device power
dissipation
PD
mW
RL= 60Ω, CL = 50 pF,
DE at VCCRE at 0 V,
Input to D a 50% duty cycle
square wave at indicated
signaling rate
HVD53, HVD58 (25Mbps)
420
404
383
HVD54, HVD59 (10Mbps)
HVD55 (1Mbps)
Low-K board, No airflow
HVD50, HVD56
–40
–40
–40
–40
–40
55
84
85
85
85
HVD51, HVD52, HVD57
Ambient air
temperature
TA
HVD53, HVD54, HVD55, HVD58, HVD59
HVD50, HVD51, HVD52, HVD56, HVD57
HVD53, HVD54, HVD55, HVD58, HVD59
°C
High-K board, No airflow
TJSD Thermal shutdown junction temperature
165
(1) See Application Information section for an explanation of these parameters.
(2) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(4) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
PARAMETER MEASUREMENT INFORMATION
V
CC
375 Ω ±1%
V
CC
I
Y
DE
I
I
DE
Y
Y
D
V
OD
R
0 or 3 V
L
V
OD
60 Ω ±1%
0 or 3 V
+
Z
I
Z
−7 V < V
< 12 V
(test)
Z
_
V
I
375 Ω ±1%
V
Z
V
Y
Figure 1. Driver VOD Test Circuit: Voltage and Current
Definitions
Figure 2. Driver VOD With Common-Mode Loading Test
Circuit
9
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
theVOD(H) and VOD(L) steady state values.
V
OD(SS)
V
OD(RING)
0 V Differential
V
OD(RING)
-V
OD(SS)
Figure 3. VOD(RING) Waveform and Definitions
V
Y
Y
V
CC
27 Ω ± 1%
V
Z
DE
Z
Y
D
V
OC(PP)
∆V
Input
OC(SS)
27 Ω ± 1%
V
OC
Z
V
OC
C
L
= 50 pF ±20%
C
L
Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t <6ns, t <6ns, Z = 50 Ω
r f O
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
»
W
Z
W
»
W
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
10
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
3 V
D
S1
Y
3 V
0 V
1.5 V
Z
1.5 V
Y
V
I
S1
D
0 V
V
0.5 V
O
t
Z
PZH(1 & 2)
V
OH
DE
R
= 110 W
L
V
2.3 V
O
C = 50 pF
L
±1%
~ 0 V
Input
Generator
V
I
50 W
±20%
t
PHZ
Generator: PRR = 500kHz, 50% Duty Cycle, t <6 ns, t < 6ns, Z = 50 W
0
r
f
C
Includes Fixture and Instrumentation Capacitance
L
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
V
CC
D
S1
Z
3 V
0 V
R
L
= 110 Ω
3 V
Y
± 1%
Y
V
I
1.5 V
1.5 V
S1
D
V
O
0 V
Z
t
t
PZL(1&2)
PLZ
DE
V
CC
C
L
= 50 pF ±20%
Input
V
I
50 Ω
0.5 V
Generator
C
L
Includes Fixture
V
O
2.3 V
and Instrumentation
Capacitance
V
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r f o
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
I
A
A
I
O
R
V
ID
V
B
A
V + V
A
V
IC
V
O
B
V
I
RE
B
B
2
I
V
I
I
Figure 8. Receiver Voltage and Current Definitions
11
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
A
3 V
R
1. 5
V
1. 5 V
Input
V
V
I
I
50 W
Generator
0 V
B
C = 15 pF
L
1.5 V
V
O
t
t
PLH
PHL
±20%
RE
0 V
V
OH
90 %
90 %
1.5 V
10%
1.5 V
10%
V
O
Generator : PRR = 500 kHz , 50%
C
Includes Fixture
L
V
t
t
Duty Cycle , t <6 ns , t < 6ns ,
Z = 50 W
OL
r
f
and Instrumentation
Capacitance
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
VCC
A
3 V
1.5 V
0 V
V
A
S1
V
1 kW ±1%
R
O
V
1.5 V
1.5 V
I
B
C
= 15 pF
B
0 V
L
t
±20%
PZH(1 & 2)
PHZ
VOH
0.5 V
~0 V
Input
Generator
50 W
I
1.5 V
V
C
Includes Fixture and
O
L
Instrumentation Capacitance
Generator: P = 500 kHz, 50%, Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 W
f
RR
r
0
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
V
CC
A
3 V
0 V
A
S1
1 kW ±1%
V
O
R
V
1.5 V
1.5 V
I
B
1.5 V
C
= 15 pF
B
0 V
L
RE
t
±20%
PZL(1 & 2)
t
PLZ
V
Input
Generator
CC
V
I
50 W
1.5 V
V
0.5 V
O
C
Includes Fixture
L
V
and Instrumentation
Capacitance
OL
Generator: P = 500 kHz, 50%, Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 W
f
RR
r
0
Figure 11. Receiver Low-Level Enable and Disable Time Test Circuit and Voltage Waveforms
12
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
0 V or 3 V
A
DE
Y
D
R
B
Z
100 W
±1%
100 W
±1%
RE
Pulse Generator
15 ms duration
1% Duty Cycle
t , t £ 100 ns
0 V or 3 V
+
+
-
-
r
f
Figure 12. Test Circuit, Transient Overvoltage Test
DEVICE INFORMATION
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against
inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode,
most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver
or the receiver is re-enabled, the internal circuitry becomes active.
12
A
2
R
11
B
3
RE
Low-Power
Shutdown
4
DE
9
Y
5
D
10
Z
Figure 13. Low-Power Shutdown Logic Diagram
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
13
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
DEVICE INFORMATION (continued)
FUNCTION TABLES
SN65HVD53, SN65HVD54, SN65HVD55, SN65HVD58,
SN65HVD59 DRIVER
INPUTS
OUTPUTS
D
H
DE
Y
H
L
Z
L
H
L
H
L or open
H
H
Z
H
X
Z
L
Open
SN65HVD53, SN65HVD54, SN65HVD55, SN65HVD58,
SN65HVD59 RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
ENABLE
RE
OUTPUT
R
V
ID ≤ –0.2 V
L
L
?
–0.2 V < VID < –0.02 V
–0.02 V ≤ VID
X
L
L
H
Z
H
H
H
H or open
Open Circuit
Idle circuit
L
L
L
Short Circuit, VA = VB
SN65HVD50, SN65HVD51, SN65HVD52, SN65HVD56,
SN65HVD57 DRIVER
OUTPUTS
INPUT
D
Y
Z
H
L
H
L
L
L
H
H
Open
SN65HVD50, SN65HVD51, SN65HVD52, SN65HVD56,
SN65HVD57 RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
OUTPUT
R
V
ID ≤ –0.2 V
L
?
–0.2 V < VID < –0.02 V
–0.02 V ≤ VID
H
H
H
H
Open Circuit
Idle circuit
Short Circuit, VA = VB
14
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SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
RE Input
D and DE Input
VCC
VCC
130 kW
470 W
470 W
Input
Input
9 V
9 V
125 kW
A Input
B Input
VCC
VCC
R1
R1
22 V
R3
22 V
R3
Input
Input
R2
22 V
R2
22 V
R Output
Y and Z Outputs
VCC
VCC
16 V
5 W
Output
Output
16 V
9 V
R1/R2
R3
SN65HVD50, SN65HVD53, SN65HVD56, SN65HVD58
9 kΩ
45 kΩ
180 kΩ
SN65HVD51, SN65HVD52, SN65HVD54, SN65HVD55 SN65HVD57, 36 kΩ
SN65HVD58, SN65HVD59
15
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
TYPICAL CHARACTERISTICS
HVD50, HVD53
HVD51, HVD54
RMS Supply Current
vs
RMS Supply Current
vs
Signaling Rate
Signaling Rate
70
65
60
55
50
45
40
70
T
A
=25°C
R
= 54 W
L
T
=25°C
R
= 54 W
L
A
RE = V
C = 50 pF
L
R
= V
C = 50 pF
L
CC
E
CC
DE = V
DE = V
CC
CC
65
60
55
50
45
40
V
= 5.0 VDC
CC
V
= 5.0 VDC
CC
0
1
2
3
4
5
0
5
10
15
20
25
Signaling Rate (Mbps)
Signaling Rate (Mbps)
Figure 14.
Figure 15.
HVD52, HVD55
RMS Supply Current
vs
Signaling Rate
75
T
A
=25°C
R
= 54 W
L
RE = V
C = 50 pF
L
CC
DE = V
70
65
60
55
50
45
40
CC
V
= 5.0 VDC
CC
0
0.2
0.4
0.6
0.8
1
Signaling Rate (Mbps)
Figure 16.
16
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
HVD50, HVD53
Bus Input Current
vs
HVD51, HVD52, HVD54, HVD55
Bus Input Current
vs
Input Voltage
Input Voltage
60
40
20
0
250
T
A
= 25°C
T
A
= 25°C
RE = 0 V
RE = 0 V
DE = 0 V
200
150
100
50
DE = 0 V
0
V
= 5 V
V
= 5 V
-50
CC
CC
-20
-40
-60
-100
-150
-200
-250
-7
-4
-1
2
5
8
11
14
-7
-4
-1
2
5
8
11
14
V - Bus Input Voltage - V
I
V - Bus Input Voltage - V
I
Figure 17.
Figure 18.
Driver Low-Level Output Current
vs
Driver High-Level Output Current
vs
Low-Level Output Voltage
High-Level Output Voltage
0.12
0.01
-0.01
-0.03
-0.05
-0.07
-0.09
-0.11
-0.13
VCC = 5 V
DE = V
CC
VCC = 5 V
DE = V
CC
D = 0 V
0.1
D = 0 V
0.08
0.06
0.04
0.02
0
-0.02
0
1
2
3
4
5
0
1
2
3
4
5
V - High-Level Output Voltage - V
OH
V
- Low-Level Output Voltage - V
OL
Figure 19.
Figure 20.
17
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Driver Differential Output Voltage
Driver Output Current
vs
vs
Free-Air Temperature
Supply Voltage
2.9
60
50
40
30
20
10
0
T
A
= 25°C
R
= 54 W
VCC = 5 V
L
DE at V
2.8
D = V
CC
CC
D at V
DE = V
CC
CC
2.7
2.6
2.5
2.4
V
= 5 V
CC
0
1
2
3
4
5
6
-40
-15
10
35
60
85
T
A
- Free-Air Temperature - °C
V
CC
- Supply Voltage - V)
Figure 21.
Figure 22.
18
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666–SEPTEMBER 2005
APPLICATION INFORMATION
THERMAL CHARACTERISTICS OF IC PACKAGES
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
•
•
•
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 23.
Figure 23. Thermal Resistance
19
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
Drawing
SN65HVD53D
SN65HVD53DR
SN65HVD54D
SN65HVD54DR
SN65HVD55D
SN65HVD55DR
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
D
D
D
D
D
D
14
14
14
14
14
14
50
2500
50
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
2500
50
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
SN65HVD53D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD53DG4
SN65HVD53DR
SN65HVD53DRG4
SN65HVD54D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD54DG4
SN65HVD54DR
SN65HVD54DRG4
SN65HVD55D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD55DG4
SN65HVD55DR
SN65HVD55DRG4
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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