SN65HVD64RGTR [TI]
具有宽工作温度范围的 AISG® 3.0 开关键控同轴调制解调器收发器 | RGT | 16 | -40 to 120;
| 型号： | SN65HVD64RGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有宽工作温度范围的 AISG® 3.0 开关键控同轴调制解调器收发器 | RGT | 16 | -40 to 120 开关 调制解调器 |
| 文件： | 总28页 (文件大小：23571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSL88 – OCTOBER 2020
SN65HVD64
SN65HVD64 AISG® 开关键控同轴调制解调器收发器
1 特性
3 说明
• 3V 至 5.5V 电源范围
SN65HVD64 收发器对逻辑（基带）接口和适用于长同
轴介质的频率之间的信号进行调制和解调，以便无线设
备之间进行有线数据传输。
• 1.6V 至 5.5V 独立逻辑电源
•
–15dBm 至 +5dBm 宽输入动态范围
接收器
SN65HVD64 器件是一款集成 AISG 收发器，旨在满足
“天线接口标准组织 v2.0 和 v3.0 规范”的要求。
•
可在 0dBm 至 6dBm 范围内调节
驱动器为同轴电缆提供的功率
支持 AISG® V2.0 和 V3.0
低功耗待机模式
SN65HVD64 接收器集成了一个有源带通滤波器，这样
即使存在寄生频率组件仍然能够解调信号。该滤波器的
中心频率为 2.176MHz。
•
•
•
针对 RS-485 总线仲裁的
方向控制输出
发送器支持在 +0dBm 至 6dBm 的范围内调节为 50Ω
同轴电缆提供的输出功率。SN65HVD64 发送器符合
AISG 标准针对发射频谱的要求。
•
•
支持高达 115kbps 的信号传输速率
集成有源带通滤波器的中心频率
为 2.176MHz
该器件提供的方向控制输出使得对 RS-485 接口的总线
仲裁更加便捷。该器件为晶振集成了一个振荡器输入，
并且接受到振荡器的标准时钟输入。
•
支持 -40°C 至 120°C 环境温度
• 3mm × 3mm 16 引脚 VQFN 封装
器件信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
SN65HVD64
• AISG - 针对天线线路器件的接口
VQFN (16)
3.00mm × 3.00mm
•
•
塔顶放大器 (TMA)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VCC
普通调制解调器 (Modem) 接口
VL
3
13
1
SYNCOUT
9
RES
FILTER
14
XTAL1
XTAL
Buffer
OOK
MOD
OUTPUT
STAGE
12
TXOUT
PREAMP
15
2
XTAL2
TXIN
2.176–MHz
7
6
DIRSET1
DIRSET2
Control
Logic
FILTER
5
DIR
OOK
DEMOD
11
Buffer
RXIN
2.176–MHz
4
RXOUT
Buffer
COMP
RECEIVER
THRESHOLD
10
8
16
GND
BIAS
GND
方框图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFI7
SN65HVD64
ZHCSL88 – OCTOBER 2020
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Table of Contents
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................15
9 Application and Implementation..................................17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 18
10 Power Supply Recommendations..............................20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Documentation Support.......................................... 22
12.2 Receiving Notification of Documentation Updates..22
12.3 Support Resources................................................. 22
12.4 Trademarks.............................................................22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................7
6.7 Typical Characteristics................................................8
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................14
4 Revision History
DATE
REVISION
NOTES
October 2020
*
Initial release.
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5 Pin Configuration and Functions
VCC
13
8
7
GND
XTAL1 14
DIRSET1
Exposed
Pad
XTAL2
GND
15
16
6
5
DIRSET2
DIR
图 5-1. RGT Package, 16-Pin VQFN, Top View
表 5-1. Pin Functions
PIN
NO.
DESCRIPTION
NAME
TYPE
BIAS
DIR
10
5
O
O
Bias voltage output for setting driver output power by external resistors
Direction control output signal for bus arbitration
DIRSET1
DIRSET2
7
—
—
DIRSET1 and DIRSET2: Bits to set the duration of DIR
DIRSET[2:1]: [L:L] = 9.6 kbps; [L:H] = 38.4 kbps; [H:L] = 115 kbps; [H:H] = standby mode
6
8
GND
Ground
—
16
9
RES
P
I
Input voltage to adjust driver output power that is set by external resistors from BIAS pin to GND
Modulated input signal to the receiver
RXIN
RXOUT
SYNCOUT
TXIN
11
4
O
O
I
Digital data bit stream from receiver
1
Open-drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1 and XTAL2
Digital data bit stream to driver
2
TXOUT
VCC
12
13
3
O
P
P
I/O
Modulated output signal from the driver
Analog supply voltage for the device
VL
Logic supply voltage for the device
XTAL1
XTAL2
EP
14
15
—
I/O pins of the crystal oscillator. Connect a 4 × fC crystal between these pins or connect XTAL1 to an
8.704-MHz clock and connect XTAL2 to GND.
Exposed pad. Connection to ground plane is recommended for best thermal conduction.
—
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN
–0.5
–0.5
–0.3
–20
MAX
UNIT
V
Supply voltage, VCC and VL
Voltage at coax pins
6
6
VVL + 0.3
20
V
Voltage at logic pins
V
Logic output current
mA
TXOUT output current
SYNCOUT output current
Junction temperature, TJ
Continuous total power dissipation
Internally limited
Internally limited
170
See the Thermal Information
150
°C
°C
°C
(2)
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Applicable before the device is installed in the final product.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
5.5
UNIT
V
VCC
VL
Analog supply voltage
Logic supply voltage
1.6
5.5
V
VI(pp)
Input signal amplitude at RXIN
1.12
Vpp
TXIN, DIRSET1, DIRSET2
XTAL1, XTAL2
70%VL
VL
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
70%VCC
VCC
TXIN, DIRSET1, DIRSET2
XTAL1, XTAL2
0
0
30%VL
30%VCC
115
1/tUI
Data signaling rate
Oscillator frequency
9.6
kbps
MHz
FOSC
8.704
50
30 ppm
–30 ppm
Load impedance between TXOUT to RXIN
Load impedance between RXIN and GND at fC (channel)
Bias resistor between BIAS and RES
Bias resistor between RES and GND
Pullup resistor between SYNCOUT and VCC
Voltage at RES pin
Ω
Ω
ZLOAD
50
R1
4.1
10
kΩ
kΩ
kΩ
V
R2
RSYNC
VRES
CC
1
0.7
1.5
Coupling capacitance between RXIN and coax (channel)
Capacitance between BIAS and GND
Operating free-air temperature
220
1
nF
µF
°C
°C
CBIAS
TA
120
125
–40
–40
TJ
Junction temperature
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6.4 Thermal Information
VQFN
THERMAL METRIC(1)
UNIT
RGT 16 Pins
49.4
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
64.2
Junction-to-board thermal resistance
22.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.7
22.9
ψJB
RθJCbot
25
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
TXIN = L (active)
28
25
33
31
DIRSET1 = L
DIRSET2 = H
TXIN = H (quiescent)
ICC
Supply current
mA
TXIN = 115 kbps,
50% duty cycle
27
12
33
DIRSET1 = H, DIRSET2 = H (standby)
TXIN = H, RXIN = DC input
VTXIN = VL
17
50
IVL
Logic supply current
µA
dB
°C
°C
°C
PSRR
Receiver power supply rejection ratio
Thermal shutdown rising
45
143
123
18
60
156
136
20
TSD_RISE
TSD_FALL
TSD_HYS
LOGIC PINS
170
147
23
Thermal shutdown falling
Thermal shutdown hysteresis
High-level logic output voltage
(RXOUT, DIR)
IOH = –4 mA for VL > 2.4 V,
IOH = –2 mA for VL < 2.4 V
VOH
90%VVL
V
V
Low-level logic output voltage
(RXOUT, DIR)
IOL = 4 mA for VL > 2.4 V,
IOL = 2 mA for VL < 2.4 V
VOL
10%VVL
COAX DRIVER
Peak-to-peak output voltage at device pin
VRES = 1.5 V (Maximum setting)
VRES = 0.7 V (Minimum setting)
2.24
5
2.5
TXOUT
VO(PP)
VPP
1.17
1.3
(see 图 7-1)
VRES = 1.5 V
VRES = 0.7 V
At TXOUT
6
Peak-to-peak voltage at coax out
(see 图 7-1)
VO(PP)
dBm
0.3
1
–0.6
mVpp
dBm
VO(OFF)
Off-state output voltage
Output emissions
At coax out
–60
Coupled to coaxial cable with characteristic
impedance of 50 Ω, as shown in 图 6-1 (1) (2)
N/A
fO
Output frequency
2.176
MHz
ppm
Output frequency variation
100
450
∆f
–100
At 100 kHz
At 10 MHz
0.03
3.5
ZO
Output impedance
Ω
TXOUT is also protected by a thermal shutdown
circuit during short-circuit faults
| IOS
|
Short-circuit output current
300
mA
COAX RECEIVER
79
–18
11
112
–15
21
158
mVPP
dBm
kΩ
VIT
Input threshold
fIN = 2.176 MHz
f = fO
–12
ZIN
Input impedance
RECEIVER FILTER
fPB
Passband
VRXIN = 1.12VP_P
1.1
1.1
4.17
4.17
MHz
MHz
2.176-MHz carrier amplitude of 112.4 mVPP
frequency band of spurious components with 800
mVPP allowed.
,
fREJ
Receiver rejection range
Receiver noise filter time (slow bit rate)
Receiver noise filter time (fast bit rate)
DIRSET for 9.6 kbps
DIRSET for > 9.6 kbps
4
2
µs
µs
tnoise filter
XTAL AND SYNC
II
Input leakage current
Output low voltage
XTAL1, XTAL2, 0V < VIN < VCC
15
µA
V
–15
VOL
0.4
SYNCOUT, with 1-kΩ resistor from SYNCOUT to VCC
(1) Specified by design with a recommended 470-pF capacitor between RXIN and GND. Measurements above 150 MHz are determined
by setup.
(2) Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see 图 7-3.
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6.6 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
UNIT
µs
tpAQ, tpQA
tr, tf
Coax driver propagation delay
Coax receiver output rise/fall time
Receiver propagation delay
See 图 7-1
20
ns
CL = 15 pF, RL = 1 kΩ; see 图 7-1
See 图 7-2
tPHL, tPLH
5.5
11
µs
VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp,
50% duty cycle
40%
40%
60%
60%
Coax receiver output duty cycle
Direction control active duration
VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5 mVpp,
50% duty cycle
DIRSET2 = GND or OPEN, DIRSET1 = GND
or OPEN
1667
tDIR
µs
ns
DIRSET2 = GND, DIRSET1 = VL
DIRSET2 = VL, DIRSET1 = VL
417
137
Direction control skew
(DIR to RXOUT)
tDIRSKEW
270
tdis
ten
Standby disable delay
Standby enable delay
300 mVPP at 2.176 MHz on RXIN
300 mVPP at 2.176 MHz on RXIN
2
2
ms
ms
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6.7 Typical Characteristics
10
0
-50
-60
AISG Mask
AISG Mask
-10
-20
-30
-40
-50
-60
-70
-80
-70
-80
-90
-100
-110
-120
30M
130M
230M
Frequency (Hz)
330M
0
10M
20M
30M
Frequency (Hz)
D003
D002
50% Duty Cycle
CF = 470 pF
50% Duty Cycle
CF = 470 pF
图 6-2. High-Frequency Emissions Spectrum With
图 6-1. Low-Frequency Emissions Spectrum With
9.6-kbps Signaling Rate
9.6-kbps Signaling Rate
10
-50
AISG Mask
AISG Mask
0
-60
-70
-10
-20
-30
-40
-50
-60
-70
-80
-80
-90
-100
-110
-120
30M
130M
230M
Frequency (Hz)
330M
0
10M
20M
30M
Frequency (Hz)
D005
D004
50% Duty Cycle
CF = 470 pF
50% Duty Cycle
CF = 470 pF
图 6-4. High-Frequency Emissions Spectrum With
图 6-3. Low-Frequency Emissions Spectrum With
38.4-kbps Signaling Rate
38.4-kbps Signaling Rate
10
-50
AISG Mask
AISG Mask
0
-60
-70
-10
-20
-30
-40
-50
-60
-70
-80
-80
-90
-100
-110
-120
0
10M
20M
30M
30M
130M
230M
Frequency (Hz)
330M
Frequency (Hz)
D006
D007
50% Duty Cycle
CF = 470 pF
50% Duty Cycle
CF = 470 pF
图 6-5. Low-Frequency Emissions Spectrum With
图 6-6. High-Frequency Emissions Spectrum With
115.2-kbps Signaling Rate
115.2-kbps Signaling Rate
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40
35
30
25
20
15
10
5
6
5
4
3
2
1
0
-1
-2
0
0.1M
1M
10M
100M
0.7
0.9
1.1
VRES Voltage (V)
1.3
1.5
Frequency (Hz)
D008
D009
图 6-7. Transmitter Output Impedance
图 6-8. Transmit Power Adjustment
27
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
26.5
26
25.5
25
24.5
24
3
3.5
4 4.5
Supply Voltage (V)
5
5.5
3
3.5
4 4.5
Supply Voltage (V)
5
5.5
D011
D011
TXIN = VL
TXIN = VL
图 6-9. Supply Current vs Supply Voltage While
图 6-10. Supply Current vs Supply Voltage in
Transmitting
Standby Mode
13.2
13.1
13
7
6
5
4
3
2
1
0
12.9
12.8
12.7
12.6
12.5
12.4
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
3
3.5
4 4.5
Supply Voltage (V)
5
5.5
D012
D013
图 6-11. Supply Current vs Temperature in Standby
图 6-12. Transmitter Output Power vs Supply
Mode
Voltage
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7
6
5
4
3
2
1
0
30000
25000
20000
15000
10000
5000
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
100
1k
10k 100k
Frequency (Hz)
1M
5M
D014
D015
图 6-13. Transmitter Output Power vs Temperature
图 6-14. Receiver Input Impedance vs Frequency
0.18
360
RTXOUT = Stable Low
RTXOUT = Stable High
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
355
350
345
340
0.09
0.08
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D016
D017
图 6-15. Receiver Input Threshold vs Temperature
图 6-16. DIR Output Delay vs Temperature
60
60
50
40
30
20
10
0
56
52
48
44
40
-10
-7
-4
Receiver Input (dBm)
-1
2
5
-10
-7
-4
Receiver Input (dBm)
-1
2
5
D018
D019
图 6-17. Receiver Duty Cycle With 9.6 kbps
图 6-18. Receiver Duty Cycle With 115.2 kbps
Signaling Rate
Signaling Rate
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7 Parameter Measurement Information
Signal generator rate is 115 kbps, 50% duty cycle. Rise and fall times are less than 6 ns, and nominal output
levels are 0 V and 3 V. Coupling capacitor, CC, is 220 nF.
Driver Amplitude Adjust
RAMP
RES
XTAL2
TXOUT
2.176–MH_z
Crystal
XTAL2
50 Ω
TXIN
Signal
Generator
Coax Out
Cc
50 Ω
RXIN
V
L
0.5 V
L
TXIN
t
t
pAQ
pQA
VPP
0.5 VPP
TXOUT
图 7-1. Measurement of Modem Driver Output Voltage With 50-Ω Loads
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TXOUT
50 Ω
Coax In
2.176–MH_z
Generator
Received
Data Out
Cc
RXIN
Direction
Control
VPP
0.5 V
L
RXIN
V
L
0.5 V
L
RXOUT
t
t
PHL
PLH
V
L
L
0.5 V
DIR
t
DIRSKEW
图 7-2. Measurement of Modem Receiver Propagation Delays
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图 7-3. AISG Emissions Template
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8 Detailed Description
8.1 Overview
The SN65HVD64 transceiver modulates and demodulates signals between the logic (baseband) and a
frequency suitable for long coaxial media. The SN65HVD64 device is an integrated AISG transceiver designed
to meet the requirements of the Antenna Interface Standards Group v2.0 and v3.0 specification. The
SN65HVD64 receiver integrates an active bandpass filter to enable demodulation of signals even in the
presence of spurious frequency components. The filter has a 2.176-MHz center frequency. The transmitter
supports adjustable output power levels from 0 dBm to 6 dBm delivered to the 50-Ω coax cable. The
SN65HVD64 transmitter is compliant with the spectrum emission requirement provided by the AISG standard. A
direction control output facilitates bus arbitration for an RS-485 interface. This device integrates an oscillator
input for a crystal, and also accepts standard clock inputs to the oscillator.
8.2 Functional Block Diagram
VL
3
VCC
13
1
9
SYNCOUT
RES
FILTER
14
15
2
XTAL1
XTAL2
XTAL
Buffer
OOK
MOD
OUTPUT
STAGE
12
TXOUT
PREAMP
2.176–MHz
TXIN
7
6
DIRSET1
DIRSET2
Control
Logic
FILTER
5
DIR
OOK
DEMOD
11
Buffer
RXIN
2.176–MHz
4
RXOUT
Buffer
COMP
RECEIVER
THRESHOLD
10
8
16
GND
BIAS
GND
8.3 Feature Description
8.3.1 Coaxial Interface
The SN65HVD64 transceiver enables the transfer of data between radio equipment by modulating baseband
data to a carrier frequency of 2.176 MHz (per the AISG standard). The transmitter output amplitude can be
configured from 0 dBm to 6 dBm in order to communicate over a variety of different links, and the output
emissions spectrum is designed to be compliant to AISG limits. The receiver features an active bandpass filter
circuit that helps to separate the carrier frequency data from other spurious frequency components.
8.3.2 Reference Input
The 2.176-MHz modulation frequency is derived from an input reference that is nominally 8.704 MHz. The input
reference can come either from a crystal or from an oscillator circuit with a tolerance of up to 30 ppm.
8.3.3 RS-485 Direction Control
To facilitate bus arbitration of an RS-485 interface, the SN65HVD64 provides a direction control output that can
be used to control the enable/disable controls of an RS-485 transceiver. The direction control output
automatically toggles based on activity present on the coaxial input interface, and has an adjustable time
constant (controlled by the DIRSET1 and DIRSET2 pins) in order to accommodate various signaling rates.
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8.4 Device Functional Modes
If DIRSET1 and DIRSET2 are in a logic high state, the device will be in standby mode. While in standby mode,
the receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the RXOUT
state. The transmitter circuits are not active in standby mode, thus the TXOUT pin is idle regardless of the logic
state of TXIN. The supply current in standby mode is significantly reduced, allowing power savings when the
node is not transmitting.
When not in standby mode, the default power-on state is idle. When in idle mode, RXOUT is high, and TXOUT is
quiet. The device transitions to receive mode when a valid modulated signal is detected on the RXIN line or the
device transitions to transmit mode when TXIN goes low. The device stays in either receive or transmit mode
until DIR time-out (nominal 16 bit times) after the last activity on RXOUT or TXIN.
When in receive mode:
• RXOUT responds to all valid modulated signals on RXIN, whether from the local transmitter, a remote
transmitter, or long noise burst.
• TXOUT responds to TXIN, generating 2.176-MHz signals on TXOUT when TXIN is low, and TXOUT is quiet
when TXIN is high. (In normal operation, TXIN is expected to remain high when the device is in receive
mode.)
• The device stays in receive mode until 16 bit times after the last rising edge on RXOUT, caused by valid
modulated signal on the RXIN line.
When in transmit mode:
• RXOUT stays high, regardless of the input signal on RXIN.
• TXOUT responds to TXIN, generating 2.176-MHz signals on TXOUT when TXIN is low, and TXOUT is quiet
when TXIN is high.
• The device stays in transmit mode until 16 bit times after TXIN goes high.
表 8-1 shows the driver functions. 表 8-2 shows the receiver functions. 图 8-1 shows the transitions between
each state.
表 8-1. Driver Function Table
TXIN(1)
[DIRSET1, DIRSET2]
[L,L], [L,H] or [H,L]
[H,H]
TXOUT
COMMENT
Driver not active
H
L
< 1 mVPP at 2.176 MHz
VOPP at 2.176 MHz
< 1 mVPP at 2.176 MHz
Driver active
X
Standby mode
(1) H = High, L = Low, X = Indeterminate
表 8-2. Receiver and DIR Function Table
RXIN(1)
RXOUT
DIR
COMMENT (see 图 8-1)
IDLE mode (not transmitting or receiving)
< VIT at 2.176 MHz for longer than DIR time-out
RECEIVE mode (not already transmitting)
< VIT at 2.176 MHz for less than tDIR time-out
> VIT at 2.176 MHz for longer than tnoise filter
TRANSMIT mode (not already receiving)
X
H
L
No outgoing or incoming signal
H
L
H
H
Incoming 1 bit, DIR stays HIGH for DIR time-out
Incoming 0 bit, DIR output is HIGH
H
L
Outgoing message, DIR stays LOW for DIR time-out
(1) H = High, L = Low, X = Indeterminate
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Receive 0
Transmit 0
RXIN 9
RXOUT = L
DIR = H
TXOUT=Active
DIR = L
TXIN ;
IDLE
RXOUT = H
TXOUT=Idle
TXIN 9
TXIN ;
RXIN 9
RXIN ;
DIR = L
Transmit 1
Receive 1
DIR Timeout
DIR Timeout
TXOUT=Idle
DIR = L
RXOUT = H
DIR = H
图 8-1. State Transition Diagram
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Driver Amplitude Adjust
The SN65HVD64 device can provide up to 2.5 V of peak-to-peak output signal at the TXOUT pin to compensate
for potential loss within the external filter, cable, connections, and termination. External resistors are used to set
the amplitude of the modulated driver output signal. Resistors connected across RES and BIAS set the output
amplitude. The maximum peak-to-peak voltage at TXOUT is 2.5 V, corresponding to 6 dBm on the coaxial cable.
The TXOUT voltage level can be adjusted by choice of resistors to set the voltage at the RES pin according to 方
程式 1:
VTXOUT (VPP) = (2.5 VPP × VRES (V)) / 1.5 V VRES (V) = 1.5 V × R2 / (R1 + R2) VTXOUT (VPP) = 2.5 VPP
× R2 / (R1 + R2)
(1)
The voltage at the RES pin should be from 0.7 V to 1.5 V. Connect RES directly to the BIAS (R1 = 0 Ω) for
maximum output level of 2.5 VPP. This gives a minimum voltage level at TXOUT of 1.2 VPP, corresponding to
about 0 dBm at the coaxial cable. A 1-μF capacitor should be connected between the BIAS pin and GND. To
obtain a nominal power level of 3 dBm at the feeder cable as the AISG standard requires, use R1 = 4.1 kΩ and
R2 = 10 kΩ that provide 1.78 VPP at TXOUT.
9.1.2 Direction Control
In many applications the mast-top modem that receives data from the base distributes the received data through
an RS-485 network to several mast-top devices. When the mast-top modem receives the first logic 0 bit (active
modulated signal) it takes control of the mast-top RS-485 network by asserting the direction control signal. The
duration of the direction control assertion should be optimized to pass a complete message of length B bits at
the known signaling rate (1/tBIT) before relinquishing control of the mast-top RS-485 network. For example, if the
messages are 10 bits in length (B=10) and the signaling rate is 9600 bits per second (tBIT = 0.104 ms) then a
positive pulse of duration 1.7 ms is sufficient (with margin to allow for network propagation delays) to enable the
mast-top RS-485 drivers to distribute each received message. 图 9-1 shows the assertion of direction control.
Coax In
Data Out
Direction
图 9-1. Assertion of Direction Control
9.1.3 Direction Control Time Constant
The time constant for the direction control function can be set by the control mode pins, DIRSET1 and DIRSET2.
These pins should be set to correspond to the desired data rate. With no external connections to the control
mode pins, the internal time constant is set to the maximum value, corresponding to the minimum data rate.
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9.1.4 Conversion Between dBm and Peak-to-Peak Voltage
dBm = 20 × LOG10 [Volts-pp / SQRT(0.008 × Zo)] = 20 × LOG10 [VPP / 0.63] for Zo = 50 Ω
VPP = SQRT(0.008 × Zo) × 10(dBm/20) = 0.63 × 10(dBm/20) for Zo = 50 Ω
(2)
(3)
表 9-1 shows conversions between dBm and peak-to-peak voltage with a 50-Ω load, for various levels of
interest including reference levels from the 3GPP TS 25.461 Technical Specification.
表 9-1. Conversions Between dBM and Peak-to-Peak Voltage
SIGNAL ON COAX
dBm
VPP
1.12
0.89
0.71
0.16
0.11
0.08
0.006
Maximum Driver ON Signal
Nominal Driver ON Signal
Minimum Driver ON Signal
AISG Maximum Receiver Threshold
Nominal Receiver Threshold
Minimum Receiver Threshold
Maximum Driver OFF Signal
5
3
1
–12
–15
–18
–40
9.2 Typical Application
The AISG On-Off Keying (OOK) interface allows for command, control, and diagnostic information to be
communicated between a base station and the corresponding tower-mounted antennae. 图 9-2 shows a typical
application.
RF+
Modulated Signals +
Power (On Coax)
(Twisted Pair)
RS-485
Signals
Power
RF
Signals
Diagnostics
and Control
图 9-2. Typical AISG Application
9.2.1 Design Requirements
An AISG transceiver is used to convert between digital logic-level signals and RF signals. The AISG standard
requires an RF carrier frequency of 2.176 MHz with 100-ppm accuracy. The output signal of the driver, when
active, should be from 1 dBm to 5 dBm. The receiver must be designed such that the input threshold is from –
18 dBm to –12 dBm.
9.2.2 Detailed Design Procedure
To ensure accuracy of the carrier frequency, an input reference frequency equal to four times the carrier (that is,
8.704 MHz) should be connected to the XTAL1 or XTAL2 inputs. This signal can come from a crystal (connected
between XTAL1 and XTAL2) or from a PLL/clock generator circuit (connected to XTAL1 with XTAL2 grounded).
The frequency accuracy must be within 100 ppm.
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The driver output power level of the SN65HVD64 device can be adjusted through use of the RES pin. To align
with AISG requirements, a nominal power level of 3 dBm should be configured by connecting a 4.1-kΩ resistor
between RES and BIAS and a 10-kΩ resistor between RES and GND. 图 9-3 shows an example schematic.
8.704 MHz
VCC
39 pF
39 pF
0.1 ꢀF
VL
220 nF
470 pF
49.9 Ω
SYNCOUT
TXIN
TXOUT
RXIN
BIAS
VL
RXOUT
RES
4.1 kΩ
0.1 ꢀF
10 kΩ
图 9-3. SN65HVD64 Schematic
9.2.3 Application Curve
图 9-4 shows the application curve for the SN65HVD64 device.
图 9-4. SN65HVD64 Application Curve
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10 Power Supply Recommendations
The SN65HVD64 device has two power supply pins: VCC, which provides power to the analog circuitry, and VL,
which is a logic supply. VCC should be operated from 3 V to 5.5 V, while VL can range from 1.6 V to 5.5 V to
interface to different logic levels. Power supply decoupling capacitances of at least 0.1 µF should be placed as
close as possible to each power supply pin.
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11 Layout
11.1 Layout Guidelines
Best practices for high-speed PCB design should be observed because the coax interface to the SN65HVD64
device operates at RF. The RF signaling traces should have a controlled characteristic impedance that is well-
matched to the coaxial line. A continuous reference plane should be used to avoid impedance discontinuities.
Power and ground distribution should be done through planes rather than traces to decrease series resistance
and increase the effective decoupling capacitance on the power rails.
11.2 Layout Example
图 11-1. SN65HVD64 Layout
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
AISG® is a registered trademark of Antenna Interface Standards Group, Ltd.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65HVD64RGTR
ACTIVE
VQFN
RGT
16
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 120
HVD64
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RGT0016A
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
1.45 0.1
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4219032/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
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EXAMPLE BOARD LAYOUT
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.45)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
17
(2.8)
(0.475)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.475) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219032/A 02/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.34)
13
16
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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