SN65HVD73DR [TI]
3.3V、全双工 RS-485、12kV IEC ESD、20Mbps 数据速率，带使能功能 | D | 14 | -40 to 125;
| 型号： | SN65HVD73DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V、全双工 RS-485、12kV IEC ESD、20Mbps 数据速率，带使能功能 | D | 14 | -40 to 125 |
| 文件： | 总44页 (文件大小：1701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
具有 ±12kV IEC ESD 的 SN65HVD7x 3.3V 全双工 RS-485 收发器
1 特性
这些器件的每一个都组装有一个差分驱动器和一个差分
接收器，这两个器件由一个 3.3V 单电源供电运行。每
个驱动器和接收器都具有用于全双工总线通信设计的独
立输入和输出引脚。这些器件均具有宽共模电压范围，
因此非常适合长电缆上的多点 应用 。
1
•
提供 1/8 单元负载选项
一条总线上多达 256 个节点
总线 I/O 保护
–
•
–
–
–
> ±30kV 人体放电模式 (HBM) 保护
> ±12kV IEC61000-4-2 接触放电
> ±4kV IEC61000-4-4 快速瞬变脉冲
SN65HVD71、SN65HVD74 和 SN65HVD77 器件均
完全启用，无需外部的使能引脚。
•
工业工作温度范围：
–40°C 至 125°C
SN65HVD70、SN65HVD73 和 SN65HVD76 器件均
具有高电平有效的驱动器使能端和低电平有效的接收器
使能端。禁用驱动器和接收器后可获得低于 5µA 的低
待机电流。
•
•
用于噪声抑制的较大接收器滞后 (70mV)
低功耗
–
–
运行期间静态电流 < 1.1mA
低待机电源电流：10nA（典型值），
< 5µA（最大值）
这些器件额定运行温度范围为 -40°C 至 125°C。
器件信息(1)
•
•
•
针对热插拔应用的无干扰加电和断电 保护
器件型号
封装
MSOP (8)
封装尺寸（标称值）
与 3.3V 或 5V 控制器兼容的 5V 耐压逻辑输入
SN65HVD71
SN65HVD74
SN65HVD77
3.00mm × 3.00mm
优化了以下信号传输速率：
SOIC (8)
4.90mm × 3.91mm
3.00mm x 3.00mm
8.65mm x 3.91mm
400kbps（70、71）、20Mbps（73、74）、
50Mbps（76、77）
SN65HVD70
SN65HVD73
SN65HVD76
MSOP (10)
SOIC (14)
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
•
•
电子式电表
工业自动化
楼宇自动化
安防和监控
编码器和解码器
方框图
VCC
VCC
A
B
A
B
R
R
R
D
R
3 说明
RE
VCC
这些器件扩展了 RS-485 产品组合，其中包括一系列具
有坚固耐用的 3.3V 驱动器和接收器以及高级 ESD 保
护的全双工收发器。ESD 保护包括 > ±30kV 的 HBM
和 > ±12kV 的 IEC61000-4-2 接触放电。SN65HVD7x
器件的较大接收器滞后能够抑制传导差模噪声，其工作
温度范围广，在恶劣的工作环境下能够保持可靠性。
SN65HVD7x 器件采用标准 SOIC 封装以及小型
MSOP 封装。
DE
D
Z
Y
Z
Y
D
D
GND
GND
SN65HVD70,
SN65HVD73, and
SN65HVD76
SN65HVD71,
SN65HVD74, and
SN65HVD77
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEI9
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
www.ti.com.cn
目录
9.1 Overview ................................................................. 17
9.2 Functional Block Diagram ....................................... 17
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 17
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 20
11 Power Supply Recommendations ..................... 26
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 27
13 器件和文档支持 ..................................................... 28
13.1 器件支持................................................................ 28
13.2 相关链接................................................................ 28
13.3 接收文档更新通知 ................................................. 28
13.4 社区资源................................................................ 28
13.5 商标....................................................................... 28
13.6 静电放电警告......................................................... 28
13.7 Glossary................................................................ 28
14 机械、封装和可订购信息....................................... 28
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information — D Packages......................... 8
7.5 Thermal Information — DGS and DGK Packages.... 8
7.6 Power Dissipation ..................................................... 8
7.7 Electrical Characteristics........................................... 8
7.8 Switching Characteristics — 400 kbps...................... 9
7.9 Switching Characteristics — 20 Mbps .................... 10
7.10 Switching Characteristics — 50 Mbps .................. 10
7.11 Typical Characteristics.......................................... 11
Parameter Measurement Information ................ 13
Detailed Description ............................................ 17
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision F (April 2019) to Revision G
Page
•
•
Changed device numbers to the 8-Pin DGK package image ................................................................................................ 4
Changed device numbers to the 10-Pin DGS package image .............................................................................................. 5
Changes from Revision E (October 2014) to Revision F
Page
•
•
•
•
•
Changed the Pin Configuration images.................................................................................................................................. 4
Changed the Supply Voltage MAX value From: 5.5 V To 5 V in the Absolute Maximum Ratings ....................................... 7
Moved Storage Temperature From the ESD table to the Absolute Maximum Ratings ......................................................... 7
Changed the Hadleing Ratings table to ESD Ratings............................................................................................................ 7
Added Note: to Supply voltage in the Recommended Operating Conditions......................................................................... 7
Changes from Revision D (August 2014) to Revision E
Page
•
Updated the MSOP–10 logic diagram.................................................................................................................................... 5
Changes from Revision C (July 2014) to Revision D
Page
•
Updated the Device Comparison Table.................................................................................................................................. 3
Changes from Revision B (July 2014) to Revision C
Page
•
Updated SN65HVD70 and SN65HVD71 specifications to production values........................................................................ 3
2
版权 © 2014–2019, Texas Instruments Incorporated
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
www.ti.com.cn
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
Changes from Revision A (June 2014) to Revision B
Page
•
•
Updated the Device Comparison Table.................................................................................................................................. 3
SN65HVD74 device status changed from Product Preview to Production Data.................................................................... 3
Changes from Original (May 2014) to Revision A
Page
•
已更改 器件状态从产品预览更改为生产数据（混合状态）..................................................................................................... 1
5 Device Comparison Table
PART NUMBER(1)
SIGNALING RATE
DUPLEX
ENABLES
PACKAGE
NODES
SOIC-14
MSOP-10
SN65HVD70
up to 400 kbps
up to 400 kbps
up to 20 Mbps
up to 20 Mbps
up to 50 Mbps
up to 50 Mbps
Full
DE, RE
256
256
256
256
96
SOIC-8
MSOP-8
SN65HVD71
SN65HVD73
SN65HVD74
SN65HVD76
SN65HVD77
Full
Full
Full
Full
Full
None
DE, RE
None
SOIC-14
MSOP-10
SOIC-8
MSOP-8
SOIC-14
MSOP-10
DE, RE
None
SOIC-8
MSOP-8
96
(1) For device status, see the 机械、封装和可订购信息 section.
Copyright © 2014–2019, Texas Instruments Incorporated
3
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
www.ti.com.cn
6 Pin Configuration and Functions
SN65HVD71, SN65HVD74, SN65HVD77
8-Pin SOIC, D Package, and 8-Pin MSOP, DGK Package
(Top View)
SN65HVD1471
8-Pin SOIC, D Package
8
2
A
B
R
D
7
1
2
3
4
8
7
6
5
A
B
Z
Y
VCC
R
5
6
D
3
Y
Z
GND
Not to scale
Pin Functions — SOIC-8 and MSOP-8
PIN
TYPE
DESCRIPTION
NAME
NO.
1
VCC
R
Supply
3-V to 3.6-V supply
2
Digital output
Digital input
Receive data output
D
3
Driver data input
GND
Y
4
Reference potential
Bus output
Local device ground
5
Digital bus output, Y (Complementary to Z)
Digital bus output, Z (Complementary to Y)
Digital bus input, B (Complementary to A)
Digital bus input, A (Complementary to B)
Z
6
Bus output
B
7
Bus input
A
8
Bus input
4
Copyright © 2014–2019, Texas Instruments Incorporated
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
www.ti.com.cn
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
SN65HVD70, SN65HVD73, SN65HVD76
10-Pin MSOP, DGS Package
(Top View)
SN65HVD1470
10-Pin MSOP, DGS Package
3
R
RE
1
2
3
4
5
10
9
VCC
A
6
4
7
2
DE
8
B
9
D
7
Z
1
8
GND
6
Y
Not to scale
Pin Functions — MSOP–10
PIN
TYPE
DESCRIPTION
NAME
R
NO.
1
2
Digital output
Digital input
Digital input
Digital input
Receive data output
RE
DE
D
Receive enable Low
3
Driver enable High
4
Driver data input
GND
Y
5
Reference potential
Bus output
Bus output
Bus input
Local device ground
6
Digital bus output, Y (Complementary to Z)
Digital bus output, Z (Complementary to Y)
Digital bus input, B (Complementary to A)
Digital bus input, A (Complementary to B)
3-V to 3.6-V supply
Z
7
B
8
A
9
Bus input
VCC
10
Supply
Copyright © 2014–2019, Texas Instruments Incorporated
5
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
www.ti.com.cn
SN65HVD70, SN65HVD73, SN65HVD76
14-Pin SOIC, D Package
(Top View)
SN65HVD1470
14-Pin SOIC, D Package
NC
R
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
A
B
Z
Y
CC
CC
RE
DE
D
GND
GND
8
NC
Not to scale
Pin Functions — SOIC-14
PIN
TYPE
DESCRIPTION
NAME
NO.
1
NC
No connect
Not connected
8
R
2
Digital output
Digital input
Digital input
Digital input
Receive data output
Receive enable Low
Driver enable High
Driver data input
RE
DE
D
3
4
5
6(1)
7(1)
9
GND
Reference potential
Local device ground
Y
Z
B
A
Bus output
Bus output
Bus input
Bus input
Digital bus output, Y (Complementary to Z)
Digital bus output, Z (Complementary to Y)
Digital bus input, B (Complementary to A)
Digital bus input, A (Complementary to B)
10
11
12
13(2)
14(2)
VCC
Supply
3-V to 3.6-V supply
(1) Pin 6 and pin 7 are connected internally.
(2) Pin 13 and pin 14 are connected internally.
6
Copyright © 2014–2019, Texas Instruments Incorporated
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
www.ti.com.cn
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–13
MAX
5
UNIT
V
Supply voltage
Voltage
VCC
Range at any bus pin (A, B, Y, or Z)
16.5
5.7
V
Input voltage
Range at any logic pin (D, DE, or RE)
–0.3
–100
–24
V
Voltage input range, transient pulse, any bus pin (A, B, Y, or Z) through 100 Ω
Receiver output
100
24
V
Output current
mA
°C
°C
Junction temperature, TJ
170
150
Storage temperature range, Tstg
–65
See the Thermal
Information table
Continuous total power dissipation
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±8000
±1500
±300
UNIT
V
Human body model (HBM), per JEDEC specification JESD22-A114, all pins
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins
Machine model (MM), all pins
IEC 61000-4-2 ESD (Air-Gap Discharge), bus pins and GND(1)(2)
IEC 61000-4-2 ESD (Contact Discharge), bus pins and GND
IEC 61000-4-4 EFT (Fast transient or burst), bus pins and GND
IEC 60749-26 ESD (Human Body Model), bus pins and GND(2)
V
V
Electrostatic
discharge
V(ESD)
±12000
±12000
±4000
±30000
V
V
V
V
(1) By inference from contact-discharge results, see the Application and Implementation section
(2) Limited by tester capability.
7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
(1)
VCC
VI
Supply voltage
3
–7
2
3.3
3.6
12
V
V
(2)
Input voltage at any bus pin (separately or common mode)
VIH
VIL
VID
IO
High-level input voltage (Driver, driver enable, and receiver enable inputs)
Low-level input voltage (Driver, driver enable, and receiver enable inputs)
Differential input voltage
VCC
0.8
12
V
0
V
–12
–60
–8
54
V
Output current, Driver
60
mA
mA
Ω
IO
Output current, Receiver
8
RL
CL
Differential load resistance
60
50
Differential load capacitance
pF
kbps
HVD70, HVD71
400
20
1/tUI
Signaling rate
HVD73, HVD74
HVD76, HVD77
Mbps
°C
50
(3)
TA
TJ
Operating free-air temperature (See the Application and Implementation for thermal
–40
–40
125
information)
Junction Temperature
150
°C
(1) Exposure to conditions beyond the recommended operation maximum for extended periods may affect device reliability.
(2) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(3) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating because of internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches 170°C.
Copyright © 2014–2019, Texas Instruments Incorporated
7
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
www.ti.com.cn
7.4 Thermal Information — D Packages
THERMAL METRIC
D
D
Unit
(8 PINS)
(14 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
110.7
54.7
51.3
9.2
83.3
42.9
37.8
9.3
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Thermal shut-down junction temperature
ψJB
50.7
37.5
TJ(TSD)
170
°C
7.5 Thermal Information — DGS and DGK Packages
THERMAL METRIC
DGS
DGK
Unit
(10 PINS)
(8 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
165.5
37.7
86.4
1.4
168.7
62.2
89.5
7.4
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Thermal shut-down junction temperature
ψJB
84.8
87.9
TJ(TSD)
170
°C
7.6 Power Dissipation
PARAMETER
TEST CONDITIONS
VALUE
150
UNITS
HVD70, HVD71
HVD73, HVD74
HVD76, HVD77
HVD70, HVD71
HVD73, HVD74
HVD76, HVD77
HVD70, HVD71
HVD73, HVD74
HVD76, HVD77
RL = 300 Ω,
CL = 50 pF (driver)
Unterminated
RS-422 load
RS-485 load
180
mW
Power Dissipation
220
driver and receiver enabled,
VCC = 3.6 V, TJ = 150°C
50% duty cycle square-wave signal at
signaling rate:
190
RL = 100 Ω,
CL = 50 pF (driver)
PD
220
mW
mW
•
•
•
HVD70 and HVD71 at 400 kbps
HVD73 and HVD74 at 20 Mbps
HVD76 and HVD77 at 50 Mbps
250
230
RL = 54 Ω,
CL = 50 pF (driver)
255
285
7.7 Electrical Characteristics
over recommended operating range (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
2
MAX UNIT
RL = 60 Ω, 375 Ω on each
1.5
1.5
2
V
V
V
output to –7 V to 12 V, See 图 15
RL = 54 Ω (RS-485), See 图 16
RL = 100 Ω (RS-422) TJ ≥ 0°C,
|VOD
|
Driver differential output voltage magnitude
2
V
CC ≥ 3.2 V, See 图 16
Change in magnitude of driver differential output
voltage
Δ|VOD
|
RL = 54 Ω, CL = 50 pF, See 图 16
–50
1
0
VCC / 2
0
50
3
mV
V
VOC(SS) Steady-state common-mode output voltage
Change in differential driver output common-mode
voltage
ΔVOC
Center of two 27-Ω load resistors, See 图 16
–50
50
mV
VOC(PP) Peak-to-peak driver common-mode output voltage
500
15
mV
pF
COD
VIT+
Differential output capacitance
Positive-going receiver differential input voltage
threshold
(1)
See
-70
–20
mV
mV
mV
Negative-going receiver differential input voltage
threshold
(1)
VIT–
Vhys
–200
40
-140 See
70
Receiver differential input voltage threshold hysteresis
(VIT+ – VIT–
)
(1) Under any specific conditions, VIT+ is assured to be at least Vhys higher than VIT–
.
8
Copyright © 2014–2019, Texas Instruments Incorporated
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
www.ti.com.cn
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
Electrical Characteristics (continued)
over recommended operating range (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
VOL
Receiver high-level output voltage
Receiver low-level output voltage
IOH = –8 mA
IOL = 8 mA
2.4 VCC–0.3
0.2
V
0.4
3
V
Driver input, driver enable, and receiver enable input
current
II
–3
–1
µA
Receiver output high-impedance
current
HVD70, HVD73,
HVD76
IOZ
IOS
VO = 0 V or VCC, RE = VCC
1
µA
Driver short-circuit output current
–150
150
125
mA
VI = 12 V
VI = –7 V
VI = 12 V
VI = –7 V
75
–40
HVD70,
HVD73
–100
–267
VCC = 0 to ROC (max),
DE = GND
II
Bus input current (disabled driver)
µA
240
333
HVD76
–180
Driver and receiver
enabled
DE = VCC, RE = GND,
No load
750
350
650
0.1
1100
650
800
5
µA
µA
µA
µA
Driver enabled, receiver DE = VCC, RE = VCC
disabled No load
,
ICC
Supply current (quiescent)
Supply current (dynamic)
Driver disabled, receiver DE = GND, RE = GND,
enabled
No load
Driver and receiver
disabled
DE = GND, D = open,
RE = VCC, No load
See the Typical Characteristics section
Tsd
Thermal Shut-down junction temperature
170
°C
7.8 Switching Characteristics — 400 kbps
400-kbps devices (SN65HVD70, SN65HVD71) bit time ≥ 2 µs (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DRIVER
tr, tf
Driver differential output rise/fall time
Driver propagation delay
100 400 750
350 550
40
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See 图 17
Driver pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
50 200
300 750
See 图 18 and 图
19
HVD70
Receiver enabled
Receiver disabled
tPZH, tPZL
Driver enable time
3
8
RECEIVER
tr, tf
Receiver output rise/fall time
13
25
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
Receiver propagation delay time
Receiver pulse skew, |tPHL – tPLH
Receiver disable time
CL = 15 pF
See 图 20
70 110
7
|
tPLZ, tPHZ
45
60
tPZL(1)
tPZH(1)
tPZL(2)
tPZH(2)
,
Driver enabled
Driver disabled
See 图 21
See 图 22
20 115
HVD70
3
8
Receiver enable time
,
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7.9 Switching Characteristics — 20 Mbps
20-Mbps devices (SN65HVD73, SN65HVD74) bit time ≥ 50 ns (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DRIVER
tr, tf
Driver differential output rise/fall time
Driver propagation delay
4
4
7
10
0
14
20
4
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See 图 17
Driver pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
12
10
3
25
20
8
See 图 18 and 图
19
HVD73
Receiver enabled
Receiver disabled
tPZH, tPZL
Driver enable time
RECEIVER
tr, tf
Receiver output rise/fall time
5
60
0
10
90
5
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
Receiver propagation delay time
Receiver pulse skew, |tPHL – tPLH
Receiver disable time
CL = 15 pF
See 图 20
|
tPLZ, tPHZ
17
12
3
25
90
8
HVD73
Driver enabled
Driver disabled
See 图 21
See 图 22
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time
7.10 Switching Characteristics — 50 Mbps
50-Mbps devices (SN65HVD76, SN65HVD77) bit time ≥ 20 ns (over recommended operating conditions)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
DRIVER
tr, tf
Driver differential output rise/fall time
Driver propagation delay
2
3
3
10
0
6
16
3.5
20
20
8
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See 图 17
Driver pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
10
10
3
See 图 18 and 图
19
HVD76
Receiver enabled
Receiver disabled
tPZH, tPZL
Driver enable time
RECEIVER
tr, tf
Receiver output rise/fall time
1
3
25
0
6
40
2
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
Receiver propagation delay time
Receiver pulse skew, |tPHL – tPLH
Receiver disable time
CL = 15 pF
See 图 20
|
tPLZ, tPHZ
8
15
90
8
HVD76
Driver enabled
Driver disabled
See 图 21
See 图 22
8
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time
3
10
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7.11 Typical Characteristics
3.6
3.3
3
3.5
3
VOH
VOL
100 W Load Line
60 W Load Line
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2.5
2
1.5
1
0.5
0
0
10
20
30
Driver Output Current (mA)
40
50
60
70
80
90 100
0
10
20
30
Driver Output Current (mA)
40
50
60
70
80
90 100
D001
D002
图 1. Driver Output Voltage vs Driver Output Current
图 2. Driver Differential-Output Voltage vs Driver Output
Current
50
2.2
2.15
2.1
45
40
35
30
25
20
15
10
5
2.05
2
1.95
1.9
0
-7
-5
-3
-1
Driver Common-Mode Voltage (V)
1
3
5
7
9
11
0
0.5
1
1.5
Supply Voltage (V)
2
2.5
3
3.5
D003
D004
图 3. Driver Differential-Output Voltage vs Driver Common-
图 4. Driver Output Current vs Supply Voltage
Mode Voltage
360
355
350
345
340
335
330
325
320
315
360
355
350
345
340
335
330
325
320
315
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D009
D010
图 5. SN65HVD70, SN65HVD71 Driver Rise and Fall Time vs
图 6. SN65HVD70, SN65HVD71 Driver Propagation Delay vs
Temperature
Temperature
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Typical Characteristics (接下页)
10
9
8
7
6
5
4
3
2
1
0
14
12
10
8
6
4
2
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D005
D006
图 7. SN65HVD73, SN65HVD74 Driver Rise and Fall Time vs
图 8. SN65HVD73, SN65HVD74 Driver Propagation Delay vs
Temperature
Temperature
4
3.5
3
12
10
8
2.5
2
6
1.5
1
4
2
0.5
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D011
D012
图 9. SN65HVD76, SN65HVD77 Driver Rise and Fall Time vs
图 10. SN65HVD76, SN65HVD77 Driver Propagation Delay vs
Temperature
Temperature
80
70
60
50
40
30
20
10
0
42
41.8
41.6
41.4
41.2
41
0
0.05
0.1
0.15
Signaling Rate (Mbps)
0.2
0.25
0.3
0.35
0.4
0
2
4
6
8
Signaling Rate (Mbps)
10
12
14
16
18
20
D013
D007
VCC = 3.3 V
TA = 25°C
图 11. SN65HVD70, SN65HVD71 Supply Current vs Signal
图 12. SN65HVD73, SN65HVD74 Supply Current vs Signal
Rate
Rate
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Typical Characteristics (接下页)
80
70
60
50
40
30
20
10
0
4
3.5
3
2.5
2
1.5
1
VCM = 12 V
VCM = 0 V
VCM = -7 V
0.5
0
0
5
10
15
20
25
30
Signaling Rate (Mbps)
35
40
45
50
-150
-130
-110 -90
Differential Input Voltage (mV)
-70
-50
D014
D008
VCC = 3.3 V
TA = 25°C
图 13. SN65HVD76, SN65HVD77 Supply Current vs Signal
图 14. Receiver Output vs Input
Rate
8 Parameter Measurement Information
The input generator rate is 100 kbps with 50% duty cycle, than 6-ns rise and fall times, and 50-Ω output
impedance.
375 W ±1%
VCC
DE
Y
Z
D
VOD
0 V or 3 V
60 W ±1%
+
_
–7 V < V(test) < 12 V
375 W ±1%
S0301-01
图 15. Measurement of Driver Differential Output Voltage With Common-Mode Load
V(Y)
Y
RL / 2
Y
V(Z)
Z
D
VOD
0 V or 3 V
VOC(PP)
DVOC(SS)
Z
RL / 2
VOC
CL
VOC
S0302-01
图 16. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
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Parameter Measurement Information (接下页)
50%
50%
Y
Z
»
»
W
W
图 17. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3 V
Y
S1
VO
D
VI
50%
50%
3 V
Z
0 V
DE
RL = 110 W
± 1%
CL = 50 pF ±20%
tPZH
VOH
90%
Input
Generator
CL Includes Fixture
50 W
VI
and Instrumentation
Capacitance
VO
50%
» 0 V
tPHZ
S0304-01
D at 3 V to test non-inverting output, D at 0 V to test inverting output.
图 18. Measurement of Driver Enable and Disable Times with Active-High Output and Pulldown Load
3 V
RL = 110 W
±1%
» 3 V
Y
Z
VI
50%
50%
S1
D
VO
3 V
0 V
tPZL
tPLZ
DE
CL = 50 pF ±20%
» 3 V
Input
Generator
VI
50 W
CL Includes Fixture
VO
50%
and Instrumentation
Capacitance
10%
VOL
S0305-01
D at 0 V to test non-inverting output, D at 3 V to test inverting output.
图 19. Measurement of Driver Enable and Disable Times with Active-Low Output and Pullup Load
3 V
A
B
VI
50%
50%
VO
R
Input
Generator
50 W
0 V
VI
tPLH
tPHL
1.5 V
0 V
CL = 15 pF ±20%
VOH
RE
90% 90%
VO
50%
10%
50%
10%
VOL
CL Includes Fixture
tr
tf
and Instrumentation
Capacitance
S0306-01
图 20. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
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Parameter Measurement Information (接下页)
3 V
DE
VCC
Y
Z
A
B
VO
1 kW ± 1%
CL = 15 pF ±20%
R
D
0 V or 3 V
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
3 V
VI
50%
50%
0 V
tPZH(1)
tPHZ
VOH
D at 3 V
S1 to GND
90%
VO
50%
» 0 V
tPZL(1)
tPLZ
VCC
D at 0 V
S1 to VCC
VO
50%
10%
VOL
S0307-01
图 21. Measurement of Receiver Enable and Disable Times With Driver Enabled
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Parameter Measurement Information (接下页)
VCC
A
B
VO
0 V or 1.5 V
1.5 V or 0 V
1 kW ± 1%
CL = 15 pF ±20%
R
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
3 V
VI
50%
0 V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to GND
VO
50%
GND
VCC
tPZL(2)
A at 0 V
B at 1.5 V
S1 to VCC
VO
50%
VOL
S0308-01
图 22. Measurement of Receiver Enable Times With Driver Disabled
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9 Detailed Description
9.1 Overview
The SN65HVD70, SN65HVD71, SN65HVD73, SN65HVD74, SN65HVD76, and SN65HVD77 devices are low-
power, full-duplex RS-485 transceivers available in three speed grades suitable for data transmission up to 400
kbps, 20 Mbps, and 50 Mbps.
The SN65HVD71, SN65HVD74, and SN65HVD77 are fully enabled with no external enabling pins. The
SN65HVD70, SN65HVD73, and SN65HVD76 have active-high driver enables and active-low receiver enables. A
standby current of less than 5 µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagram
VCC
VCC
A
B
A
B
R
R
R
D
R
RE
VCC
DE
D
Z
Y
Z
Y
D
D
GND
GND
图 23. Block Diagram
SN65HVD70, SN65HVD73, and SN65HVD76
图 24. Block Diagram
SN65HVD71, SN65HVD74, and SN65HVD77
9.3 Feature Description
Internal ESD protection circuits protect the transceiver against Electrostatic Discharges (ESD) according to
IEC61000-4-2 of up to ±12 kV, and against electrical fast transients (EFT) according to IEC61000-4-4 of up to ±4
kV.
The SN65HVD7x full-duplex family provides internal biasing of the receiver input thresholds in combination with
large input-threshold hysteresis. At a positive input threshold of VIT+ = –20 mV and an input hysteresis of Vhys
=
40 mV, the receiver output remains logic high under a bus-idle or bus-short condition even in the presence of
120 mVPP differential noise without the need for external failsafe biasing resistors.
Device operation is specified over a wide temperature range from –40°C to 125°C.
9.4 Device Functional Modes
For the SN65HVD70, SN65HVD73, and SN65HVD76, when the driver enable pin, DE, is logic high, the
differential outputs Y and Z follow the logic states at data input D. A logic high at D causes Y to turn high and Z
to turn low. In this case the differential output voltage defined as VOD = V(Y) – V(Z) is positive. When D is low, the
output states reverse, Z turns high, Y becomes low, and VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pulldown resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pullup resistor to VCC, thus, when left open while the driver is enabled, output Y
turns high and Z turns low.
表 1. Driver Function Table SN65HVD70, SN65HVD73, SN65HVD76
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
Y
Z
L
H
H
H
L
Actively drives the bus high
Actively drives the bus low
Driver disabled
L
X
H
L
H
Z
Z
L
Z
Z
H
X
OPEN
H
Driver disabled by default
Actively drives the bus high by default
OPEN
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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT–, the
receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
表 2. Receiver Function Table SN65HVD70, SN65HVD73, SN65HVD76
DIFFERENTIAL INPUT
VID = V(A) – V(B)
VIT+ < VID
ENABLE
OUTPUT FUNCTION
R
RE
L
H
?
Receives valid bus High
VIT– < VID < VIT+
VID < VIT–
L
Indeterminate bus state
Receives valid bus Low
Receiver disabled
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
For the SN65HVD71, HVD74, and HVD77, the driver and receiver are fully enabled, thus the differential outputs
Y and Z follow the logic states at data input D at all times. A logic high at D causes Y to turn high and Z to turn
low. In this case the differential output voltage defined as VOD = V(Y) – V(Z) is positive. When D is low, the output
states reverse, Z turns high, Y becomes low, and VOD is negative. The D pin has an internal pullup resistor to
VCC, thus, when left open while the driver is enabled, output Y turns high and Z turns low.
表 3. Driver Function Table SN65HVD71, SN65HVD74, SN65HVD77
INPUT
OUTPUTS
FUNCTION
D
H
Y
H
L
Z
L
Actively drives the bus High
L
H
L
Actively drives the bus Low
OPEN
H
Actively drives the bus High by default
When the differential input voltage defined as VID = V(A) – V(B) is positive and higher than the positive input
threshold, VIT+, the receiver output, R, turns high. When VID is negative and less than the negative input
threshold, VIT–, the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate.
Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected
from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
表 4. Receiver Function Table SN65HVD71, SN65HVD74, SN65HVD77
DIFFERENTIAL INPUT
VID = V(A) – V(B)
VIT+ < VID
OUTPUT
FUNCTION
R
H
?
Receives valid bus High
Indeterminate bus state
Receives valid bus Low
Fail-safe high output
Fail-safe high output
Fail-safe high output
VIT– < VID < VIT+
VID < VIT–
L
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
H
H
H
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9.4.1 Equivalent Circuits
V
V
CC
CC
1 Mꢀ
1.5 kꢀ
1.5 kꢀ
D, RE
DE
1 Mꢀ
9 V
9 V
图 25. D and RE Inputs
图 26. DE Input
V
CC
V
CC
R2
R2
R1
R1
R
A
B
R
9 V
16 V
R3
R3
图 27. R Output
图 28. Receiver Inputs
V
CC
Y
Z
16 V
图 29. Driver Outputs
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN65HVD7x family consists of full-duplex RS-485 transceivers commonly used for asynchronous data
transmissions. Full-duplex implementation requires two signal pairs (four wires), and allows each node to
transmit data on one pair while simultaneously receiving data on the other pair.
To eliminate line reflections, each cable end is terminated with a termination resistor, R(T), whose value matches
the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data
rates over longer cable length.
Y
Z
A
B
R
(T)
R
D
R
R
R
(T)
DE
RE
Master
R
Slave
D
RE
D
DE
D
B
A
Z
Y
R
R
(T)
(T)
A
B
Z
Y
R
Slave
D
R RE DE D
图 30. Typical RS-485 Network With SN65HVD7x Full-Duplex Transceivers
10.2 Typical Application
A full-duplex RS-485 network consists of multiple transceivers connecting in parallel to two bus cables. On one
signal pair, a master driver transmits data to multiple slave receivers. The master driver and slave receivers may
remain fully enabled at all times. On the other signal pair, multiple slave drivers transmit data to the master
receiver. To avoid bus contention, the slave drivers must be intermittently enabled and disabled such that only
one driver is enabled at any time, as in half-duplex communication. The master receiver may remain fully
enabled at all times.
Because the driver may not be disabled, only one driver should be connected to the bus when using the
SN65HVD71, SN65HVD74, or SN65HVD77 device.
Master Enable Control
Slave Enable Control
VCC
VCC
R
A
B
R
A
B
R
R
RE
RE
DE
D
DE
D
VCC
Z
Y
Z
Y
D
D
GND
GND
图 31. Full-Duplex Transceiver Configurations
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Typical Application (接下页)
10.2.1 Design Parameters
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 ft and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
图 32. Cable Length vs Data Rate Characteristic
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in 公式 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
v is the signal velocity of the cable or trace as a factor of c
c is the speed of light (3 × 108 m/s)
(1)
Per 公式 1, 表 5 lists the maximum cable-stub lengths for the minimum-driver output rise-times of the
SN65HVD7x full-duplex family of transceivers for a signal velocity of 78%.
表 5. Maximum Stub Length
DEVICE
MINIMUM DRIVER OUTPUT
RISE TIME (ns)
MAXIMUM STUB LENGTH
(m)
2.34
2.34
0.1
(ft)
7.7
SN65HVD70
SN65HVD71
SN65HVD73
SN65HVD74
SN65HVD76
SN65HVD77
100
100
4
7.7
0.3
4
0.1
0.3
2
0.05
0.05
0.15
0.15
2
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10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the SN65HVD7x family consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
10.2.1.4 Receiver Failsafe
The differential receivers of the SN65HVD7x family are failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a Low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT+, VIT–, and Vhys (the separation between VIT+ and VIT–). As shown in the Electrical Characteristics table,
differential signals more negative than –200 mV will always cause a low receiver output, and differential signals
more positive than 200 mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output will
be High. Only when the differential input is more than Vhys below VIT+ will the receiver output transition to a Low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, Vhys, as well as the value of VIT+
.
R
Vhysmin
40 mV
V
ID
(mV)
œ60
œ20
0
60
Vnmax = 120 mVpp
图 33. SN65HVD7x Noise Immunity Under Bus Fault Conditions
10.2.1.5 Transient Protection
The bus pins of the SN65HVD7x full-duplex transceiver family include on-chip ESD protection against ±30-kV
HBM and ±12-kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD
test is far more severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower
discharge resistance, R(D), of the IEC model produce significantly higher discharge currents than the HBM model.
As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method.
Although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred
from contact discharge test results.
22
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SN65HVD74, SN65HVD76, SN65HVD77
www.ti.com.cn
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
图 34. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
图 35 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automations.
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
图 35. Power Comparison of ESD, EFT, and Surge Transients
In the case of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
图 36 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse
train that is commonly applied during compliance testing.
版权 © 2014–2019, Texas Instruments Incorporated
23
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
www.ti.com.cn
1000
100
10
Surge
1
EFT Pulse Train
0.1
0.01
10-3
10-4
10-5
10-6
EFT
ESD
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
图 36. Comparison of Transient Energies
10.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is therefore necessary. 图 37 shows a protection circuit against 16-kV ESD, 4-kV EFT, and 1-kV surge
transients.
3.3 V
100 nF
R1
TVS
V
CC
A
10 kꢀ 10 kꢀ
R
RxD
B
RE
DIR
R2
MCU/
UART
SN65HVD7x
R1
DE
D
DIR
TxD
TVS
Z
Y
GND
10 kꢀ
R2
图 37. Transient Protection Against ESD, EFT, and Surge transients
24
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SN65HVD74, SN65HVD76, SN65HVD77
www.ti.com.cn
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
表 6. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
3.3-V, full-duplex RS-485
transceiver
SN65HVD7xD
TI
R1
10-Ω, pulse-proof thick-film CRCW0603010RJNEAHP
resistor
Vishay
Bourns
R2
TVS
Bidirectional 400-W
transient suppressor
CDSOT23-SM712
10.2.3 Application Curves
D
D
VOD
VOD
R
R
RL = 60 Ω
RL = 60 Ω
图 39. SN65HVD73 and SN65HVD74, 20 Mbps
图 38. SN65HVD70 and SN65HVD71, 500 kbps
D
VOD
R
RL = 60 Ω
图 40. SN65HVD76 and SN65HVD77, 50 Mbps
版权 © 2014–2019, Texas Instruments Incorporated
25
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
www.ti.com.cn
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76333 is a linear voltage regulator
suitable for the 3.3-V supply.
12 Layout
12.1 Layout Guidelines
On-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and surge
transients occurring in industrial environments. Therefore robust and reliable bus node design requires the use of
external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz, high-
frequency layout techniques must be applied during PCB design.
For successful PCB design, begin with the design of the protection circuit (see 图 41).
1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART,
controller ICs on the board (see 图 41).
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance (see 图 41).
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in theses lines during
transient events (see 图 41).
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up (see 图 41).
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
26
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SN65HVD74, SN65HVD76, SN65HVD77
www.ti.com.cn
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
12.2 Layout Example
GND
5
C
4
V
or GND
CC
7
6
R
1
R
7
TVS
R
MCU
5
R
7
SN65HVD7x
R
6
R
7
1
R
TVS
R
5
V
or GND
CC
GND
GND
图 41. SN65HVD7x Layout Example
版权 © 2014–2019, Texas Instruments Incorporated
27
SN65HVD70, SN65HVD71, SN65HVD73
SN65HVD74, SN65HVD76, SN65HVD77
ZHCSCM6G –MAY 2014–REVISED OCTOBER 2019
www.ti.com.cn
13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 7. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
单击此处
单击此处
单击此处
样片与购买
单击此处
单击此处
单击此处
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
单击此处
单击此处
单击此处
SN65HVD70
SN65HVD71
SN65HVD73
SN65HVD74
SN65HVD76
SN65HVD77
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
28
版权 © 2014–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65HVD70D
SN65HVD70DGS
SN65HVD70DGSR
SN65HVD70DR
SN65HVD71D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
DGS
DGS
D
14
10
10
14
8
50
80
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
HVD70
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAUAG
NIPDAUAG
NIPDAU
VD70
2500 RoHS & Green
2500 RoHS & Green
VD70
HVD70
HVD71
VD71
SOIC
D
75
80
RoHS & Green
RoHS & Green
NIPDAU
SN65HVD71DGK
SN65HVD71DGKR
SN65HVD71DR
SN65HVD73D
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAUAG
NIPDAUAG
NIPDAU
8
2500 RoHS & Green
2500 RoHS & Green
VD71
8
HVD71
HVD73
VD73
SOIC
D
14
10
10
14
8
50
80
RoHS & Green
RoHS & Green
NIPDAU
SN65HVD73DGS
SN65HVD73DGSR
SN65HVD73DR
SN65HVD74D
VSSOP
VSSOP
SOIC
DGS
DGS
D
NIPDAUAG
NIPDAUAG
NIPDAU
2500 RoHS & Green
2500 RoHS & Green
VD73
HVD73
HVD74
VD74
SOIC
D
75
80
RoHS & Green
RoHS & Green
NIPDAU
SN65HVD74DGK
SN65HVD74DGKR
SN65HVD74DR
SN65HVD76D
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAUAG
NIPDAUAG | SN
NIPDAU
8
2500 RoHS & Green
2500 RoHS & Green
VD74
8
HVD74
HVD76
VD76
SOIC
D
14
10
10
14
50
80
RoHS & Green
RoHS & Green
NIPDAU
SN65HVD76DGS
SN65HVD76DGSR
SN65HVD76DR
VSSOP
VSSOP
SOIC
DGS
DGS
D
NIPDAUAG
NIPDAUAG
NIPDAU
2500 RoHS & Green
2500 RoHS & Green
VD76
HVD76
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65HVD77D
SN65HVD77DGK
SN65HVD77DGKR
SN65HVD77DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
8
8
8
8
75
80
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
HVD77
Samples
Samples
Samples
Samples
DGK
DGK
D
NIPDAUAG
NIPDAUAG
NIPDAU
VD77
VD77
HVD77
2500 RoHS & Green
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
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25-Oct-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD70DGSR
SN65HVD70DR
VSSOP
SOIC
DGS
D
10
14
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
12.4
12.5
12.4
12.4
12.5
12.4
16.4
12.4
12.5
5.3
6.5
5.3
6.4
5.3
5.3
6.4
5.3
6.5
5.3
6.4
3.4
9.0
3.4
5.2
3.4
3.4
5.2
3.4
9.0
3.4
5.2
1.4
2.1
1.4
2.1
1.4
1.4
2.1
1.4
2.1
1.4
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
16.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
SN65HVD71DGKR
SN65HVD71DR
VSSOP
SOIC
DGK
D
8
SN65HVD73DGSR
SN65HVD74DGKR
SN65HVD74DR
VSSOP
VSSOP
SOIC
DGS
DGK
D
10
8
8
SN65HVD76DGSR
SN65HVD76DR
VSSOP
SOIC
DGS
D
10
14
8
SN65HVD77DGKR
SN65HVD77DR
VSSOP
SOIC
DGK
D
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65HVD70DGSR
SN65HVD70DR
VSSOP
SOIC
DGS
D
10
14
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
364.0
340.5
364.0
340.5
364.0
364.0
340.5
366.0
340.5
364.0
340.5
364.0
336.1
364.0
336.1
364.0
364.0
336.1
364.0
336.1
364.0
336.1
27.0
32.0
27.0
25.0
27.0
27.0
25.0
50.0
32.0
27.0
25.0
SN65HVD71DGKR
SN65HVD71DR
VSSOP
SOIC
DGK
D
8
SN65HVD73DGSR
SN65HVD74DGKR
SN65HVD74DR
VSSOP
VSSOP
SOIC
DGS
DGK
D
10
8
8
SN65HVD76DGSR
SN65HVD76DR
VSSOP
SOIC
DGS
D
10
14
8
SN65HVD77DGKR
SN65HVD77DR
VSSOP
SOIC
DGK
D
8
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
SN65HVD70D
SN65HVD70DGS
SN65HVD71D
D
DGS
D
SOIC
VSSOP
SOIC
14
10
8
50
80
75
80
50
80
75
80
50
80
75
80
507
330
507
330
507
330
507
330
507
330
507
330
7.85
6.55
8
3750
500
2.24
2.88
4.32
2.88
2.24
2.88
4.32
2.88
2.24
2.88
4.32
2.88
3940
500
SN65HVD71DGK
SN65HVD73D
DGK
D
VSSOP
SOIC
8
6.55
7.85
6.55
8
14
10
8
3750
500
SN65HVD73DGS
SN65HVD74D
DGS
D
VSSOP
SOIC
3940
500
SN65HVD74DGK
SN65HVD76D
DGK
D
VSSOP
SOIC
8
6.55
7.85
6.55
8
14
10
8
3750
500
SN65HVD76DGS
SN65HVD77D
DGS
D
VSSOP
SOIC
3940
500
SN65HVD77DGK
DGK
VSSOP
8
6.55
Pack Materials-Page 3
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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Copyright © 2023，德州仪器 (TI) 公司
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