SN65LBC170DWR [TI]
TRIPLE DIFFERENTIAL TRANSCEIVERS; 三重微分收发器
| 型号： | SN65LBC170DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE DIFFERENTIAL TRANSCEIVERS |
| 文件： | 总17页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
SN65LBC170DB (marked as BL170)
SN75LBC170DB (marked as BL170)
D
D
D
D
Three Differential Transceivers in One
Package
(TOP VIEW)
†
Signaling Rates Up to 30 Mbps
Low Power and High Speed
1D
1DIR
NC
1B
1A
NC
V
1
2
3
4
5
6
7
8
16
15
14
13
12
Designed for TIA/EIA-485, TIA/EIA-422, ISO
8482, and ANSI X3.277 (HVD SCSI Fast–20)
Applications
GND
2D
CC
2B
D
D
Common-Mode Bus Voltage Range
–7 V to 12 V
2DIR
3D
11 2A
10 3B
ESD Protection on Bus Terminals
Exceeds 12 kV
3DIR
9
3A
D
D
D
D
Driver Output Current up to ±60 mA
SN65LBC170DW (marked as 65LBC170)
SN75LBC170DW (marked as 75LBC170)
Thermal Shutdown Protection
(TOP VIEW)
Driver Positive and Negative Current
Limiting
1D
1DIR
NC
1
2
3
4
5
6
7
8
9
10
20 1B
Power-Up, Power-Down Glitch-Free
Operation
19
18
17
16
15
14
13
12
11
1A
NC
NC
D
Pin-Compatible With the SN75ALS170
GND
NC
D
Available in Shrink Small-Outline Package
V
CC
2D
2B
2A
3B
3A
NC
description
2DIR
NC
The SN65LBC170 and SN75LBC170 are
3D
monolithic integrated circuits designed for
bidirectional data communication on multipoint
bus-transmission lines. Potential applications
include serial or paralleldatatransmission, cabled
peripheral buses with twin axial, ribbon, or
twisted-pair cabling. These devices are suitable
for FAST-20 SCSI and can transmit or receive
data pulses as short as 25 ns, with skew less
than 3 ns.
3DIR
NC – No internal connection
logic diagram
1DIR
1A
1B
1D
These devices combine three 3-state differential
line drivers and three differential input line
receivers, all of which operate from a single 5-V
power supply.
2DIR
2A
2B
The driver differential outputs and the receiver
differential inputs are connected internally to form
three differential input/output (I/O) bus ports that
are designed to offer minimum loading to the bus
2D
3DIR
3A
3B
whenever the driver is disabled or V = 0. These
CC
ports feature a wide common-mode voltage range
making the device suitable for party-line
applications over long cable runs.
3D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
description (continued)
The driver’s active-high enable and the receiver’s active-low enable are tied together internally and provide a
direction input for each driver/receiver pair.
The SN75LBC170 is characterized for operation over the temperature range of 0°C to 70°C. The SN65LBC170
is characterized for operation over the temperature range of –40°C to 85°C.
†
AVAILABLE OPTIONS
PACKAGE
PLASTIC SHRINK SMALL-OUTLINE
T
PLASTIC SMALL-OUTLINE
(JEDEC MS-013)
A
(JEDEC MO-150)
SN75LBC170DB
SN65LBC170DB
0°C to 70°C
SN75LBC170DW
SN65LBC170DW
–40°C to 85°C
†
Add R suffix for taped and reel
Function Tables
EACH DRIVER
EACH RECEIVER
INPUT
D
ENABLE
DIR
OUTPUTS
DIFFERENTIAL INPUT ENABLE OUTPUT
(V –V )
DIR
D
A
H
L
B
A
B
V
≥ 0.2 V
L
L
L
H
L
H
?
H
H
L
ID
–0.2 V < V < 0.2 V
L
OPEN
X
H
H
H
H
Z
ID
≤ –0.2 V
V
ID
L
L
X
Z
H
L
Z
X
OPEN
X
OPEN
X
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
A INPUT
B INPUT
DIR INPUTS
V
CC
V
V
CC
CC
4 kΩ
4 kΩ
100 kΩ
16 V
16 V
18 kΩ
18 kΩ
Input
Input
1 kΩ
Input
100 kΩ
4 kΩ
16 V
16 V
4 kΩ
100 kΩ
8 V
A AND B OUTPUT
D I/O
V
V
V
CC
CC
CC
16 V
4 kΩ
18 kΩ
Output
40 Ω
100 kΩ
4 kΩ
16 V
8 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
†
absolute maximum ratings
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
CC
Voltage range at any bus I/O terminal (steady state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V
Voltage input range, A and B, (transient pulse through 100 Ω, see Figure 12) . . . . . . . . . . . . . . –30 V to 30 V
Voltage range at any D or DIR terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
+ 0.5 V
CC
Electrostatic discharge: Human body model (A, B, GND) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV
Charged-device model (all pins) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Power Dissipation Rating Table
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114–A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
POWER DISSIPATION RATING TABLE
}
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DB
995 mW
8.0 mW/°C
11.8 mW/°C
635 mW
950 mW
515 mW
770 mW
DW
1480 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM
MAX
5.25
12
UNIT
V
Supply voltage, V
CC
4.75
–7
2
5
Voltage at any bus I/O terminal
A, B
V
High-level input voltage, V
V
CC
0.8
IH
D, DIR
V
V
Low-level input voltage, V
0
IL
Differential input voltage, V
A with respect to B
Driver
–12
–60
–8
0
12
60
8
ID
Output current
mA
Receiver
SN75LBC170
SN65LBC170
70
85
Operating free-air temperature, T
°C
A
–40
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
DRIVER SECTION
electrical characteristics over recommended operating conditions
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
D and DIR
I = 18 mA
–1.5
0
–0.7
IK
I
Open-circuit output voltage (single-ended)
A or B, No load
No load
V
V
V
O
CC
3.8
1
4.3
1.6
1.6
CC
2.4
Steady-state differential output voltage
R
= 54 Ω,
See Figure 1
|V
|
V
L
OD(SS)
‡
magnitude
With common-mode loading, See Figure 2
1
2.4
0.2
2.8
0.2
Change in differential output voltage
magnitude, | V | – |V
∆V
–0.2
2
OD
|
OD(H) OD(L)
V
V
R
C
= 54 Ω,
= 50 pF
L
L
V
Steady-state common-mode output voltage
2.4
See Figure 1
OC(SS)
Change in steady-state common-mode output
∆V
OC(SS)
–0.2
voltage (V
OC(H)
– V )
OC(L)
I
I
I
I
Input current
D, DIR
–100
–700
–250
100
900
250
20
µA
µA
I
Output current with power off
Short-circuit output current
Supply current (driver enabled)
V
V
= 0 V,
V
= –7 V to 12 V
O
CC
= –7 V to 12 V, See Figure 7
O
O
mA
mA
OS
D at 0 V or V
CC
,
DIR at V , No load
CC
14
CC
†
‡
All typical values are at V
= 5 V and T = 25°C.
A
CC
may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
The minimum V
OD
lower output signal into account in determining the maximum signal-transmission distance.
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
4
TYP
8.5
8.5
7.5
7.5
MAX
12
11
11
11
2
UNIT
t
Differential output propagation delay, low-to high
Differential output propagation delay, high-to-low
Differential output rise time
PLH
t
4
PHL
t
r
t
f
3
Differential output fall time
3
R
= 54 Ω,
C
= 50 pF, See Figure 3
L
ns
L
t
Pulse skew | (t ) |
– t
sk(p)
PLH PHL
§
t
Output skew
Part-to-part skew
1.5
2
sk(o)
¶
t
sk(pp)
t
Differential output propagation delay, low-to high
Differential output propagation delay, high-to-low
Differential output rise time
3
3
3
3
7
7.5
7.5
7.5
10
10
12
12
3
PLH
t
PHL
t
r
t
f
See Figure 4,
(HVD SCSI double-terminated load)
Differential output fall time
ns
t
Pulse skew | (t ) |
– t
sk(p)
PLH PHL
§
t
Output skew
Part-to-part skew
1.5
2.5
25
25
25
25
sk(o)
¶
t
sk(pp)
t
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
15
18
10
17
PZH
See Figure 5
See Figure 6
ns
ns
t
PHZ
t
PZL
t
PLZ
§
¶
Output skew (t
sk(o)
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
Part-to-part skew (t
sk(pp)
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
RECEIVER SECTION
electrical characteristics over recommended operating conditions
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
0.2
IT+
IT–
hys
OH
OL
V
–0.2
See Figure 8
Hysteresis voltage (V
IT+
– V
)
40
4.7
0.2
mV
IT–
High-level output voltage
Low-level output voltage
V
V
= 200 mV, I
OH
= –8 mA, See Figure 8
= –8 mA, See Figure 8
V = 12 V
4
0
V
ID
CC
0.4
V
= –200 mV, I
OL
ID
0.9
I
I
I
Line input current
Input resistance
Other input = 0 V
mA
V = –7 V
I
–0.7
R
A, B
12
kΩ
I
I
Supply current (receiver enabled)
= 5 V and T = 25°C.
A, B, D, and DIR open
16
mA
CC
†
All typical values are at V
CC
A
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
7
TYP
MAX
16
16
3
UNIT
ns
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Receiver output rise time
PLH
t
7
ns
PHL
See Figure 9
t
r
1.3
1.3
26
ns
t
f
Receiver output fall time
3
ns
t
Receiver output enable time to high level
Receiver output disable time from high level
Receiver output enable time to low level
Receiver output enable time to high level
40
40
40
40
2
PZH
See Figure 10
See Figure 11
ns
ns
t
PHZ
t
29
PZL
t
PLZ
t
Pulse skew (| t
– t
|)
ns
ns
ns
sk(p)
PLH PHL
‡
t
Output skew
Part-to-part skew
Output skew (t
1.5
3
sk(o)
§
t
sk(pp)
‡
§
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
sk(o)
Part-to-part skew (t
sk(pp)
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
I
O
27 Ω
27 Ω
I
I
†
V
OD
50 pF
0 V or 3 V
I
O
V
O
V
OC
V
O
† Includes probe and jig capacitance
Figure 1. Driver Test Circuit, V
and V
Without Common-Mode Loading
OC
OD
375 Ω
V
OD
V
TEST
= –7 V to 12 V
Input
60 Ω
375 Ω
V
TEST
Figure 2. Driver Test Circuit, V
With Common-Mode Loading
OD
3 V
0 V
Input
1.5 V
1.5 V
R
= 54 Ω
L
}
C
= 50 pF
V
OD
L
t
t
PHL
Signal
Generator
PLH
50 Ω
{
V
OD(H)
90% 90%
Output
0 V
10%
10%
V
OD(L)
t
t
f
r
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes probe and jig capacitance
Figure 3. Driver Switching Test Circuit and Waveforms, 485-Loading
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
5 V
0 V
S1
3 V
0 V
375 Ω
75 Ω
‡
60 pF
Input
1.5 V
1.5 V
165 Ω
165 Ω
t
t
PHL
PLH
V
OD
V
OD(H)
90% 90%
Signal
Generator
Output
0 V
V
50 Ω
10%
10%
{
OD(L)
‡
t
t
f
60 pF
r
375 Ω
5 V
0 V
S2
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes probe and jig capacitance
Figure 4. Driver Switching Test Circuit and Waveforms, HVD SCSI-Loading (double terminated)
A
3 V
0 V
Input
S1
1.5 V
1.5 V
Output
{
0 V or 3 V
B
§
= 50 pF
R
= 110 Ω
0.5 V
C
L
t
L
PZH
Input
V
OH
Output
2.3 V
0 V
}
Generator
50 Ω
t
PHZ
† 3 V if testing A output, 0 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
w Includes probe and jig capacitance
Figure 5. Driver Enable/Disable Test, High Output
5 V
3 V
A
R
= 110 Ω
Input
L
1.5 V
1.5 V
S1
0 V
5 V
{
0 V or 3 V
Output
t
B
t
PZL
PLZ
§
= 50 pF
C
L
Output
Input
2.3 V
V
OL
‡
Generator
50 Ω
0.5 V
† 0 V if testing A output, 3 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
w Includes probe and jig capacitance
Figure 6. Driver Enable/Disable Test, Low Output
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
I
OS
V
O
I
O
V
ID
Voltage
Source
V
O
Figure 7. Driver Short-Circuit Test
Figure 8. Receiver DC Parameters
{
Generator
50 Ω
50 Ω
Input B
3 V
0 V
A
B
I
O
1.5 V
D
Input A
V
ID
t
t
PHL
V
O
PLH
}
C
= 15 pF
{
L
Generator
V
V
OH
90% 90%
Output
1.5 V
10%
1.5 V
10%
OL
t
t
f
r
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
‡ Includes probe and jig capacitance
r
f
o
Figure 9. Receiver Switching Test Circuit and Waveforms
V
CC
A
B
1.5 V
3 V
0 V
1 kΩ
D
DIR
1.5 V
1.5 V
}
C
= 15 pF
L
DIR
t
t
PZH
PHZ
–0.5 V
V
OH
V
OH
1.5 V
{
Generator
50 Ω
GND
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes probe and jig capacitance
Figure 10. Receiver Enable/Disable Test, High Output
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
V
CC
A
B
3 V
0 V
–1.5 V
DIR
t
1 kΩ
D
1.5 V
1.5 V
}
C
= 15 pF
L
t
DIR
PZL
PLZ
V
CC
1.5 V
V
OL
+ 0.5 V
{
V
Generator
OL
50 Ω
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes probe and jig capacitance
Figure 11. Receiver Enable/Disable Test, Low Output
V
100 Ω
Pulse
TEST
0 V
15 µs
Generator,
–V
TEST
1.5 ms
15-µs Duration,
1% Duty Cycle
Figure 12. Test Circuit and Waveform, Transient Over Voltage Test
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
4
2.5
3.5
3
V
CC
= 5.25 V
2
V
CC
= 5 V
V
CC
= 5.25 V
2.5
2
1.5
V
CC
= 5 V
V
CC
= 4.75 V
1
0.5
0
1.5
1
V
= 4.75 V
CC
0.5
0
0
20
40
60
80
100
–60 –40 –20
0
20
40
60
80
100
I
O
– Output Current – mA
T
A
– Free-Air Temperature – °C
Figure 13
Figure 14
DRIVER PROPAGATION DELAY
vs
SUPPLY CURRENT
vs
SIGNALING RATE
FREE-AIR TEMPERATURE
12
11
10
165
160
155
All 3 Channels Driving
R
C
= 54 Ω,
= 50 pF (Each Channel),
L
L
Pseudorandom NRZ Data
SCSI Load
9
8
7
6
5
4
150
145
140
135
RS–485 Load
–40
–20
0
20
40
60
80
0.1
1
10
100
T
– Free-Air Temperature – °C
A
Signaling Rate – Mbps
Figure 15
Figure 16
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
RECEIVER PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
800
600
12
11
10
V
= 0 V
V
CC
t
t
PHL
PLH
400
200
0
= 5 V
CC
9
8
7
6
5
4
–200
–400
–600
–10
–5
0
5
10
15
–40
–20
0
20
40
60
80
Bus Input Voltage – V
T
A
– Free-Air Temperature°C
Figure 17
Figure 18
SN65LBC170
(as Driver)
SN65LBC170
(as Receiver)
15 Meters, Cat. 5
Twisted-Pair Cable
Signal
Generator
100 Ω
15 pF
Figure 19. Circuit Diagram for Signaling Characteristics
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
25 ns
Receiver Output
(5 V/div)
Figure 20. Signal Waveforms at 30 Mbps
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
12.5 ns
Receiver Output
(5 V/div)
Figure 21. Eye Patterns, Pseudorandom Data at 30 Mbps
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
25 ns
Receiver Output
(5 V/div)
Figure 22. Signal Waveforms at 50 Mbps
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
12.5 ns
Receiver Output
(5 V/div)
Figure 23. Eye Patterns, Pseudorandom Data at 50 Mbps
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /D 09/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–ā8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/D 01/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SSOP
SOIC
SOIC
SSOP
SSOP
SSOP
SOIC
SOIC
Drawing
SN65LBC170DB
SN65LBC170DBR
SN65LBC170DW
SN65LBC170DWR
SN75LBC170DB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
DB
16
16
20
20
16
16
16
20
20
80
2000
25
None
None
None
None
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
DB
DW
DW
DB
2500
80
SN75LBC170DBR
SN75LBC170DBRG4
SN75LBC170DW
SN75LBC170DWR
DB
2000
2000
50
DB
Call TI
Call TI
DW
DW
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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