SN65LBC176QDRQ1 [TI]
汽车类差动总线收发器 | D | 8 | -40 to 125;
| 型号： | SN65LBC176QDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类差动总线收发器 | D | 8 | -40 to 125 驱动 信息通信管理 光电二极管 接口集成电路 总线收发器 驱动器 |
| 文件： | 总20页 (文件大小：1167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LBC176-Q1
ZHCSRM9B – OCTOBER 2003 – REVISED JANUARY 2023
SN65LBC176-Q1 差分总线收发器
1 特性
2 说明
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符合汽车应用要求
SN65LBC176 差分总线收发器是单片集成电路，旨在
实现多点总线传输线路上的双向数据通信。它专为平衡
传输线路而设计，符合 ANSI 标准 RS-485 和 ISO
8482:1987(E)。
双向收发器
符合或超出 ANSI 标准 RS-485 和 ISO
8482:1987(E) 的要求
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高速低功耗 LinBiCMOS 电路
专为在串行和并行应用中实现高速运行而设计
低偏斜
SN65LBC176 将一个三态差分线路驱动器和一个差分
输入线路接收器组合在一起，这两个器件由一个 5V 单
电源供电。驱动器和接收器分别具有高电平有效和低电
平有效使能端，它们可以在外部连接在一起以用作方向
控制。驱动器差分输出端和接收器差分输入端在内部连
接以形成差分输入/输出 (I/O) 总线端口，该端口用于在
禁用驱动器或 VCC = 0 时为总线提供最小负载。该端
口具有较宽的正负共模电压范围，使得该器件适用于合
用线应用。可以通过禁用驱动器和接收器来实现超低的
器件待机电源电流。德州仪器 (TI) LinASIC 库中的驱
动器和接收器均以单元形式提供。
适用于嘈杂环境中的长距离总线线路上的多点传输
超低禁用电源电流要求：200μA（最大值）
宽正负输入/输出总线电压范围
驱动器输出容量：±60mA
热关断保护
驱动器正负电流限制
开路失效防护接收器设计
接收器输入灵敏度：±200mV（最大值）
接收器输入迟滞：50mV（典型值）
由一个 5V 单电源供电运行
无干扰上电和断电保护
此收发器适用于 ANSI 标准 RS-485 和 ISO 8482:1987
(E) 应用，前提是它们在此数据表的运行条件和特性部
分中已指定。ANSI 标准 RS-485 和 ISO 8482:1987
(E) 中包含的某些限制不符合或无法在整个工作温度范
围内进行测试。
封装信息
器件型号
封装(1)
封装尺寸（标称值）
SN65LBC176-Q1
D (SOIC) (8)
4.90mm x 3.91mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
3
DE
4
D
2
RE
6
1
A
Bus
7
R
B
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SGLS211
SN65LBC176-Q1
ZHCSRM9B – OCTOBER 2003 – REVISED JANUARY 2023
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Table of Contents
1 特性................................................................................... 1
2 说明................................................................................... 1
3 修订历史记录.....................................................................2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions.........................4
5.3 Thermal Resistance Characteristics........................... 5
5.4 Electrical Characteristics - Driver................................5
5.5 Switching Characteristics - Driver ..............................6
5.6 Electrical Characteristics - Reciever........................... 7
5.7 Switching Characteristics - Reciever ......................... 7
Parameter Measurement Information...............................8
6 Detailed Description......................................................11
6.1 Device Functional Modes..........................................11
7 Device and Documentation Support............................12
7.1 Documentation Support............................................ 12
7.2 接收文档更新通知..................................................... 12
7.3 支持资源....................................................................12
7.4 Trademarks...............................................................12
7.5 静电放电警告............................................................ 12
7.6 术语表....................................................................... 12
8 Mechanical, Packaging, and Orderable Information..12
3 修订历史记录
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (October 2003) to Revision B (January 2023)
Page
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添加了封装信息 表、引脚配置和实施、热性能信息 表、器件功能模式、器件和文档支持 部分以及机械、封装
和可订购信息 部分 ............................................................................................................................................. 1
删除了订购信息 表..............................................................................................................................................1
•
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4 Pin Configuration and Functions
R
RE
DE
D
1
2
3
4
8
7
6
5
V
B
A
ꢀ
CC
GND
Not to scale
图 4-1. D Package, SOIC 8 Pins
(Top View)
表 4-1. Pin Functions
NO
NAME
TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
R
RE
DE
D
O
Receive data output
I
I
Receiver enable, active low
Driver enable, active high
Driver data input
I
GND
A
GND
I/O
I/O
P
Device ground
Bus I/O port, A (complementary to B)
Bus I/O port, B(complementary to A)
5 V Supply Pin
B
VCC
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
V
VCC
Supply voltage
7
15
Voltage range at any bus terminal
Input voltage, VI (D, DE, R, or RE)
Operating free-air temperature range
Storage temperature
-10
−0.3
-40
V
VCC + 0.5
125
V
TA
°C
°C
Tstg
-65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal GND.
5.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VCC
Supply voltage
4.75
5
5.25
12
V
V
Voltage at any bus terminal (separately
or common mode),
VI or VIC
-7
V
VIH
VIL
VID
High-level input voltage,
Low-level input voltage,
Differential input voltage(1)
High-level output current
D, DE, and RE
D, DE, and RE
2
V
0.8
±12
60
V
V
Driver
mA
µA
mA
mA
°C
IOH
Receiver
Driver
-400
-60
8
IOL
TA
Low-level output current
Receiver
Operating free-air temperature,
-40
125
(1) Differential input /output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
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5.3 Thermal Resistance Characteristics
SN65LBC176-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
UNIT
R θJA
R θJC
R θJB
ψ JT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
116.7
56.3
63.4
8.8
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψ JB
62.6
n/a
R θJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
5.4 Electrical Characteristics - Driver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input clamp voltage
Output voltage
TEST CONDITIONS
MIN
TYP
MAX
-1.5
6
UNIT
VIK
II = − 18 mA
V
V
V
VO
IO = 0
IO = 0
0
|VOD1
|
Differential output voltage
1.5
6
Vtest = −7 V to 12
V
VOD3
Differential output voltage
Differential output voltage
See Fig 2, (2)
See Fig 1, (2)
1.1
1.1
V
V
V
V
V
|VOD2
|
RL = 54 Ω
Change in magnitude of differential
output voltage(1)
Δ|VOD
|
|
±0.2
-1
RL = 54 Ω or 100 Ω
See Fig 1
VOC
Common-mode output voltage
Change in magnitude of common-
mode output voltage(1)
Δ|VOC
±0.2
VO = 12 V
VO = -7 V
1
-0.8
-100
-100
-250
-150
250
mA
mA
µA
Output disabled,
IO
Output current
(3)
IIH
IIL
High-level input current
Low-level input current
VI = 2.4 V
VI = 0.4 V
VO = -7 V
VO = 0 V
VO = VCC
VO = 12 V
µA
mA
mA
mA
mA
IOS
Short-circuit output current
Supply current
250
Receiver disabled
and driver
enabled
1.75
0.25
mA
mA
VI = 0 or VCC
,
ICC
No Load
Receiver and
driver disabled
(1) Δ | VOD | and Δ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input changes from a high level
to a low level.
(2) This device meets the ANSI Standard RS-485 VOD requirements above 0°C only.
(3) This applies for both power on and off; refer to ANSI Standard RS-485 for exact conditions.
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5.5 Switching Characteristics - Driver
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
ns
td(OD)
tt(OD)
tsk(p)
Differential output delay time
8
31
RL = 54 Ω
Differential output transition time CL = 50 pF
12
ns
See Fig 3
Pulse skew ( | td(ODH) − td(ODL)| )
6
ns
RL = 110 Ω
Output enable time to high level
See Figure 4
tPZH
tPZL
tPHZ
tPLZ
65
ns
ns
ns
ns
RL = 110 Ω
Output enable time to low level
See Figure 5
65
105
105
Output disable time from high
level
RL = 110 Ω
See Figure 4
RL = 110 Ω
See Figure 5
Output disable time from low level
(1) All typical values are at VCC = 5 V, TA = 25°C.
5.5.1 Symbol Equivalents
Data Sheet Parameter
RS-485
Voa, Vob
VO
VO
| VOD1
| VOD2
| VOD3
Δ | VOD
VOC
|
|
|
Vt (RL = 54 Ω)
Vt (test termination measurement 2)
| | Vt | − | Vt | |
|
|
| VOS
|
Δ | VOC
IOS
| VOS - VOS
None
|
IO
Iia, Iib
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5.6 Electrical Characteristics - Reciever
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Positive-going input threshold
voltage
VIT+
VIT-
VO = 2.7 V
VO = 0.5 V
IO = -0.4 mA
IO = 8 mA
0.2
V
Negative-going input threshold
voltage
-0.2(2)
V
Vhys
VIK
Hysteresis voltage (VIT+ − VIT−)
Enable-input clamp voltage
(see Figure 4)
II = -18 mA
50
mV
V
-1.5
VID = 200 mV
IOH = -400 µA
VOH
High-level output voltage
Low-level output voltage
See Fig 6
See Fig 6
2.7
V
V
VID = 200 mV
IOL = 8 mA
VOL
IOZ
0.45
High-impedance-state output current VO = 0.4 V to 2.4 V
±20
1
µA
mA
mA
µA
µA
kΩ
VI = 12 V
VI = -7
Other input = 0
II
Line input current
V(3)
-0.8
-100
-100
IIH
IIL
rI
High-level enable-input current
Low-level enable-input current
Input resistance
VIH = 2.7 V
VIL = 0.4 V
12
Receiver disabled
and driver
enabled
3.9
mA
mA
VI = 0 or VCC
No Load
,
ICC
Supply current
Receiver and
driver disabled
0.25
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for
common-mode input voltage and threshold voltage levels only.
(3) This applies for both power on and off; refer to ANSI Standard RS-485 for exact conditions.
5.7 Switching Characteristics - Reciever
over operating free-air temperature range (unless otherwise noted), CL = 15 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, low- to
high-level single-ended output
tPLH
tPHL
11
37
ns
VID = -1.5 V to 1.5 V
See Figure 7
Propagation delay time, high- to
low-level single-ended output
11
37
ns
tsk(p)
tPZH
tPZL
Pulse skew ( | td(ODH) − td(ODL)| )
Output enable time to high level
Output enable time to low level
10
35
35
ns
ns
ns
See Figure 8
See Figure 8
Output disable time from high
level
tPHZ
tPLZ
35
35
ns
ns
Output disable time from low level
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Parameter Measurement Information
27 W
VOD
0 or 3 V
27 W VOC
图 6-1. Driver VOD and VOC
Vtest
R1
375W
Y
D
RL = 60W
VOD
0 V or 3 V
Z
R2
375W
- 7 V < Vtest < 12 V
Vtest
图 6-2. Driver VOD3
3 V
Input
1.5 V
1.5 V
CL = 50 pF
(see Note B)
0 V
RL = 54 W
tPLH
tPHL
Generator
(see Note A)
VO
50 W
» 1.5 V
90%
50%
tr
Output
10%
» –1.5 V
tf
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO
=
50 Ω.
B. CL includes probe and jig capacitance.
图 6-3. Driver Test Circuit and Voltage Waveforms
Output
3 V
S1
Input
1.5 V 1.5 V
3 V
0 V
0.5 V
tPZH
RL = 110 W
CL = 50 pF
VOH
(see Note B)
Generator
(see Note A)
Output
50 W
2.3 V
tPHZ
V
off » 0 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO
=
50 Ω.
B. CL includes probe and jig capacitance.
图 6-4. Driver Test Circuit and Voltage Waveforms
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5 V
3 V
1.5 V
1.5 V
Input
RL = 110 W
0 V
tPLZ
S1
Output
0 V
tPZL
CL = 50 pF
(see Note B)
5 V
0.5 V
Generator
(see Note A)
50 W
2.3 V
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO
=
50 Ω.
B. CL includes probe and jig capacitance.
图 6-5. Driver Test Circuit and Voltage Waveforms
IO
VID
VO
图 6-6. Receiver VOH and VOL
3 V
Input
1.5 V
1.5 V
Output
0 V
Generator
(see Note A)
50 W
tPHL
1.5 V
0 V
tPLH
Output
CL = 10 pF
(see Note B)
VOH
90%
1.3 V
10%
1.3 V
VOL
tF
tR
TEST CIRCUIT
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO
=
50 Ω.
B. CL includes probe and jig capacitance.
图 6-7. Receiver Test Circuit and Voltage Waveforms
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S1
1.5 V
S2
2 kW
–1.5 V
5 V
CL = 10 pF
(see Note B)
5 kW
Generator
(see Note A)
50 W
S3
TEST CIRCUIT
3 V
3 V
S1 to -1.5 V
S2 Closed
S3 Open
S1 to 1.5 V
S2 Open
S3 Closed
0 V
Input
Input
1.5 V
1.5 V
0 V
tPZH
tPZL
VOH
» 4.5 V
1.5 V
Output
Output
1.5 V
0 V
VOL
3 V
3 V
S1 to 1.5 V
S2 Closed
S3 Closed
S1 to -1.5 V
S2 Closed
S3 Closed
Input
Input
1.5 V
1.5 V
0 V
0 V
tPHZ
tPLZ
» 1.3 V
VOH
0.5 V
Output
Output
0.5 V
VOL
» 1.3 V
VOLTAGE WAVEFORMS
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO
=
50 Ω.
B. CL includes probe and jig capacitance.
图 6-8. Receiver Test Circuit and Voltage Waveforms
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6 Detailed Description
6.1 Device Functional Modes
表 6-1. Function Table - Driver
Input(1)
Output
Outputs
D
H
L
DE
H
A
H
L
B
L
H
H
Z
X
L
Z
(1) H = high level, L = low level, ? = indeterminate, X = irrelevant, Z
= high impedance (off)
表 6-2. Function Table - Receiver
Differential Inputs
ENABLE
Output
A−B
RE
L
R
H
?
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V
X
L
L
L
H
L
Z
H
Open
EQUIVALENT OF D, RE, and
DE INPUTS
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
V
CC
V
CC
V
CC
3 kΩ
NOM
100 kΩ NOM
A Port Only
A or B
Output
Input
18 kΩ
NOM
100 kΩ NOM
1.1 kΩ
NOM
B Port Only
图 6-1. Schematics of Inputs and Outputs
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7 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
7.1 Documentation Support
7.1.1 Related Documentation
7.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
7.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
7.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
7.5 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
7.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: SN65LBC176-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65LBC176QDRG4Q1
SN65LBC176QDRQ1
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
J176Q1
J176Q1
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
OTHER QUALIFIED VERSIONS OF SN65LBC176-Q1 :
Catalog : SN65LBC176
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LBC176QDRG4Q1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
340.5 336.1 25.0
SN65LBC176QDRG4Q1
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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